ATA6623_09

Features • • • • • Supply Voltage up to 40V Operating Voltage VS = 5V to 27V Typically 10 µA Supply Current During Sleep Mode Typically 57 µA Supply Current in Silent Mode Linear Low-drop Voltage Regulator: – Normal, Fail-safe, and Silent Mode – ATA6623: VCC = 3.3V ±2% – ATA6625: VCC = 5.0V ±2% – Sleep Mode: VCC is Switched Off VCC Undervoltage Detection with Reset Open Drain Output NRES (4 ms Reset Time) Voltage Regulator is Short-circuit and Over-temperature Protected LIN Physical Layer According to LIN 2.0, 2.1 and SAEJ2602-2 Wake-up Capability via LIN Bus (90 µs Dominant) TXD Time-out Timer Bus Pin is Overtemperature and Short-circuit Protected versus GND and Battery Advanced EMC and ESD Performance ESD HBM 8 kV at Pins LIN and VS Following STM5.1 Interference and Damage Protection According to ISO/CD7637 Package: SO8 • • • • • • • • • • LIN Bus Transceiver with Integrated Voltage Regulator ATA6623 ATA6625 1. Description ATA6623/ATA6625 is a fully integrated LIN transceiver, designed according to the LIN specification 2.0 and 2.1, with a low-drop voltage regulator (3.3V/5V/50 mA). The combination of voltage regulator and bus transceiver makes it possible to develop simple, but powerful, slave nodes in LIN Bus systems. ATA6623/ATA6625 is designed to handle the low-speed data communication in vehicles (for example, in convenience electronics). Improved slope control at the LIN driver ensures secure data communication up to 20 kBaud with an RC oscillator for the protocol handling. The bus output is designed to withstand high voltage. Sleep Mode (voltage regulator switched off) and Silent Mode (communication off; VCC voltage on) guarantee minimized current consumption. 4957G–AUTO–09/09 Figure 1-1. Block Diagram ATA6623/25 VCC Normal Mode 1 VS RXD 5 Receiver + RF-filter 4 LIN VCC Wake-up bus timer Short circuit and overtemperature protection TXD 6 TXD Time-out timer Slew rate control 8 EN 2 Control unit GND 3 Sleep mode VCC switched off Normal/Silent/ Fail-safe Mode 3.3V/50 mA/±2% 5V/50 mA/±2% Undervoltage reset 7 VCC NRES 2. Pin Configuration Figure 2-1. Pinning SO8 VS EN GND LIN 1 2 3 4 8 7 6 5 VCC NRES TXD RXD Table 2-1. Pin 1 2 3 4 5 6 7 8 Pin Description Symbol VS EN GND LIN RXD TXD NRES VCC Function Battery supply Enables Normal Mode if the input is high Ground, heat sink LIN bus line input/output Receive data output Transmit data input Output undervoltage reset, low at reset Output voltage regulator 3.3V/5V/50 mA 2 ATA6623/ATA6625 4957G–AUTO–09/09 ATA6623/ATA6625 3. Functional Description 3.1 Physical Layer Compatibility Since the LIN physical layer is independent from higher LIN layers (e.g., LIN protocol layer), all nodes with a LIN physical layer according to revision 2.x can be mixed with LIN physical layer nodes, which are according to older versions (i.e., LIN 1.0, LIN 1.1, LIN 1.2, LIN 1.3) without any restrictions. 3.2 Supply Pin (VS) LIN operating voltage is VS = 5V to 27V. An undervoltage detection is implemented to disable transmission if VS falls below 5V, in order to avoid false bus messages. After switching on VS, the IC starts with the Fail-safe Mode and the voltage regulator is switched on (i.e., 3.3V/5V/50 mA). The supply current in Sleep Mode is typically 10 µA and 57 µA in Silent Mode. 3.3 Ground Pin (GND) The IC is neutral on the LIN pin in the event of GND disconnection. It is able to handle a ground shift up to 11.5% of VS. 3.4 Voltage Regulator Output Pin (VCC) The internal 3.3V/5V voltage regulator is capable of driving loads with up to 50 mA, supplying the microcontroller and other ICs on the PCB and is protected against overload by means of current limitation and overtemperature shut-down. Furthermore, the output voltage is monitored and will cause a reset signal at the NRES output pin if it drops below a defined threshold Vthun. 3.5 Undervoltage Reset Output (NRES) If the VCC voltage falls below the undervoltage detection threshold of Vthun, NRES switches to low after tres_f (Figure 6-1 on page 11). Even if VCC = 0V the NRES stays low, because it is internally driven from the VS voltage. If VS voltage ramps down, NRES stays low until VS < 1.5V and then becomes highly resistant. The implemented undervoltage delay keeps NRES low for tReset = 4 ms after VCC reaches its nominal value. 3.6 Bus Pin (LIN) A low-side driver with internal current limitation and thermal shutdown as well as an internal pull-up resistor according to LIN specification 2.x is implemented. The voltage range is from –27V to +40V. This pin exhibits no reverse current from the LIN bus to VS, even in the event of a GND shift or VBatt disconnection. The LIN receiver thresholds are compatible with the LIN protocol specification. The fall time (from recessive to dominant) and the rise time (from dominant to recessive) are slope controlled. 3 4957G–AUTO–09/09 3.7 Input Pin (TXD) In Normal Mode the TXD pin is the microcontroller interface to control the state of the LIN output. TXD must be pulled to ground in order to drive the LIN bus low. If TXD is high or unconnected (internal pull-up resistor), the LIN output transistor is turned off and the bus is in the recessive state. 3.8 Dominant Time-out Function (TXD) The TXD input has an internal pull-up resistor. An internal timer prevents the bus line from being driven permanently in the dominant state. If TXD is forced to low longer than tDOM > 6 ms, the LIN bus driver is switched to the recessive state. To reactivate the LIN bus driver, switch TXD to high (> 10 µs). 3.9 Output Pin (RXD) The pin reports the state of the LIN-bus to the microcontroller. LIN high (recessive state) is reported by a high level at RXD; LIN low (dominant state) is reported by a low level at RXD. The output has an internal pull-up resistor with typically 5 kΩ to VCC. The AC characteristics are measured with an external load capacitor of 20 pF. The output is short-circuit protected. In Unpowered Mode (that is, VS = 0V), RXD is switched off. 3.10 Enable Input Pin (EN) The Enable Input pin controls the operation mode of the device. If EN is high, the circuit is in Normal Mode, with transmission paths from TXD to LIN and from LIN to RXD both active. The VCC voltage regulator operates with 3.3V/5V/50 mA output capability. If EN is switched to low while TXD is still high, the device is forced to Silent Mode. No data transmission is then possible, and the current consumption is reduced to IVS typ. 57 µA. The VCC regulator has its full functionality. If EN is switched to low while TXD is low, the device is forced to Sleep Mode. No data transmission is possible, and the voltage regulator is switched off. 4 ATA6623/ATA6625 4957G–AUTO–09/09 ATA6623/ATA6625 4. Mode of Operation Figure 4-1. Mode of Operation Unpowered Mode VBatt = 0V b a a: VS > 5V b: VS < 4V c: Bus wake-up event d: NRES switches to low Fail-safe Mode b d EN = 1 Go to silent command VCC: 3.3V/5V/50 mA with undervoltage monitoring Communication: OFF EN = 1 c b c+d b Silent Mode EN = 0 TXD = 1 Normal Mode VCC: 3.3V/5V/50 mA with undervoltage monitoring EN = 0 Communication: ON TXD = 0 Sleep Mode Local wake-up event EN = 1 VCC: 3.3V/5V/50 mA with undervoltage monitoring Communication: OFF Go to sleep command VCC: switched off Communication: OFF Table 4-1. Mode of Operation Fail safe Normal Silent Sleep Mode of Operation Transceiver OFF ON OFF OFF VCC 3.3V/5V 3.3V/5V 3.3V/5V 0V RXD High, Except after wake-up LIN depending High 0V LIN Recessive TXD depending Recessive Recessive 5 4957G–AUTO–09/09 4.1 Normal Mode This is the normal transmitting and receiving Mode of the LIN Interface, in accordance with LIN specification 2.x. The VCC voltage regulator operates with a 3.3V/5V output voltage, with a low tolerance of ±2% and a maximum output current of 50 mA. If an undervoltage condition occurs, NRES is switched to low and the IC changes its state to Fail-safe Mode. 4.2 Silent Mode A falling edge at EN while TXD is high switches the IC into Silent Mode. The TXD Signal has to be logic high during the Mode Select window (Figure 4-2 on page 7). The transmission path is disabled in Silent Mode. The overall supply current from V Batt i s a combination of the IVSsi = 57 µA plus the VCC regulator output current IVCC. The 3.3V/5V regulator with 2% tolerance can source up to 50 mA. In Silent Mode the internal slave termination between pin LIN and pin VS is disabled, and only a weak pull-up current (typically 10 µA) between pin LIN and pin VS is present. The Silent Mode can be activated independently from the current level on pin LIN. If an undervoltage condition occurs, NRES is switched to low and the IC changes its state to Fail-safe Mode. A voltage less than the LIN Pre-wake detection V LINL a t pin LIN activates the internal LIN receiver and switches on the internal slave termination between the LIN pin and the VS pin. A falling edge at the LIN pin followed by a dominant bus level maintained for a certain time period (tbus) and the following rising edge at pin LIN (see Figure 4-3 on page 7) results in a remote wake-up request. The device switches from Silent Mode to Fail-safe Mode, and the remote wake-up request is indicated by a low level at pin RXD to interrupt the microcontroller (Figure 4-3 on page 7). EN high can be used to switch directly to Normal Mode. 6 ATA6623/ATA6625 4957G–AUTO–09/09 ATA6623/ATA6625 Figure 4-2. Switch to Silent Mode Normal Mode Silent Mode EN TXD Mode select window td = 3.2 µs NRES VCC Delay time silent mode td_silent = maximum 20 µs LIN LIN switches directly to recessive mode Figure 4-3. LIN Wake-up Waveform Diagram from Silent Mode Bus wake-up filtering time tbus Fail-safe mode Normal mode LIN bus RXD High Low VCC Silent mode 3.3V/5V/50 mA Fail-safe mode 3.3V/5V/50 mA Normal mode EN High EN NRES Undervoltage detection active 7 4957G–AUTO–09/09 4.3 Sleep Mode A falling edge at EN while TXD is low switches the IC into Sleep Mode. The TXD Signal has to be logic low during the Mode Select window (Figure 4-4 on page 8). To avoid influencing the LIN-pin during the switch to sleep mode, it is possible to switch the EN up to 3.2 µs earlier to LOW than the TXD. Even if the two falling edges at TXD and EN occur at the same time, the LIN line will remain uninfluenced. In Sleep Mode the transmission path is disabled. The supply current IVSsleep from VBatt is typically 10 µA. The VCC regulator is switched off, NRES and RXD are low. The internal slave termination between pin LIN and pin VS is disabled, only a weak pull-up current (typically 10 µA) between pin LIN and pin VS is present. Sleep Mode can be activated independently from the current level on pin LIN. A voltage less than the LIN Pre-wake detection V LINL a t pin LIN activates the internal LIN receiver and switches on the internal slave termination between the LIN pin and the VS pin. A falling edge at the LIN pin followed by a dominant bus level maintained for a certain time period (tbus) and a following rising edge at pin LIN results in a remote wake-up request. The device switches from Sleep Mode to Fail-safe Mode. The VCC regulator is activated, and the remote wake-up request is indicated by a low level at the RXD pin to interrupt the microcontroller (Figure 4-5 on page 9). EN high can be used to switch directly from Sleep to Fail-safe Mode. If EN is still high after VCC ramp up and undervoltage reset time, the IC switches to Normal Mode. Figure 4-4. Switch to Sleep Mode Normal Mode Sleep Mode EN Mode select window TXD td = 3.2 µs NRES VCC Delay time sleep mode td_sleep = maximum 20 µs LIN LIN switches directly to recessive mode 8 ATA6623/ATA6625 4957G–AUTO–09/09 ATA6623/ATA6625 Figure 4-5. LIN Wake-up Diagram from Sleep Mode Bus wake-up filtering time tbus Fail-safe Mode Normal Mode LIN bus RXD Low or floating Low VCC voltage regulator On state Off state Regulator wake-up time EN High EN Reset time NRES Low or floating Microcontroller start-up time delay 4.4 Fail-safe Mode At system power-up the device automatically switches to Fail-safe Mode. The voltage regulator is switched on (VCC = 3.3V/5V/50 mA), (see Figure 6-1 on page 11). The NRES output switches to low for tres = 4 ms and gives a reset to the microcontroller. LIN communication is switched off. The IC stays in this mode until EN is switched to high, and changes then to the Normal Mode. A power down of VBatt (VS < 4V) during Silent- or Sleep Mode switches the IC into the Fail-safe Mode after power up. A logic low at NRES switches the IC into Fail-safe Mode directly. 4.5 Unpowered Mode If you connect battery voltage to the application circuit, the voltage at the VS pin increases according to the block capacitor (see Figure 6-1 on page 11). After VS is higher than the VS undervoltage threshold VSth, the IC mode changes from Unpowered Mode to Fail-safe Mode. The VCC output voltage reaches its nominal value after tVCC. This time, tVCC, depends on the VCC capacitor and the load. NRES is low for the reset time delay tReset; no mode change is possible during this time. 9 4957G–AUTO–09/09 5. Fail-safe Features • During a short-circuit at LIN to VBattery, the output limits the output current to IBUS_lim. Due to the power dissipation, the chip temperature exceeds TLINoff and the LIN output is switched off. The chip cools down and after a hysteresis of Thys, switches the output on again. RXD stays on high because LIN is high. During LIN overtemperature switch-off, the VCC regulator is working independently. • During a short-circuit from LIN to GND the IC can be switched into Sleep or Silent Mode. If the short-circuit disappears, the IC starts with a remote wake-up. • The reverse current is very low < 2 µA at pin LIN during loss of VBatt. This is optimal behavior for bus systems where some slave nodes are supplied from battery or ignition. • During a short circuit at VCC, the output limits the output current to IVCClim. Because of undervoltage, NRES switches to low and sends a reset to the microcontroller. The IC switches into Fail-safe Mode. If the chip temperature exceeds the value TVCCoff, the VCC output switches off. The chip cools down and after a hysteresis of Thys, switches the output on again. Because of Fail-safe Mode, the VCC voltage will switch on again although EN is switched off from the microcontroller. The microcontroller can then start with normal operation. • Pin EN provides a pull-down resistor to force the transceiver into Recessive Mode if EN is disconnected. • Pin RXD is set floating if VBatt is disconnected. • Pin TXD provides a pull-up resistor to force the transceiver into Recessive Mode if TXD is disconnected. • If TXD is short-circuited to GND, it is possible to switch to Sleep Mode via ENABLE after tdom > 20 ms. 10 ATA6623/ATA6625 4957G–AUTO–09/09 ATA6623/ATA6625 6. Voltage Regulator Figure 6-1. VCC Voltage Regulator: Ramp Up and Undervoltage VS 12V 5.5V/3.8V VCC 5V/3.3V Vthun tVCC NRES 5V/3.3V tReset tres_f The voltage regulator needs an external capacitor for compensation and to smooth the disturbances from the microcontroller. It is recommended to use an electrolythic capacitor with C > 1.8 µF and a ceramic capacitor with C = 100 nF. The values of these capacitors can be varied by the customer, depending on the application. With this special SO8 package (fused lead frame to pin 3) an Rthja of 80 K/W is achieved. Therefore, it is recommended to connect pin 3 with a wide GND plate on the printed board to get a good heat sink. The main power dissipation of the IC is created from the V CC o utput current IVCC , which is needed for the application. Figure 6-2 shows the safe operating area of the ATA6623/ATA6625. 11 4957G–AUTO–09/09 Figure 6-2. Power Dissipation: Save Operating Area versus VCC Output Current and Supply Voltage VS at Different Ambient Temperatures Due to Rthja = 80 K/W 60.00 50.00 40.00 Tamb = 85°C Tamb = 95°C Tamb = 105°C 30.00 20.00 10.00 0.00 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 IVCC (mA) VS (V) To program the microcontroller it may be necessary to supply the VCC output via an external power supply while the VS Pin of the system basis chip is disconnected. This issue does not occur with the system basis chip. 12 ATA6623/ATA6625 4957G–AUTO–09/09 ATA6623/ATA6625 7. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Supply voltage VS Pulse time ≤ 500 ms Ta = 25°C Output current IVCC ≤ 50 mA Pulse time ≤ 2 min Ta = 25°C Output current IVCC ≤ 50 mA Logic pins (RxD, TxD, EN, NRES) Output current NRES LIN - DC voltage VCC - DC voltage ESD according to IBEE LIN EMC Test specification 1.0 following IEC 61000-4-2 - Pin VS, LIN to GND ESD HBM following STM5.1 with 1.5 kΩ/100 pF - Pin VS, LIN to GND HBM ESD ANSI/ESD-STM5.1 JESD22-A114 AEC-Q100 (002) CDM ESD STM 5.3.1 Machine Model ESD AEC-Q100-RevF(003) Junction temperature Storage temperature Tj Ts INRES –27 –0.3 Symbol VS VS Min. –0.3 Typ. Max. +40 +40 Unit V V VS –0.3 27 +5.5 +2 +40 +5.5 V V mA V V ±6 KV ±8 ±3 KV KV ±750 ±200 –40 –55 +150 +150 V V °C °C 8. Thermal Characteristics Parameters Thermal resistance junction to ambient (free air) Special heat sink at GND (pin 3) on PCB Thermal shutdown of VCC regulator Thermal shutdown of LIN output Thermal shutdown hysteresis Symbol Rthja Rthja TVCCoff TLINoff Thys 150 150 80 160 160 10 170 170 Min. Typ. Max. 145 Unit K/W K/W °C °C °C 13 4957G–AUTO–09/09 9. Electrical Characteristics 5V < VS < 27V, –40°C < Tj < 150°C; unless otherwise specified all values refer to GND pins. No. 1 1.1 Parameters VS Pin Nominal DC voltage range Sleep Mode VLIN > VS – 0.5V VS < 14V (Tj = 25°C) Sleep Mode VLIN > VS – 0.5V VS < 14V (Tj = 125°C) Bus recessive VS < 14V (Tj = 25°C) Without load at VCC Bus recessive VS < 14V (Tj = 125°C) Without load at VCC VS VS IVSsleep 5 13.5 27 V A Test Conditions Pin Symbol Min. Typ. Max. Unit Type* VS 3 10 14 µA A 1.2 Supply current in Sleep Mode VS IVSsleep 5 11 16 µA A VS IVSsi 47 57 67 µA A 1.3 Supply current in Silent Mode VS IVSsi 56 66 76 µA A 1.4 Bus recessive Supply current in Normal VS < 14V Mode Without load at VCC Bus dominant Supply current in Normal VS < 14V Mode VCC load current 50 mA Supply current in Fail-safe Mode VS undervoltage threshold VS undervoltage threshold hysteresis RXD Output Pin Low level output sink current Normal Mode VLIN = 0V VRXD = 0.4V Bus recessive VS < 14V Without load at VCC VS IVSrec 0.3 0.8 mA A 1.5 VS IVSdom 50 53 mA A 1.6 VS IVSspeed VSth VSth_hys 200 500 µA A 1.7 1.8 2 2.1 2.2 2.3 3 3.1 3.2 3.3 3.4 VS VS 4.0 4.5 0.2 5 V V A A RXD RXD RXD TXD TXD IRXD VRXDL RRXD VTXDL VTXDH RTXD ITXD 1.3 2.5 8 0.4 mA V kΩ V V kΩ µA A A A A A A A Low level output voltage IRXD = 1 mA Internal resistor to VCC TXD Input Pin Low level voltage input High level voltage input Pull-up resistor High level leakage current VTXD = 0V VTXD = VCC 3 –0.3 2 125 –3 5 7 +0.8 VCC + 0.3V TXD TXD 250 400 +3 *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 14 ATA6623/ATA6625 4957G–AUTO–09/09 ATA6623/ATA6625 9. Electrical Characteristics (Continued) 5V < VS < 27V, –40°C < Tj < 150°C; unless otherwise specified all values refer to GND pins. No. 4 4.1 4.2 4.3 4.4 5 5.1 Parameters EN Input Pin Low level voltage input High level voltage input Pull-down resistor Low level input current VEN = VCC VEN = 0V EN EN EN EN VENL VENH REN IEN –0.3 2 50 –3 125 +0.8 VCC + 0.3V 200 +3 V V kΩ µA A A A A Test Conditions Pin Symbol Min. Typ. Max. Unit Type* NRES Open Drain Output Pin VS ≥ 5.5V Low level output voltage INRES = 1 mA INRES = 250 µA Low level output low Undervoltage reset time 10 kΩ to VCC VCC = 0V VS ≥ 5.5V CNRES = 20 pF NRES VNRESL VNRESL VNRESLL tReset tres_f 2 1.5 4 0.2 0.14 0.2 6 10 V V V ms µs A A A A A 5.2 5.3 5.4 6 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 7 7.1 7.2 7.3 7.4 NRES NRES NRES Reset debounce time for VS ≥ 5.5V CNRES = 20 pF falling edge VCC Voltage Regulator ATA6623 Output voltage VCC Output voltage VCC at low VS Regulator drop voltage Regulator drop voltage Line regulation Load regulation Power supply ripple rejection 4V < VS < 18V (0 mA to 50 mA) 3V < VS < 4V VS > 3V, IVCC = –15 mA VS > 3V, IVCC = –50 mA 4V < VS < 18V 5 mA < IVCC < 50 mA 10 Hz to 100 kHz CVCC = 10 µF VS = 14V, IVCC = –15 mA 0.2Ω < ESR < 5Ω at 100 kHz Referred to VCC VS > 4V Referred to VCC VS > 4V CVCC = 2.2 µF Iload = –5 mA at VCC 5.5V < VS < 18V (0 mA to 50 mA) 4V < VS < 5.5V VS > 4V, IVCC = –20 mA VS > 4V, IVCC = –50 mA VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCnor VCClow VD1 VD2 VCCline VCCload 3.234 VS – VDrop 500 0.5 50 3.366 3.366 200 700 1 2 V V mV mV % % dB A A A A A A C A D A A A Output current limitation VS > 4V Load capacity VCC undervoltage threshold Hysteresis of undervoltage threshold Ramp up time VS > 4V to VCC = 3.3V IVCClim Cload VthunN Vhysthun tVCC –240 1.8 2.8 –160 10 3.2 150 100 250 mA µF V mV µs VCC Voltage Regulator ATA6625 Output voltage VCC Output voltage VCC at low VS Regulator drop voltage Regulator drop voltage VCC VCC VCC VCC VCCnor VCClow VD1 VD2 400 4.9 VS – VD 5.1 5.1 250 600 V V mV mV A A A A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 15 4957G–AUTO–09/09 9. Electrical Characteristics (Continued) 5V < VS < 27V, –40°C < Tj < 150°C; unless otherwise specified all values refer to GND pins. No. 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 Parameters Regulator drop voltage Line regulation Load regulation Power supply ripple rejection Test Conditions VS > 3.3V, IVCC = –15 mA 5.5V < VS < 18V 5 mA < IVCC < 50 mA 10 Hz to 100 kHz CVCC = 10 µF VS = 14V, IVCC = –15 mA 0.2Ω < ESR < 5Ω at 100 kHz Referred to VCC VS > 5.5V Referred to VCC VS > 5.5V Pin VCC VCC VCC VCC VCC VCC VCC VCC VCC IVCClim Cload VthunN Vhysthun tVCC Symbol VD3 VCCline VCCload 50 –240 1.8 4.2 250 130 300 –160 10 4.8 0.5 Min. Typ. Max. 200 1 2 Unit mV % % dB mA µF V mV µs Type* A A A C A D A A A Output current limitation VS > 5.5V Load capacity VCC undervoltage threshold Hysteresis of undervoltage threshold Ramp up time VS > 5.5V CVCC = 2.2 µF to VCC = 5V Iload = –5 mA at VCC 8 LIN Bus Driver: Bus Load Conditions: Load 1 (Small): 1 nF, 1 kΩ, Load 2 (Large): 10 nF, 500Ω, Internal Pull-up RRXD = 5 kΩ, CRXD = 20 pF, Load 3 (Medium): 6.8 nF, 660Ω, Characterized on Samples 10.6 and 10.7 Specifies the Timing Parameters for Proper Operation at 20 kBit/s and 10.8 and 10.9 at 10.4 kBit/s Driver recessive output voltage Load1/Load2 LIN LIN LIN LIN LIN LIN LIN LIN Input Leakage current Driver off VBUS = 0V VBatt = 12V Driver off 8V < VBatt < 18V 8V < VBUS < 18V VBUS ≥ VBatt VBUSrec V_LoSUP V_HiSUP V_LoSUP_1k V_HiSUP_1k RLIN VSerDiode IBUS_lim 0.6 0.8 20 0.4 40 120 30 60 1.0 200 0.9 × VS VS 1.2 2 V V V V V kΩ V mA A A A A A A D A 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 Driver dominant voltage VVS = 7V, Rload = 500Ω Driver dominant voltage VVS = 18V, Rload = 500Ω Driver dominant voltage VVS = 7V, Rload = 1000Ω Driver dominant voltage VVS = 18V, Rload = 1000Ω Pull–up resistor to VS The serial diode is mandatory Voltage drop at the serial In pull-up path with Rslave ISerDiode = 10 mA diodes LIN current limitation VBUS = VBatt_max Input leakage current at the receiver including pull-up resistor as specified Leakage current LIN recessive 8.9 LIN IBUS_PAS_dom –1 –0.35 mA A 8.10 LIN IBUS_PAS_rec 10 20 µA A 8.11 Leakage current when control unit disconnected GNDDevice = VS from ground. Loss of VBatt = 12V local ground must not 0V < VBUS < 18V affect communication in the residual network LIN IBUS_NO_gnd –10 +0.5 +10 µA A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 16 ATA6623/ATA6625 4957G–AUTO–09/09 ATA6623/ATA6625 9. Electrical Characteristics (Continued) 5V < VS < 27V, –40°C < Tj < 150°C; unless otherwise specified all values refer to GND pins. No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* Leakage current at disconnected battery. Node has to sustain the VBatt disconnected current that can flow VSUP_Device = GND under this condition. Bus 0V < VBUS < 18V must remain operational under this condition. LIN Bus Receiver Center of receiver threshold VBUS_CNT = (Vth_dom + Vth_rec)/2 LIN LIN LIN LIN LIN Activates the LIN receiver LIN VBUS_CNT VBUSdom VBUSrec VBUShys VLINH VLINL 0.475 × VS –27 0.6 × VS 0.028 × VS VS – 2V –27 0.1 x VS 0.5 × VS 0.525 × VS 0.4 × VS 40 0.175 × VS VS + 0.3V VS – 3.3V V V V V V V A A A A A A 8.12 LIN IBUS_NO_bat 0.1 2 µA A 9 9.1 9.2 9.3 9.4 9.5 9.6 10 10.1 Receiver dominant state VEN = 5V Receiver recessive state VEN = 5V Receiver input hysteresis Pre-wake detection LIN High level input voltage Pre-wake detection LIN Low level input voltage Internal Timers Dominant time for wake–up via LIN bus VLIN = 0V Vhys = Vth_rec – Vth_dom LIN tbus 30 90 150 µs A 10.2 Time delay for mode change from Pre-normal V = 5V into Normal Mode via pin EN EN Time delay for mode change from Normal V = 0V Mode to Sleep Mode via EN pin EN TXD dominant time out time VTXD = 0V EN tnorm 5 20 µs A 10.3 EN tsleep 2 7 15 µs A 10.4 TXD tdom ts_n 6 13 20 ms A 10.5 Time delay for mode change from Silent Mode VEN = 5V into Normal Mode via EN THRec(max) = 0.744 × VS THDom(max) = 0.581 × VS VS = 7.0V to 18V tBit = 50 µs D1 = tbus_rec(min)/(2 × tBit) THRec(min) = 0.422 × VS THDom(min) = 0.284 × VS VS = 7.6V to 18V tBit = 50 µs D2 = tbus_rec(max)/(2 × tBit) EN 5 15 40 µs A 10.6 Duty cycle 1 LIN D1 0.396 A 10.7 Duty cycle 2 LIN D2 0.581 A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 17 4957G–AUTO–09/09 9. Electrical Characteristics (Continued) 5V < VS < 27V, –40°C < Tj < 150°C; unless otherwise specified all values refer to GND pins. No. Parameters Test Conditions THRec(max) = 0.778 × VS THDom(max) = 0.616 × VS VS = 7.0V to 18V tBit = 96 µs D3 = tbus_rec(min)/(2 × tBit) THRec(min) = 0.389 × VS THDom(min) = 0.251 × VS VS = 7.6V to 18V tBit = 96 µs D4 = tbus_rec(max)/(2 × tBit) VS = 7.0V to 18V Pin Symbol Min. Typ. Max. Unit Type* 10.8 Duty cycle 3 LIN D3 0.417 A 10.9 Duty cycle 4 LIN D4 0.590 A 10.10 11 11.1 Slope time falling and rising edge at LIN LIN tSLOPE_fall tSLOPE_rise 3.5 22.5 µs A Receiver Electrical AC Parameters of the LIN Physical Layer LIN Receiver, RXD Load Conditions: CRXD = 20 pF Propagation delay of receiver Figure 9-1 VS = 7.0V to 18V trx_pd = max(trx_pdr , trx_pdf) RXD trx_pd trx_sym –2 6 µs A 11.2 Symmetry of receiver VS = 7.0V to 18V propagation delay rising trx_sym = trx_pdr – trx_pdf edge minus falling edge RXD +2 µs A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 18 ATA6623/ATA6625 4957G–AUTO–09/09 ATA6623/ATA6625 Figure 9-1. Definition of Bus Timing Characteristics tBit TXD (Input to transmitting node) tBit tBit tBus_dom(max) tBus_rec(min) THRec(max) VS (Transceiver supply of transmitting node) THDom(max) LIN Bus Signal THRec(min) THDom(min) Thresholds of receiving node1 Thresholds of receiving node2 tBus_dom(min) tBus_rec(max) RXD (Output of receiving node1) trx_pdf(1) trx_pdr(1) RXD (Output of receiving node2) trx_pdr(2) trx_pdf(2) 19 4957G–AUTO–09/09 Figure 9-2. Application Circuit VCC VCC ATA6623/25 1 VS Master node pull-up VBAT + RXD 5 Receiver Normal Mode 1 kΩ 100 nF 22 µF + RF filter LIN 4 LIN-BUS 220 pF VCC Microcontroller TXD 6 TXD Time-out timer Wake-up bus timer Short circuit and overtemperature protection Slew rate control 8 EN 2 Control unit GND 3 Sleep mode VCC switched off Normal/Silent/ Fail-safe Mode 3.3V/50 mA/±2% 5V/50 mA/±2% Undervoltage reset VCC 7 NRES 10 kΩ 100 nF 10 µF GND 20 ATA6623/ATA6625 4957G–AUTO–09/09 ATA6623/ATA6625 10. Ordering Information Extended Type Number ATA6623-TAPY ATA6625-TAPY ATA6623-TAQY ATA6625-TAQY Package SO8 SO8 SO8 SO8 Remarks 3.3V LIN system basis chip, Pb-free, 1k, taped and reeled 5V LIN system basis chip, Pb-free, 1k, taped and reeled 3.3V LIN system basis chip, Pb-free, 4k, taped and reeled 5V LIN system basis chip, Pb-free, 4k, taped and reeled 11. Package Information Package: SO 8 Dimensions in mm 4.9±0.1 5±0.2 3.7±0.1 0.2 0.1+0.15 1.4 0.4 1.27 3.81 3.8±0.1 6±0.2 8 5 technical drawings according to DIN specifications 1 Drawing-No.: 6.541-5031.01-4 Issue: 1; 15.08.06 4 21 4957G–AUTO–09/09 12. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. History • • • • • • Figures changed: 1-1, 4-2, 4-3, 4-4, 4-5, 6-2, 9-2 Sections changed: 3.1, 3.6, 3.8, 3.9, 3.10, 4.1, 4.2, 4.3, 5 Description Text changed Table 4-1 changed Abs. Max. Ratings table changed El. Characteristics table changed 4957G-AUTO-09/09 4957F-AUTO-02/08 • “Pre-normal Mode” in “Fail-safe Mode” changed • Section 7 “Absolute Maximum Ratings” on page 13 changed • Section 8 “Electrical Characteristics” numbers 10.5 to 10.10 on pages 17 to 18 changed • Section 9 “Ordering Information” on page 20 changed • • • • Features changed Block diagram changed Application diagram changed Text changed under the headings: 3.2, 3.3, 3.4, 3.6, 3.7, 3.8, 3.9, 4, 4.1, 4.2, 4.3, 4.4, 4.5, 5.5, 5.6, 6 Figure 4-2, 4-3, 4-4, 4-5, 8-2: changed Figure title 6-1: text changed Abs. Max. Ratings: row “Output current NRES” added El. Char. table: values changed in the following rows: 1.3, 5.1, 5.3, 5.4, 6.9, 6.12, 7.9, 11.1 4957E-AUTO-10/07 4957D-AUTO-07/07 • • • • • • • • • • • • • 4957C-AUTO-02/07 Features on page 1 changed Table 2-1 “Pin Description” on page 2 changed Section 3-1 “Physical Layer Compatibility” on page 3 added Section 3-2 “Supply Pin (VS) on page 3 changed Section 3-3 “Ground Pin (GND) on page 3 changed Section 3-8 “Dominant Time-out Function (TXD)” on page 4 changed Section 4-1 “Normal Mode” on page 5 changed Section 4-2 “Silent Mode” on page 5 changed Figure 4-3 “LIN Wake-up Waveform Diagram from Silent Mode” on page 6 changed • Section 4.3 “Sleep Mode” on page 7 changed • Section 4-5 “Unpowered Mode” on page 7 changed • Figure 4-4 “Switch to Sleep Mode” on page 8 changed • Figure 4-6 “VCC Voltage Regulator: Ramp up and Undervoltage” on page 9 changed • Section 5 “Fail-safe Features on page 9 changed • Section 6 “Voltage Regulator” on page 10 changed • Section 7 “Absolute Maximum Ratings” on page 11 changed • Section 8 “Electrical Characteristics” on pages 12 to 16 changed • Section 9 “Ordering Information” on page 18 changed 22 ATA6623/ATA6625 4957G–AUTO–09/09 Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 International Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-en-Yvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Product Contact Web Site www.atmel.com Technical Support auto_control@atmel.com Sales Contact www.atmel.com/contacts Literature Requests www.atmel.com/literature Disclaimer: T he information in this document is provided in connection with Atmel products. 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