ATA6824-PNQW

Features • • • • • • • • • • • PWM and Direction-controlled Driving of Four Externally-powered NMOS Transistors High Temperature Capability up to 200°C Junction A Programmable Dead Time Is Included to Avoid Peak Currents Within the H-bridge Integrated Charge Pump to Provide Gate Voltages for High-side Drivers and to Supply the Gate of the External Battery Reverse Protection NMOS 5V/3.3V Regulator and Current Limitation Function Reset Derived From 5V/3.3V Regulator Output Voltage A Programmable Window Watchdog Battery Overvoltage Protection and Battery Undervoltage Management Overtemperature Warning and Protection (Shutdown) High Voltage Serial Interface for Communication QFN32/TPQFP Package 1. Description The ATA6824 is designed for DC motor control application in automotive high temperature environment like in mechatronic assemblies in the vicinity of the hot engine, e.g. turbo charger. With a maximum junction temperature of 200°C, ATA6824 is suitable for applications with an ambient temperature up to 150°C. The IC includes 4 driver stages to control 4 external power MOSFETs. An external microcontroller provides the direction signal and the PWM frequency. In PWM operation, the high-side switches are permanently on while the low-side switches are activated by the PWM frequency. ATA6824 contains a voltage regulator to supply the microcontroller; via the input pin VMODE the output voltage can be set to 5V or 3.3V respectively. The on-chip window watchdog timer provides a pin-programmable time window. The watchdog is internally trimmed to an accuracy of 10%. For communication a high voltage serial interface with a maximum data range of 20 kBaud is integrated. High Temperature H-bridge Motor Driver ATA6824 4931G–AUTO–04/09 Figure 1-1. Block Diagram M CVRES CP VRES CPLO RGATE H2 RGATE H1 S1 S2 RGATE L1 RGATE L2 PGND GND Charge Pump CPIH OT UV 12V Regulator Supervisor DG2 DG1 CC CC timer HS Driver 2 HS Driver 1 LS Driver 1 LS Driver 2 VBAT DG3 CCP CVG VBAT VG PBAT VINT Vint 5V Regulator OTP 12 bit OV Logic Control Oscillator CCC RCC CVINT CP WD timer VBAT TP1 VBG VBATSW VCC 5V Regulator Serial Interface RRWD SIO Bandgap CSIO WD TP2 DIR PWM RX TX VCC VMODE /RESET CVCC Battery Microcontroller 2 ATA6824 4931G–AUTO–04/09 ATA6824 2. Pin Configuration Figure 2-1. Pinning QFN32/TPQFP32 TP2 VBATSW VBAT VCC PGND L1 L2 PBAT VMODE VINT RWD CC /RESET WD GND SIO 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 24 23 22 Atmel YWW 21 ATA6824 20 ZZZZZ-AL 19 18 17 9 10 11 12 13 14 15 16 TX DIR PWM TP1 RX DG3 DG2 DG1 VG CPLO CPHI VRES H2 S2 H1 S1 Note: YWW ATA6824 ZZZZZ AL Date code (Y = Year - above 2000, WW = week number) Product name Wafer lot number Assembly sub-lot number Table 2-1. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Pin Description Symbol VMODE VINT RWD CC /RESET WD GND SIO TX DIR PWM TP1 RX DG3 DG2 DG1 S1 H1 S2 H2 VRES I/O I I/O I I/O O I I I/O I I I – O O O O I/O O I/O O I/O Function Selector for VCC and interface logic voltage level Blocking capacitor 220 nF/10V/X7R Resistor defining the watchdog interval RC combination to adjust cross conduction time Reset signal for microcontroller Watchdog trigger signal Ground for chip core High Voltage (HV) serial interface Transmit signal to serial interface from microcontroller Defines the rotation direction for the motor PWM input controls motor speed Test pin to be connected to GND Receive signal from serial interface for microcontroller Diagnostic output 3 Diagnostic output 2 Diagnostic output 1 Source voltage H-bridge, high-side 1 Gate voltage H-bridge, high-side 1 Source voltage H-bridge, high-side 2 Gate voltage H-bridge, high-side 2 Gate voltage for reverse protection NMOS, blocking capacitor 470 nF/25V/X7R 3 4931G–AUTO–04/09 Table 2-1. Pin 22 23 24 25 26 27 28 29 30 31 32 Pin Description (Continued) Symbol CPHI CPLO VG PBAT L2 L1 PGND VCC VBAT VBATSW TP2 I/O I O I/O I O O I O I O – Function Charge pump capacitor 220 nF/25V/X7R Blocking capacitor 470 nF/25V/X7R Power supply (after reverse protection) for charge pump and H-bridge Gate voltage H-bridge, low-side 2 Gate voltage H-bridge, low-side 1 Power ground for H-bridge and charge pump 5V/100 mA supply for microcontroller, blocking capacitor 2.2 µF/10V/X7R Supply voltage for IC core (after reverse protection) 100Ω PMOS switch from VBAT Test pin to be connected to GND 3. General Statement and Conventions • Parameter values given without tolerances are indicative only and not to be tested in production • Parameters given with tolerances but without a parameter number in the first column of parameter table are “guaranteed by design” (mainly covered by measurement of other specified parameters). These parameters are not to be tested in production. The tolerances are given if the knowledge of the parameter tolerances is important for the application • The lowest power supply voltage is named GND • All voltage specifications are referred to GND if not otherwise stated • Sinking current means that the current is flowing into the pin (value is positive) • Sourcing current means that the current is flowing out of the pin (value is negative) 3.1 Related Documents • Qualification of integrated circuits according to Atmel® HNO procedure based on AEC-Q100 • AEC-Q100-004 and JESD78 (Latch-up) • ESD STM 5.1-1998 • CEI 801-2 (only for information regarding ESD requirements of the PCB) 4 ATA6824 4931G–AUTO–04/09 ATA6824 4. Application 4.1 General Remark This chapter describes the principal application for which the ATA6824 was designed. Because Atmel cannot be considered to understand fully all aspects of the system, application and environment, no warranties of fitness for a particular purpose are given. Table 4-1. Component CVINT CVCC CCC RCC CVG CCP CVRES RRWD CSIO Typical External Components (See also Figure 1-1 on page 2) Function Blocking capacitor at VINT Blocking capacitor at VCC Cross conduction time definition capacitor Cross conduction time definition resistor Blocking capacitor at VG Charge pump capacitor Reservoir capacitor Watchdog time definition resistor Filter capacitor for SIO Value 220 nF, 10V, X7R 2.2 µF, 10V, X7R Typical 680 pF, 100V, COG Typical 10 kΩ Typical 470 nF, 25V, X7R Typical 220 nF, 25V, X7R Typical 470 nF, 25V, X7R Typical 51 kΩ Typical 220 pF, 100V 50% Tolerance 50% 50% 5. Functional Description 5.1 5.1.1 Power Supply Unit with Supervisor Functions Power Supply The IC is supplied by a reverse-protected battery voltage. To prevent it from destruction, proper external protection circuitry has to be added. It is recommended to use at least a capacitor combination of storage and HF caps behind the reverse protection circuitry and closed to the VBAT pin of the IC (see Figure 1-1 on page 2). An internal low-power and low drop regulator (VINT), stabilized by an external blocking capacitor, provides the necessary low-voltage supply for all internal blocks except the digital IO pins. This voltage is also needed in the wake-up process. The low-power band gap reference is trimmed and is used for the bigger VCC regulator, too. All internal blocks are supplied by the internal regulator. Note: The internal supply voltage VINT must not be used for any other supply purpose! Nothing inside the IC except the logic interface to the microcontroller is supplied by the 5V/3.3V VCC regulator. A power-good comparator checks the output voltage of the VINT regulator and keeps the whole chip in reset as long as the voltage is too low. There is a high-voltage switch which brings out the battery voltage to the pin VBATSW for measurement purposes. This switch is switched ON for VCC = HIGH and stays ON in case of a watchdog reset. The signal can be used to switch on external voltage regulators, etc. 5 4931G–AUTO–04/09 5.1.2 Voltage Supervisor This block is intended to protect the IC and the external power MOS transistors against overvoltage on battery level and to manage undervoltage on it. Function: in case of both overvoltage alarm (VTHOV) and of undervoltage alarm (VTHUV) the external NMOS motor bridge transistors will be switched off. The failure state will be flagged via DG2. No other actions will be carried out. The voltage supervision block is connected to VBAT and filtered by a first-order low pass with a corner frequency of typical 15 kHz. 5.1.3 Temperature Supervisor There is a temperature sensor integrated on-chip to prevent the IC from overheating due to a failure in the external circuitry and to protect the external NMOSFET transistors. In case of detected overtemperature (180°C), the diagnostic pin DG3 will be switched to “H” to signalize this event to the microcontroller. It should undertake actions to reduce the power dissipation in the IC. In case of detected overtemperature (200°C), the VCC regulator and all drivers including the serial interface will be switched OFF immediately and /RESET will go LOW. Both temperature thresholds are correlated. The absolute tolerance is ±15°C and there is a built-in hysteresis of about 10°K to avoid fast oscillations. After cooling down below the 170°C threshold; the IC will go into Active mode. 5.2 5V/3.3V VCC Regulator The 5V/3.3V regulator is fully integrated on-chip. It requires only a 2.2 µF ceramic capacitor for stability and has 100 mA current capability. Using the VMODE pin, the output voltage can be selected to either 5V or 3.3V. Switching of the output voltage during operation is not intended to be supported. The VMODE pin must be hard-wired to either VINT for 5V or to GND for 3.3V. The logic HIGH level of the microcontroller interface will be adapted to the VCC regulator voltage. The output voltage accuracy is in general < ±3%; in the 5V mode with VVBAT < 9V it is limited to < 5%. To prevent destruction of the IC, the current delivered by the regulator is limited to maximum 100 mA to 350 mA. The delivered voltage will break down and a reset may occur. Please note that this regulator is the main heat source on the chip. The maximum output current at maximum battery voltage and high ambient temperature can only guaranteed if the IC is mounted on an efficient heat sink. A power-good comparator checks the output voltage of the VCC regulator and keeps the external microcontroller in reset as long as the voltage is too low. 6 ATA6824 4931G–AUTO–04/09 ATA6824 Figure 5-1. Voltage Dependence and Timing of VCC Controlled RESET T res T delayRESL VCC 5V V tHRES /RESET Figure 5-2. Correlation between VCC Output Voltage and Reset Threshold VCC 5.15V 4.9V VCC1 4.85V VtHRESH Tracking voltage VCC1-tHRESH > 100 mV 4.1V VCC1-VtHRESH = VCC1 - VtHRESH The voltage difference between the regulator output voltage and the upper reset threshold voltage is bigger than 75 mV (VMODE = HIGH) and bigger than 50 mV (VMODE = LOW). 5.3 Reset and Watchdog Management The timing basis of the watchdog is provided by the trimmed internal oscillator. Its period TOSC is adjustable via the external resistor RWD. The watchdog expects a triggering signal (a rising edge) from the microcontroller at the WD input within a period time window of TWD. Figure 5-3. Timing Diagram of the Watchdog Function tres tresshort /RESET td t1 t2 t1 t2 td WD 7 4931G–AUTO–04/09 5.3.1 Timing Sequence For example, with an external resistor RWD = 33 kΩ ±1% we get the following typical parameters of the watchdog. TOSC = 12.32 µs, t1 = 12.1 ms, t2 = 9.61 ms, TWD = 16.88 ms ±10% The times tres = 68 ms and td = 68 ms are fixed values with a tolerance of 10%. After ramp-up of the battery voltage (power-on reset), the VCC regulator is switched on. The reset output, /RESET, stays low for the time tres (typically 68 ms), then switches to high. For an initial lead time td (typically 68 ms for setups in the controller) the watchdog waits for a rising edge on WD to start its normal window watchdog sequence. If no rising edge is detected, the watchdog will reset the microcontroller for tres and wait td for the rising edge on WD. Times t1 (close window) and t2 (open window) form the window watchdog sequence. To avoid receiving a reset from the watchdog, the triggering signal from the microcontroller must hit the timeframe of t2 = 9.61 ms. The trigger event will restart the watchdog sequence. Figure 5-4. TWD versus RWD 60 50 max typ TWD (ms) 40 30 min 20 10 0 10 20 30 40 50 60 70 80 90 100 RWD (kΩ) If triggering fails, /RESET will be pulled to ground for a shortened reset time of typically 2 ms. The watchdog start sequence is similar to the power-on reset. The internal oscillator is trimmed to a tolerance of < ±10%. This means that t1 and t2 can also vary by ±10%. The following calculation shows the worst case calculation of the watchdog period Twd which the microcontroller has to provide. t1min = 0.90 × t1 = 10.87 ms, t1max = 1.10 × t1 = 13.28 ms t2min = 0.90 × t2 = 8.65ms, t2max = 1.10 × t2 = 10.57 ms Twdmax = t1min + t2min = 10.87 ms + 8.65 ms = 19.52 ms Twdmin = t1max = 13.28 ms Twd = 16.42 ms ±3.15 ms (±19.1%) Figure 5-4 on page 8 shows the typical watchdog period TWD depending on the value of the external resistor ROSC. A reset will be active for VCC < VtHRESx; the level VtHRESx is realized with a hysteresis (HYSRESth). 8 ATA6824 4931G–AUTO–04/09 ATA6824 5.4 High Voltage Serial Interface A bi-directional bus interface is implemented for data transfer between hostcontroller and the local microcontroller (SIO). The transceiver consists of a low side driver (1.2V at 40 mA) with slew rate control, wave shaping, current limitation, and a high-voltage comparator followed by a debouncing unit in the receiver. In case of an active reset shown at pin /RESET the pin SIO is switched to low. 5.4.1 Transmit Mode During transmission, the data at the pin TX will be transferred to the bus driver to generate a bus signal on pin SIO. The pin TX has a pull-down resistor included. To minimize the electromagnetic emission of the bus line, the bus driver has an integrated slew rate control and wave-shaping unit. Transmission will be interrupted in the following cases: • Thermal shutdown active Figure 5-5. Definition of Bus Timing Parameters tBit TX (input to transmitting Node) tBit tBit tSIO_dom(max) tSIO_rec(min) THRec(max) VS (Transceiver supply of transmitting node) Thresholds of receiving node 1 SIO Signal THDom(max) Thresholds of receiving node 2 THRec(min) THDom(min) tSIO_dom(min) RX (output of receiving Node 1) tSIO_rec(max) trx_pdf(1) RX (output of receiving Node 2) trx_pdr(1) trx_pdr(2) trx_pdf(2) The recessive BUS level is generated from the integrated 30 kΩ pull-up resistor in series with an active diode. This diode prevents the reverse current of VBUS during differential voltage between VSUP and BUS (VBUS > VSUP). 9 4931G–AUTO–04/09 5.5 5.5.1 Control Inputs DIR and PWM Pin DIR Logical input to control the direction of the external motor to be controlled by the IC. An internal pull-down resistor is included. 5.5.2 Pin PWM Logical input for PWM information delivered by external microcontroller. Duty cycle and frequency at this pin are passed through to the H-bridge. An internal pull-down resistor is included. Table 5-1. ON 0 1 1 DIR X 0 1 Status of the IC Depending on Control Inputs and Detected Failures Driver Stage for External Power MOS H1 OFF ON /PWM L1 OFF OFF PWM H2 OFF /PWM ON L2 OFF PWM OFF Standby mode Motor PWM forward Motor PWM reverse X PWM PWM Comments PWM Control Inputs The internal signal ON is high when • At least one valid trigger has been accepted (SYNC = 1) • VBAT is inside the specified range (UV = 0 and nOV = 1) • The charge pump has reached its minimum voltage (CPOK = 1) and • The device is not overheated (OT2 = 0) In case of a short circuit, the appropriate transistor is switched off after a debounce time of about 10 µs. In order to avoid cross current through the bridge, a cross conduction timer is implemented. Its time constant is programmable by means of an RC combination. Table 5-2. CPOK 0 X X X X Note: Status of the Diagnostic Outputs Device Status OT1 X 1 X X OV X X 1 X UV X X X 1 SC X X X X Diagnostic Outputs DG1 – – – – DG2 1 – 1 1 – DG3 – 1 – – – Charge pump failure Overtemperature warning Overvoltage Undervoltage Short circuit Comments X X X 1 1 X represents: don't care – no effect) OT1: Overtemperature warning OV: Overvoltage of VBAT UV: Undervoltage of VBAT SC: Short circuit CPOK: Charge pump OK 10 ATA6824 4931G–AUTO–04/09 ATA6824 5.6 VG Regulator The VG regulator is used to generate the gate voltage for the low-side driver. Its output voltage will be used as one input for the charge pump, which generates the gate voltage for the high-side driver. The purpose of the regulator is to limit the gate voltage for the external power MOS transistors to 12V. It needs a ceramic capacitor of 470 nF for stability. The output voltage is reduced if the supply voltage at VBAT falls below 12V. 5.7 Charge Pump The integrated charge pump is needed to supply the gates of the external power MOS transistors. It needs a shuffle capacitor of 220 nF and a reservoir capacitor of 470 nF. Without load, the output voltage on the reservoir capacitor is VVBAT plus VG. The charge pump is clocked with a dedicated internal oscillator of 100 KHz. The charge pump is designed to reach a good EMC level. The charge pump will be switched off for VVBAT > VTHOV. 5.8 Thermal Shutdown There is a thermal shutdown block implemented. With rising junction temperature, a first warning level will be reached at 180°C. At this point the IC stays fully functional and a warning will be sent to the microcontroller. At junction temperature 200°C the VCC regulator will be switched off and a reset occurs. 5.9 H-bridge Driver The IC includes two push-pull drivers for control of two external power NMOS used as high-side drivers and two push-pull drivers for control of two external power NMOS used as low-side drivers. The drivers are able to be used with standard and logic-level power NMOS. The drivers for the high-side control use the charge pump voltage to supply the gates with a voltage of VG above the battery voltage level. The low-side drivers are supplied by VG directly. It is possible to control the external load (motor) in the forward and reverse direction (see Table 5-1 on page 10). The duty cycle of the PMW controls the speed. A duty cycle of 100% is possible in both directions. 5.9.1 Cross Conduction Time To prevent high peak currents in the H-bridge, a non-overlapping phase for switching the external power NMOS is realized. An external RC combination defines the cross conduction time in the following way: tCC (µs) = 0.41 × RCC (kΩ) × CCC (nF) (tolerance: ±5% ±0.15 µs) The RC combination is charged to 5V and the switching level of the internal comparator is 67% of the start level. The resistor RCC must be greater than 5 kΩ and should be as close as possible to 10 kΩ, the CCC value has to be ≤5 nF. Use of COG capacitor material is recommended. The time measurement is triggered by the PWM or DIR signal crossing the 50% level. 11 4931G–AUTO–04/09 Figure 5-6. Timing of the Drivers PWM or DIR 50% t tLxHL tLxf tLxLH tLxr 80% Lx 20% tCC t tHxLH tHxr tHxHL tHxf tCC 80% Hx 20% t The delays tHxLH and tLxLH include the cross conduction time tCC. 5.10 Short Circuit Detection To detect a short in H-bridge circuitry, internal comparators detect the voltage difference between source and drain of the external power NMOS. If the transistors are switched ON and the source-drain voltage difference is higher than the value VSC (4V with tolerances) for a time > tSC (typically 10 µs) the signal SC (short circuit) will be set and the drivers will be switched off immediately. The diagnostic pin DG1 will be set to “H”. With the next transition on pin PWM, the bit will be cleared and the corresponding drivers, depending on the DIR pin, will be switched on again. There is a PBAT supervision block implemented to detect the possible voltage drop on PBAT during a short circuit. If the voltage at PBAT falls under VSCPB (5.6V with tolerances) for a time > tSC the drivers will be switched off immediately and DG1 will be set to “H”. It will be cleared as above. 12 ATA6824 4931G–AUTO–04/09 ATA6824 6. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Pin Description Ground Power ground Reverse protected battery voltage Reverse current out of pin Reverse protected battery voltage Reverse current out of pin Digital output Digital output 4.9V output, external blocking capacitor Cross conduction time capacitor/resistor combination Digital input coming from microcontroller Watchdog timing resistor Digital input direction control Digital input PWM control + Test mode 5V regulator output Digital input 12V output, external blocking capacitor Digital output Digital input Serial interface data pin Source external high-side NMOS Gates external low-side NMOS Gates of external high-side NMOS Charge pump Charge pump Charge pump output Switched VBAT Power dissipation Storage temperature Notes: 1. For VVBAT ≤ 13.5V 2. May be additionally limited by external thermal resistance 3. x = 1.2 4. t < 0.5s 5. Load dump of t < 0.5s tolerated Pin Name GND PGND VBAT VBAT PBAT PBAT /RESET DG1, DG2, DG3 VINT CC WD RWD DIR PWM VCC VMODE VG RX TX SIO S1, S2 L1, L2 H1, H2 CPLO CPHI VRES VBATSW Ptot ϑ STORE –55 –500 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –27 (1) Min 0 –0.3 –1 Max 0 +0.3 +40 +40 VVCC + 0.3 VVCC + 0.3 +5.5 VVCC + 0.3 VVCC + 0.3 VVCC + 0.3 VVCC + 0.3 VVCC + 0.3 +5.5 VVINT + 0.3 +16 VVCC + 0.3 VVCC + 0.3 VVBAT + 2 +30 +40(4) VVG + 0.3 VSx + 16(3) VPBAT + 0.3 VVRES + 0.3 +40 (5) Unit V V V mA V mA V V V V V V V V V V V V V V V V V V V V V W °C –2 VPGND – 0.3 VSx – 1(3) –0.3 –0.3 –0.3 –0.3 VVBAT + 0.3 1.4(2) +200 13 4931G–AUTO–04/09 7. Thermal Resistance Parameters Thermal resistance junction to heat slug Thermal resistance junction to ambient when heat slug is soldered to PCB Symbol Rthjc Rthja Value VTHOV –40 –40 180 200 Max VTHOV < VTHUV 125°C DC line 2.3 Line regulation Iload = 0 mA to 100 mA 29