ATA6827-PIQW

Features • • • • • • • • • • • • Supply Voltage up to 40V RDSon Typically 0.8Ω at 25°C, Maximum 1.8Ω at 200°C Up to 1.0A Output Current Three Half-bridge Outputs Formed by Three High-side and Three Low-side Drivers Capable to Switch all Kinds of Loads Such as DC Motors, Bulbs, Resistors, Capacitors and Inductors No Shoot-through Current Outputs Short-circuit Protected Overtemperature Protection for Each Switch and Overtemperature Prewarning Undervoltage Protection Various Diagnostic Functions Such as Shorted Output, Open-load, Overtemperature and Power-supply Fail Detection Serial Data Interface, Daisy Chain Capable, up to 2 MHz Clock Frequency QFN18 Package 1. Description The ATA6827 is a fully protected driver IC specially designed for high temperature applications. In mechatronic solutions, for example turbo charger or exhaust gas recirculation systems, many flaps have to be controlled by DC motor driver ICs which are located very close to the hot engine or actuator where ambient temperatures up to 150°C are usual. Due to the advantages of SOI technology junction temperatures up to 200°C are allowed. This enables new cost effective board design possibilities to achieve complex mechatronic solutions. The ATA6827 is a fully protected Triple Half-Bridge to control up to 3 different loads by a microcontroller in automotive and industrial applications. Each of the 3 high-side and 3 low-side drivers is capable to drive currents up to 1.0A. The drivers are internally connected to form 3 half-bridges and can be controlled separately from a standard serial data interface. Therefore, all kinds of loads such as bulbs, resistors, capacitors and inductors can be combined. The IC design especially supports the application of H-bridges to drive DC motors. Protection is guaranteed regarding short-circuit conditions, overtemperature and undervoltage. Various diagnostic functions and a very low quiescent current in standby mode opens a wide range of applications. Automotive qualification gives added value and enhanced quality for exacting requirements of automotive applications. High Temperature Triple Half-bridge Driver with Serial Input Control ATA6827 4912E–AUTO–02/10 Figure 1-1. Block Diagram n. u. n. u. O S C n. u. n. u. n. u. n. u. n. u. n. u. H S 3 L S 3 H S 2 L S 2 H S 1 L S 1 S R R 10 VS 11 Input register Ouput register Serial interface Charge pump L S 1 T P VS DI 4 CLK 5 P S F O P L S C D n. u. n. u. n. u. n. u. n. u. n. H u. S 3 L S 3 H S 2 L S 2 H S 1 CS 3 INH 8 DO 7 Control logic Power on reset 14 GND 17 Fault detector Fault detector Fault detector Fault detector Fault detector Fault detector UV protection 9 VCC GND Thermal protection 18 GND 6 1 OUT3S 2 OUT3F 13 OUT2S 12 OUT2F 16 OUT1S 15 OUT1F GND 2 ATA6827 4912E–AUTO–02/10 ATA6827 2. Pin Configuration Figure 2-1. Pinning QFN18 PGND3 PGND1 OUT1S OUT1F PGND2 OUT2S OUT3S OUT3F CS DI CLK GND 1 2 3 4 5 6 18 17 16 15 14 13 12 11 10 9 8 7 OUT2F VS VS VCC INH DO Table 2-1. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Pin Description Symbol OUT3S OUT3F CS DI CLK GND DO INH VCC VS VS OUT2F OUT2S PGND2 OUT1F OUT1S PGND1 PGND3 PGND1 PGND3 Function Used only for final testing, to be connected to OUT3F Half-bridge output 3 Chip select input; 5-V CMOS logic level input with internal pull up; low = serial communication is enabled, high = disabled Serial data input; 5-V CMOS logic level input with internal pull down; receives serial data from the control device; DI expects a 16-bit control word with LSB being transferred first Serial clock input; 5-V CMOS logic level input with internal pull down; controls serial data input interface and internal shift register (fmax = 2 MHz) Ground; reference potential Serial data output; 5-V CMOS logic level tri-state output for output (status) register data; sends 16-bit status information to the microcontroller (LSB is transferred first); output will remain tri-stated unless device is selected by CS = low, therefore, several ICs can operate on one data output line only. Inhibit input; 5-V logic input with internal pull down; low = standby, high = normal operation Logic supply voltage (5 V) Power supply for output stages OUT1, OUT2 and OUT3, internal supply Power supply for output stages OUT1, OUT2 and OUT3, internal supply Half-bridge output 2 Used only for final testing, to be connected to OUT2F Power Ground OUT2 Half-bridge output 1 Used only for final testing, to be connected to OUT13F Power Ground OUT1 and OUT3 Power Ground OUT1 and OUT3 3 4912E–AUTO–02/10 3. Functional Description 3.1 Serial Interface Data transfer starts with the falling edge of the CS signal. Data must appear at DI synchronized to CLK and are accepted on the falling edge of the CLK signal. LSB (bit 0, SRR) has to be transferred first. Execution of new input data is enabled on the rising edge of the CS signal. When CS is high, pin DO is in tri-state condition. This output is enabled on the falling edge of CS. Output data will change their state with the rising edge of CLK and stay stable until the next rising edge of CLK appears. LSB (bit 0, TP) is transferred first. Figure 3-1. CS Data Transfer DI SRR 0 LS1 1 HS1 2 LS2 3 HS2 4 LS3 5 HS3 6 n. u. 7 n. u. 8 n. u. 9 n. u. 10 n. u. 11 n. u. 12 OCS 13 n. u. 14 n. u. 15 CLK DO TP S1L S1H S2L S2H S3L S3H n. u. n. u. n. u. n. u. n. u. n. u. SCD OPL PSF Table 3-1. Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Input Data Protocol Input Register SRR LS1 HS1 LS2 HS2 LS3 HS3 n. u. n. u. n. u. n. u. n. u. n. u. OCS n. u. n. u. Function Status register reset (high = reset; the bits PSF, OPL and SCD in the output data register are set to low) Controls output LS1 (high = switch output LS1 on) Controls output HS1 (high = switch output HS1 on) See LS1 See HS1 See LS1 See HS1 Not used Not used Not used Not used Not used Not used Overcurrent shutdown (high = overcurrent shutdown is active) Not used Not used 4 ATA6827 4912E–AUTO–02/10 ATA6827 Table 3-2. Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 Output Data Protocol Output (Status) Register TP Status LS1 Status HS1 Status LS2 Status HS2 Status LS3 Status HS3 n. u. n. u. n. u. n. u. n. u. n. u. SCD Function Temperature prewarning: high = warning High = output is on, low = output is off; not affected by SRR High = output is on, low = output is off; not affected by SRR Description see LS1 Description see HS1 Description see LS1 Description see HS1 Not used Not used Not used Not used Not used Not used Short circuit detected: set high when at least one high-side or low-side switch is switched off by a short-circuit condition. Bits 1 to 6 can be used to detect the shorted switch. Open load detected: set high, when at least one active high-side or low-side switch sinks/sources a current below the open load threshold current. Power-supply fail: undervoltage at pin VS detected 14 15 OPL PSF After power-on reset, the input register has the following status: Bit 15 Bit 14 x x Bit 13 (OCS) H Bit 12 x Bit 11 x Bit 10 x Bit 9 x Bit 8 x Bit 7 x Bit 6 (HS3) L Bit 5 (LS3) L Bit 4 (HS2) L Bit 3 (LS2) L Bit 2 Bit 1 (HS1) (LS1) L L Bit 0 (SRR) L The following patterns are used to enable internal test modes of the IC. It is not recommended to use these patterns during normal operation. Bit 15 Bit 14 H H H H H H Bit 13 (OCS) H H H Bit 12 H L L Bit 11 H L L Bit 10 L H L Bit 9 L H L Bit 8 L L H Bit 7 L L H Bit 6 (HS3) L L L Bit 5 (LS3) L L L Bit 4 (HS2) L L L Bit 3 (LS2) L L L Bit 2 Bit 1 (HS1) (LS1) L L L L L L Bit 0 (SRR) L L L 5 4912E–AUTO–02/10 3.2 Power-supply Fail In case of undervoltage at pin VS, the Power-Supply Fail bit (PSF) in the output register is set and all outputs are disabled. To detect an undervoltage, its duration has to be longer than the undervoltage detection delay time tdUV. The outputs are enabled immediately when supply voltage recovers to a normal operating value. The PSF bit stays high until it is reset by the SRR (Status Register Reset) bit in the input register. 3.3 Open-load Detection If the current through a high-side or low-side switch in the ON-state stays below the open-load detection threshold, the open-load detection bit (OPL) in the output register is set. The OPL bit stays high until it is reset by the SRR bit in the input register. To detect an open load, its duration has to be longer than the open-load detection delay time tdSd. 3.4 Overtemperature Protection If the junction temperature of one or more output stages exceeds the thermal prewarning threshold, T jPW s et , the temperature prewarning bit (TP) in the output register is set. When the temperature falls below the thermal prewarning threshold, TjPW reset, the bit TP is reset. The TP bit can be read without transferring a complete 16-bit data word. The status of TP is available at pin DO with the falling edge of CS. After the microcontroller has read this information, CS is set high and the data transfer is interrupted without affecting the status of input and output registers. If the junction temperature of one or more output stages exceeds the thermal shutdown threshold, Tj switch off, all outputs are disabled and the corresponding bits in the output register are set to low. The outputs can be enabled again when the temperature falls below the thermal shutdown threshold, Tjswitch on and the SRR bit in the input register is set to high. Hysteresis of thermal prewarning and shutdown threshold avoids oscillations. 3.5 Short-circuit Protection The output currents are limited by a current regulator. Overcurrent detection is activated by writing a high to the OCS (Overcurrent Shutdown) bit in the input register. When the current in an output stage exceeds the overcurrent limitation and shutdown threshold, it is switched off after a delay time (tdSd). The short-circuit detection bit (SCD) is set and the corresponding status bit in the output register is set to low. For OCS = low the overcurrent shutdown is inactive. The SCD bit is also set if the current exceeds the overcurrent limitation and shutdown threshold, but the outputs are not affected. By writing a high to the SRR bit in the input register the SCD bit is reset and the disabled outputs are enabled. 3.6 Inhibit Applying 0V to pin 8 (INH) inhibits the ATA6827. All output switches are then turned off and switched to tri-state. The data in the output register is deleted. The output switches can be activated again by switching pin 8 (INH) to 5V which initiates an internal power-on reset. 6 ATA6827 4912E–AUTO–02/10 ATA6827 4. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All values refer to GND pins. Parameters Supply voltage Supply voltage t < 0.5s; IS > –2A Logic supply voltage Logic input voltage Logic output voltage Input current Output current Output current Output voltage Reverse conducting current (tpulse = 150 µs) Junction temperature range Storage temperature range Ambient temperature range Pin 10, 11 10, 11 9 3, 4, 5, 8 7 3, 4, 5, 8 7 2, 12, 15 2, 12, 15 2, 12, 15 Symbol VVS VVS VVCC VCS,VDI, VCLK, VINH VDO ICS, IDI, ICLK, IINH IDO IOut3, IOut2, IOut1 IOut3, IOut2, IOut1 IOut3, IOut2, IOut1 Tj TSTG Ta Value –0.3 to +40 –1 –0.3 to +7 –0.3 to VVCC + 0.3 –0.3 to VVCC + 0.3 –10 to +10 –10 to +10 Internally limited, see output specification –0.3 to +40 17 –40 to +200 –55 to +200 –40 to +150 V A °C °C °C Unit V V V V V mA mA 5. Thermal Resistance Parameters Junction case Junction ambient Notes: (1) Test Conditions Symbol Rthjc RthJA Value 5 40 Unit K/W K/W 1. Depends on PCB board design 6. Operating Range Parameters Supply voltage Logic supply voltage Logic input voltage Serial interface clock frequency Junction temperature range Note: Threshold for undervoltage detection Symbol VVS VVCC VCS,VDI, VCLK, VINH fCLK Tj Value VUV(2) to 40 4.75 to 5.25 –0.3 to VVCC 2 –40 to +200 Unit V V V MHz °C 7 4912E–AUTO–02/10 7. Noise and Surge Immunity Parameters Conducted interferences Interference suppression ESD (Human Body Model) CDM (Charged Device Model) Note: Test pulse 5: Vsmax = 40V Test Conditions ISO 7637-1 VDE 0879 Part 2 ESD S 5.1 ESD STM 5.3.1-1999 all pins Value Level 4(1) Level 5 2 kV 500V 8. Electrical Characteristics 7.5V < VVS < 40V; 4.75V < VVCC < 5.25 V; INH = High; –40°C ≤ Tj ≤ 200° C; Ta ≤ 150°C; unless otherwise specified, all values refer to GND pins. No. 1 1.1 1.2 1.3 1.4 1.5 1.6 2 2.1 2.2 2.3 2.4 2.5 3 3.1 3.2 3.3 3.4 3.5 Parameters Current Consumption Quiescent current VS Quiescent current VCC Supply current VS Supply current VCC Discharge current VS Discharge current VS VVS < 20V, INH = low 4.75 V < VVCC < 5.25V, INH = low 10, 11 9 IVS IVCC IVS IVCC IVS IVS 0.5 2.0 1 15 4 350 60 40 6 500 5.5 10 µA µA mA µA mA mA A A A A A A Test Conditions Pin Symbol Min. Typ. Max. Unit Type* VVS < 20V normal 10, 11 operating, all outputs off 4.75V < VVCC < 5.25V, normal operating VVS = 32.5V, INH = low VVS = 40V, INH = low 9 10, 11 10, 11 Undervoltage Detection, Power-on Reset Power-on reset threshold Power-on reset delay time After switching on VCC 10, 11 10, 11 9 VVCC tdPor VUv ΔVUv tdUV 10 3.1 30 5.5 0.6 40 3.9 95 4.5 190 7.1 V µs V V µs A A A A A Undervoltage-detection VCC = 5V threshold Undervoltage-detection VCC = 5V hysteresis Undervoltage-detection delay time Thermal Prewarning and Shutdown Thermal prewarning set Thermal prewarning reset Thermal prewarning hysteresis Thermal shutdown off Thermal shutdown on TjPW set TjPW reset ΔTjPW Tj switch off Tj switch on 170 155 195 180 15 220 205 °C °C °C B B B B B 200 185 225 210 250 235 °C °C *) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Delay time between rising edge of the input signal at pin CS after data transmission and switch on output stages to 90% of final level. Device not in standby for t > 1 ms 8 ATA6827 4912E–AUTO–02/10 ATA6827 8. Electrical Characteristics (Continued) 7.5V < VVS < 40V; 4.75V < VVCC < 5.25 V; INH = High; –40°C ≤ Tj ≤ 200° C; Ta ≤ 150°C; unless otherwise specified, all values refer to GND pins. No. 3.6 Parameters Thermal shutdown hysteresis Ratio thermal shutdown off/thermal prewarning set Ratio thermal shutdown on/thermal prewarning reset Output Specification (OUT1-OUT3) IOut 1-3 = –0.9A On resistance 4.2 4.3 4.4 High-side output leakage current Low-side output leakage current High-side switch reverse diode forward voltage IOut 1-3 = +0.9A VOut 1-3 = 0V, output stages off VOut 1-3 = VVS, output stages off IOut 1-3 = 1.5A 2, 12, 15 2, 12, 15 2, 12, 15 2, 12, 15 2, 12, 15 2, 12, 15 2, 12, 15 2, 12, 15 2, 12, 15 2, 12, 15 2, 12, 15 2, 12, 15 2, 12, 15 RDSOn1-3 RDSOn1-3 IOut1-3 IOut1-3 VOut1-3 – VVS VOut 1-3 IOut1-3 –2 –60 300 1.8 1.8 Ω Ω µA µA A A A A Test Conditions Pin Symbol ΔTj switch off Tj switch off/ TjPW set Tj switch on/ TjPW reset 1.05 Min. Typ. 15 Max. Unit °C Type* B 3.7 1.15 B 3.8 4 4.1 1.05 1.15 B 4.5 2 V A 4.6 Low-side switch reverse IOut 1-3 = –1.5A diode forward voltage High-side overcurrent limitation and shutdown 7.5V < VS < 20V threshold Low-side overcurrent limitation and shutdown 7.5V < VS < 20V threshold High-side overcurrent limitation and shutdown 20V < VS < 40V threshold Low-side overcurrent limitation and shutdown 20V < VS < 40V threshold Overcurrent shutdown delay time High-side open-load detection threshold Low-side open-load detection threshold Open-load detection delay time V A 4.7 1.0 1.3 1.7 AA A 4.8 IOut1-3 –1.7 –1.3 –1.0 A A 4.18 IOut1-3 1.0 1.3 2.0 AA A 4.19 IOut1-3 tdSd IOut1-3 IOut1-3 tdSd –2.0 –1.3 –1.0 A A 4.9 4.10 4.11 4.12 10 –55 5 200 –30 30 40 –5 55 600 µs mA mA µs A A A A *) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Delay time between rising edge of the input signal at pin CS after data transmission and switch on output stages to 90% of final level. Device not in standby for t > 1 ms 9 4912E–AUTO–02/10 8. Electrical Characteristics (Continued) 7.5V < VVS < 40V; 4.75V < VVCC < 5.25 V; INH = High; –40°C ≤ Tj ≤ 200° C; Ta ≤ 150°C; unless otherwise specified, all values refer to GND pins. No. 4.13 4.14 4.15 4.16 Parameters Test Conditions Pin Symbol tdon tdon tdoff tdoff tdon – tdoff 1 Min. Typ. Max. 20 20 20 3 Unit µs µs µs µs Type* A A A A High-side output switch VVS = 13V RLoad = 30Ω on delay(1) Low-side output switch VVS = 13V on delay(1) RLoad = 30Ω High-side output switch VVS = 13V off delay(1) RLoad = 30Ω Low-side output switch VVS = 13V off delay(1) RLoad = 30Ω Dead time between corresponding highand low-side switches Input voltage low-level threshold Input voltage high-level threshold Hysteresis of input voltage Pull-down current pin DI, CLK, INH Pull-up current Pin CS VDI, VCLK, VINH = VCC VCS = 0V VVS = 13V RLoad = 30Ω 4.17 5 5.1 5.2 5.3 5.4 5.5 6 6.1 6.2 6.3 7 7.1 µs A Logic Inputs DI, CLK, CS, INH 3, 4, 5, 8 3, 4, 5, 8 3, 4, 5, 8 4, 5, 8 3 VIL VIH ΔVI IPD IPU 50 5 –70 0.3 × VVCC 0.7 × VVCC 700 70 –5 V V mV µA µA A A B A A Serial Interface – Logic Output DO Output-voltage low level IDOL = 2 mA Output-voltage high level Leakage current (tri-state) Inhibit Input - Timing Delay time from standby to normal operation tdINH 100 µs A IDOL = –2 mA VCS = VCC 0V < VDO < VVCC 7 7 7 VDOL VDOH IDO VVCC –0.7V –15 +15 0.4 V V µA A A A *) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Delay time between rising edge of the input signal at pin CS after data transmission and switch on output stages to 90% of final level. Device not in standby for t > 1 ms 10 ATA6827 4912E–AUTO–02/10 ATA6827 9. Serial Interface – Timing No. 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 Parameters Test Conditions Pin 7 7 7 7 7 3 3 3 5 5 5 5 5 4 4 Timing Chart No.(1) 1 2 10 4 8 9 5 6 7 3 11 12 Symbol tENDO tDISDO tDOf tDOr tDOVal tCSSethl tCSSetlh tCSh tCLKh tCLKl tCLKp tCLKSethl tCLKSetlh tDIset tDIHold 225 225 500 225 225 500 225 225 40 40 Min. Typ. Max. 200 200 100 100 200 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Type* D D D D D D D D D D D D D D D DO enable after CS CDO = 100 pF falling edge DO disable after CS CDO = 100 pF rising edge DO fall time DO rise time DO valid time CS setup time CS setup time CS high time CLK high time CDO = 100 pF CDO = 100 pF CDO = 100 pF 8.10 CLK low time 8.11 CLK period time 8.12 CLK setup time 8.13 CLK setup time 8.14 DI setup time 8.15 DI hold time *) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Serial Interface Timing with Chart Numbers 11 4912E–AUTO–02/10 Figure 9-1. Serial Interface Timing with Chart Numbers 1 2 CS DO 9 CS 4 7 CLK 5 3 6 8 DI 11 CLK 10 12 DO Inputs DI, CLK, CS: High level = 0.7 × VCC, low level = 0.3 × VCC Output DO: High level = 0.8 × VCC, low level = 0.2 × VCC 12 ATA6827 4912E–AUTO–02/10 ATA6827 10. Application Circuit Figure 10-1. Application Circuit VCC U5021M Watchdog Enable n. u. n. u. VS O S C n. u. n. u. n. u. n. u. n. u. H n. S u. 3 L S 3 H S 2 L S 2 H S 1 L S 1 S R R 10 11 Serial interface Charge pump L S 1 T P VS VS BYT41D VBatt Input register Ouput register 13V Reset Trigger + DI 4 CLK 5 P S F O P L S C D n. u. n. u. n. u. n. u. n. u. n. H u. S 3 L S 3 H S 2 L S 2 H S 1 CS 3 Microcontroller INH 8 DO 7 Fault detector Fault detector Fault detector UV protection 9 Control logic VCC Power on reset 14 GND VCC VCC 5V + Fault detector Fault detector Fault detector 17 GND Thermal protection 18 GND 6 GND OUT1F VCC 1 2 OUT3F 13 12 OUT2F 16 15 M M 11. Application Notes It is strongly recommended to connect the blocking capacitors at VCC and VS as close as possible to the power supply and GND pins. Recommended value for capacitors at VS: Electrolytic capacitor C > 22 µF in parallel with a ceramic capacitor C = 100 nF. The value for electrolytic capacitor depends on external loads, conducted interferences and reverse conducting current IOut1,2,3 (see Section 4. “Absolute Maximum Ratings” on page 7). Recommended value for capacitors at VCC: Electrolytic capacitor C > 10 µF in parallel with a ceramic capacitor C = 100 nF. To reduce thermal resistance it is recommended to place cooling areas on the PCB as close as possible to the GND pins and to the die pad. 13 4912E–AUTO–02/10 12. Ordering Information Extended Type Number ATA6827-PIQW Package QFN18, 4 mm × 4 mm Remarks Taped and reeled, Pb-free 13. Package Information Package: VQFN_4 x 4_18L Exposed pad 2.7 x 3.175 Dimensions in mm Not indicated tolerances ±0.05 Top 18 Pin 1 identification 3.175±0.15 1 12 13 Z Bottom 2.5 0.5 nom. 18 1 2.5 7 0.175 6 2.7±0.15 technical drawings according to DIN specifications 4912E–AUTO–02/10 6 4 0.2 0.9±0.1 Z 10:1 0.23±0.07 Issue: 1; 26.04.07 14. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. 4912E-auto-02/10 History • Section 5 “Thermal Resistance” on page 7 changed • • • • • • Put datasheet in a new template Package drawing changed Block diagram changed Pinning drawing changed Pin Description table changed Application circuit drawing changed 4912D-auto-06/07 14 ATA6827 0.4±0.1 Drawing-No.: 6.543-5133.01-4 Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 International Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-en-Yvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Product Contact Web Site www.atmel.com Technical Support auto_drivers@atmel.com Sales Contact www.atmel.com/contacts Literature Requests www.atmel.com/literature Disclaimer: T he information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2010 Atmel Corporation. All rights reserved. A tmel®, logo and combinations thereof, and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. 4912E–AUTO–02/10