Features
• ATA6833 Temperature Range TJ = 150°C • ATA6834 Extended Temperature Range TJ = 200°C • Direct Driving of 6 External NMOS Transistors with a Maximum Switching Frequency of
50 kHz
• Integrated Charge Pump to Provide Gate Voltages for High-side Drivers and to Supply
the Gate of the External Battery Reverse Protection NMOS Built-in 5V/3.3V Voltage Regulator with Current Limitation Reset Signal for the Microcontroller Sleep Mode with Supply Current of typically < 45 µA Wake-up via LIN Bus or High Voltage Input Programmable Window Watchdog Battery Overvoltage Protection and Battery Undervoltage Management Overtemperature Warning and Protection (Shutdown) 200 mA Peak Current for Each Output Driver LIN Transceiver Conformal to LIN 2.1 and SAEJ2602-2 with Outstanding EMC and ESD Performance • QFN48 Package 7 mm × 7 mm
• • • • • • • • •
BLDC Motor Driver and LIN System Basis Chip ATA6833 ATA6834 Preliminary
1. Description
The ATA6833 and ATA6834 are system basis chips for three-phase brushless DC motor controllers designed in Atmel ® ’s state-of-the-art 0.8 µm SOI technology SMART-I.S.™1. In combination with a microcontroller and six discrete power MOSFETs, the system basis chip forms a BLDC motor control unit for automotive applications. In addition, the circuits provide a 3.3V/5V linear regulator and a window watchdog. The circuit includes various control and protection functions like overvoltage and overtemperature protection, short circuit detection, and undervoltage management. Thanks to these function blocks, the driver fulfils a maximum of safety requirements and offers a high integration level to save cost and space in various applications. The target applications are most suitable for the automotive market due to the robust technology and the high qualification level. ATA6834, in particular, is designed for applications in a high-temperature environment.
9122D–AUTO–09/09
Figure 1-1.
VBAT
Block Diagram
VBAT
VBATSW VINT VG
CPHI1 CPHI2 CPOUT CPLO1 CPLO2
PBAT
VMODE VCC
3.3/5V VCC Regulator
13V Regulator
CP
High-side Driver 3 High-side Driver 2
H3
DG1 DG2 DG3
H2
Supervisor: Short Circuit Overtemperature Undervoltage
VINT 5V Regulator
VBG
Oscillator
High-side Driver 1
H1 S1 S2 S3
Microcontroller
/RESET WD IH1-3 IL1-3
M
Logic Control
ATA6833/34
Low-side Driver 1 Low-side Driver 2
L1
RX TX
LIN
WD Timer
CC Timer
Low-side Driver 3
L3
Hall A Hall B Hall C
LIN
EN1 EN2 GND RWD WDD
CC
PGND
2
ATA6833/ATA6834 [Preliminary]
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Hall A Hall B Hall C
L2
ATA6833/ATA6834 [Preliminary]
2. Pin Configuration
Figure 2-1. Pinning QFN48
VBATSW EN2 VBAT NC VCC PGND L3 L2 L1 VG PBAT NC VMODE VINT RWD CC /RESET WD WDD EN1 NC NC GND NC 48 47 46 45 44 43 42 41 40 39 38 37 36 1 35 2 34 3 33 4 32 5 Atmel YWW 31 6 ATA6833/ATA6834 30 7 ZZZZZ-AL 29 8 28 9 27 10 26 11 25 12 13 14 15 16 17 18 19 20 21 22 23 24 LIN NC TXD IL3 IH3 IL2 IH2 IL1 IH1 RXD DG1 DG2 CPLO1 CPHI1 CPLO2 CPHI2 CPOUT S1 H1 S2 H2 S3 H3 DG3
Note:
YWW ATA683x ZZZZZ AL
Date code (Y = Year - above 2000, WW = week number) Product name Wafer lot number Assembly sub-lot number
Table 2-1.
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
Pin Description
Symbol VMODE VINT RWD CC /RESET WD WDD EN1 N.C. N.C. GND NC LIN NC TXD IL3 IH3 I I I I/O I I/O I I/O I I/O O I I I Function Selector for VCC and interface logic voltage level Blocking capacitor Resistor defining the watchdog interval RC combination to adjust cross conduction time Reset signal for microcontroller Watchdog trigger signal Enable and disable the watchdog Microcontroller output to switch system in Sleep Mode Connect to GND Connect to GND Ground Connect to GND LIN-bus terminal Connect to GND Transmit signal to LIN bus from microcontroller Control Input for output L3 Control Input for output H3
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Table 2-1.
Pin 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
Pin Description
Symbol IL2 IH2 IL1 IH1 RXD DG1 DG2 DG3 H3 S3 H2 S2 H1 S1 CPOUT CPHI2 CPLO2 CPHI1 CPLO1 NC PBAT VG L1 L2 L3 PGND VCC NC VBAT EN2 VBATSW I I O I I/O O O O I O I/O I I I I O O O O O I/O O I/O O I/O I/O I O I O Function Control Input for output L2 Control Input for output H2 Control Input for output L1 Control Input for output H1 Receive signal from LIN bus for microcontroller Diagnostic output 1 Diagnostic output 2 Diagnostic output 3 Gate voltage high-side 3 Voltage at half bridge 3 Gate voltage high-side 2 Voltage at half bridge 2 Gate voltage high-side 1 Voltage at half bridge 1 Charge pump output capacitor Charge pump capacitor 2 Charge pump capacitor 2 Charge pump capacitor 1 Charge pump capacitor 1 Connect to GND Power supply (after reverse protection) for charge pump and gate drivers Blocking capacitor Gate voltage H-bridge, low-side 1 Gate voltage H-bridge, low-side 2 Gate voltage H-bridge, low-side 3 Power ground for H-bridge and charge pump 5V/100 mA supply for microcontroller Connect to GND Supply voltage for IC core (after reverse protection) High voltage enable input 100Ω PMOS switch from VBAT
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ATA6833/ATA6834 [Preliminary]
3. Functional Description
3.1
3.1.1
Power Supply Unit with Supervisor Functions
Power Supply The IC has to be supplied by a reverse-protected battery voltage. To prevent damage to the IC, proper external protection circuitry has to be added. It is recommended to use at least one capacitor combination of storage and RF capacitors behind the reverse protection circuitry, which is connected close to the VBAT and GND pins of the IC. A fully integrated low-power and low-drop regulator (VINT regulator), stabilized by an external blocking capacitor, provides the necessary low-voltage supply needed for the wake-up process. A trimmed low-power band gap is used as reference for the VINT regulator as well as for the VCC regulator. All internal blocks are supplied by VINT regulator. VINT regulator must not be used for any external supply purposes. Nothing inside the IC except the logic interface to the external microcontroller is supplied by the 5V/3.3V VCC regulator. Both voltage regulators are checked by a “power-good comparator”, which keeps the whole chip in reset as long as the internal supply voltage (VINT regulator output) is too low and generates a reset for the external microcontroller if the output voltage of the VCC regulator is not sufficient.
3.1.2
VBatt Switch This high-voltage switch provides the battery voltage at pin VBATSW for various purposes. It is switched ON after power on reset when the IC transits to Active Mode and it will only turn OFF when the IC changes to Sleep Mode. Watchdog resets do not have an effect on the switch. The switch can be used for measuring purposes as well as to switch on external voltage regulators.
3.1.3
Voltage Supervisor This function is implemented to protect the IC and the external power MOS transistors from damage due to overvoltage on PBAT input. In the event of overvoltage (VTHOV) or undervoltage (VTHUV), the external NMOS motor driver transistors will be switched off. The failure state will be flagged on DG2 pin. It is recommended to block PBAT with an external RF capacitor to suppress high frequency disturbances. Temperature Supervisor An integrated temperature sensor prevents the IC from overheating. If the temperature is above the overtemperature pre-warning threshold TJPW set, the diagnostic pin DG3 will be switched to HIGH to signal this event to the external microcontroller. The microcontroller should take actions to reduce the power dissipation in the IC. If the temperature rises above the overtemperature shutdown threshold TJ switch off, the VCC regulator and all output drivers together with the LIN transceiver will be switched OFF immediately and the /RESET signal will go LOW. Both thresholds have a built-in hysteresis to avoid oscillations. The IC will return to normal operation (Active Mode) when it has cooled down below the shutdown threshold. When the junction temperature drops below the pre-warning threshold, bit DG3 will be switched LOW.
3.1.4
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3.2
Active Mode and Sleep Mode
The IC has two modes: Sleep Mode and Active Mode. Switching between the modes is described below. By default the IC starts in Active Mode (which means normal operation) after power-on. A Go to Sleep procedure switches the IC from Active Mode to Sleep Mode (standby). A Go to Active procedure brings the IC back from Sleep Mode to Active Mode. When in Sleep Mode the internal 5V supply (VINT regulator), the EN2 pin input structure, and a certain part of the LIN receiver remain active to ensure a proper startup of the system. The VCC regulator is turned off. The Go to Sleep and Go to Active procedures are implemented as follows: Go to Sleep: Pin EN1 is a low-voltage input supplied by the VCC regulator. It is ESD protected by diodes against VCC and GND. Thus the input voltage at pin EN1 must not go below GND or exceed the output voltage of the VCC regulator. A transition from HIGH to LOW followed by a permanent LOW signal for a minimum time period tgotosleep (typical 10 µs) at pin EN1 switches the IC to Sleep Mode as the EN1 is edge triggered. VCC is switched off in Sleep Mode. It is recommended to keep EN1 LOW during normal operation. Go to Active Using Pin EN2: Pin EN2 is a high-voltage input for external wake-up signals. Its input structure consists of a comparator with a built-in hysteresis. It is ESD-protected by diodes against GND and VBAT, B, and for this reason the applied input voltage must not go below GND or exceed VBAT. Pulling EN2 up to VBAT switches the IC to Active Mode. EN2 is debounced and edge triggered. Go to Active Using the LIN Interface: Using the LIN interface provides a second possibility to wake-up the IC (see Figure 3-1). A falling edge at pin LIN followed by a dominant bus level maintained for a minimum time period (Tbus) and ending with a rising edge leads to a remote wake-up request. The device switches from Sleep Mode to Active Mode. The VCC regulator is activated and the internal LIN slave termination resistor is switched on. Figure 3-1. Wake-up Using the LIN Interface
Active Mode Sleep Mode Active Mode
EN1 Tdebounce VCC
LIN
Tgotosleep = 10 µs
Tbus = 90 µs
Regulator Wake-up Time = 4 × TOSC
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ATA6833/ATA6834 [Preliminary]
3.3 5V/3.3V VCC Regulator
The 5V/3.3V regulator is fully integrated. It requires an external electrolytic capacitor in the range of 2.2 µF up to 10 µF and with an ESR in the range from 2Ω to 15Ω for stability (see Figure 3-2). The output voltage can be configured as either 5V or 3.3V by connecting pin VMODE to either pin VINT or GND. Since the regulator is not designed to be switched between both output voltages during operation, it is advisable to hard-wire VMODE pin. The logic levels of the microcontroller interface are adapted to the VCC regulator output voltage. The maximum output current (IOS1) of the regulator is 100 mA. For TJ > 150°C the IOS1 of ATA6834 is reduced to 80 mA. The VCC regulator has a built-in short circuit protection. A comparator checks the output voltage of the VCC regulator and keeps the external microcontroller in reset as long as the voltage is below the lower operation minimum (shown in Figure 3-33). Figure 3-2.
40 35 20 30 ESRmax (CVCC = 10 µF)
ESR versus Load Current for External Capacitors with Different Values
ESR versus Load Current at Pin VCC
25
ESR versus Load Current at Pin VCC
ESR (Ω)
ESR (Ω)
25 20 15 10 5 0 0 25
ESRmax (CVCC = 2.2 µF)
15
10
ESRmin (CVCC = 2.2 µF)
5
ESRmin (CVCC = 10 µF)
0 50 75 10 0 12 5 150 0 25 50 75 10 0 12 5 150
Load Current (mA)
Load Current (mA)
Figure 3-3.
/RESET as Function of the VCC Output Voltage
VCC
100% VCC 88% VCC 80% VCC
0V
/RESET
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3.4
Reset and Watchdog Management
The watchdog timing is based on the trimmed internal watchdog oscillator. Its period time TOSC is determined by the external resistor RWD. A HIGH signal on WDD pin enables the watchdog function; a LOW signal disables it. Since WDD pin is equipped with an internal pull-up resistor the watchdog is enabled by default. In order to keep the current consumption as low as possible the watchdog is switched off during Sleep Mode. The timing diagram in Figure 3-4 shows the watchdog and external reset timing.
Figure 3-4.
Timing Diagram of the Watchdog in Conjunction with the /RESET Signal
VCC
88% VCC
/RESET
Watchdog trigger edge
Watchdog trigger in t2 window
WD
t1 tres td tres td t2
tresshort t1 t2 t1
Reset and lead Reset and lead time, Watchdog cycle, time, no trigger trigger during lead time no trigger
Watchdog cycle, trigger during t2 window
After power-up of the VCC regulator (VCC output exceeds 88% of its nominal value) /RESET output stays LOW for the timeout period tres (typical 10 ms). Subsequently /RESET output switches to HIGH. During the following time td (typical 500 ms) a rising edge at the input WD is expected otherwise another external reset will be triggered. When the watchdog has been correctly triggered for the first time, normal watch-dog operation begins. A normal watchdog cycle consists of two time sections t1 and t2 followed by a short pulse for the time tresshort at /RESET if no valid trigger has been applied at pin WD during t2. Rising edges on WD pin during t1 also cause a short pulse on /RESET. Start for such a cycle is always the time of the last rising edge either on WD pin or on /RESET pin. If the watchdog is disabled (WDD = LOW), only the initial reset for the time tres after power-up will be generated. Additional resets will be generated if the VCC output voltage drops below 80% of its nominal value. The following example demonstrates how to calculate the timing scheme for valid watchdog trigger pulses, which the external microcontroller has to provide in order to prevent undesired resets.
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ATA6833/ATA6834 [Preliminary]
Example: Using an external resistor RWD = 33 kΩ ±1% results in typical parameters as follows: TOSC = 12.32 µs t1 = 980 × TOSC = 12.07 ms ±10% t2 = 780 × TOSC = 9.609 ms ±10% t1 + t2 = 21.68 ms ±10% Hence, the minimum time the external microcontroller has to wait before pin WD can be triggered is in worst case tmin = 1.1 × t1 = 13.28 ms. The maximum time for the watchdog trigger on WD pin is t max = 0.9 × (t1 + t2) = 19.51 ms. Thus watchdog trigger input must remain within tmax – tmin = 6.23 ms. Other values can be set up by picking a different resistor value for RWD. The dependency of TOSC on the value of RWD is shown in Figure 3-5. Figure 3-5. TOSC versus RWD
45 40 35 TOSC (µs)
TOSC (µs)
30 25 20 15 TOSCmin (µs) 10 5 0 10 20 30 40 50 60 70 80 90 10 0 TOSCmax (µs)
RWD (kΩ)
3.5
Charge Pump
A charge pump has been implemented in order to provide sufficient voltage to operate the external high-side power-NMOS transistors and the VG regulator, which drives the low-side Power-NMOS transistors. The charge pump output voltage at CPOUT pin is controlled to settle typically about 15V above the voltage at pin PBAT. A built-in supervisor circuit checks if the output voltage is sufficient to operate the VG regulator and external Power-NMOS transistors. The output voltage is accepted as good when it rises above VCPCPGOOD. A charge pump failure is flagged at DG2 if this minimum can not be reached or if the output voltage drops below the lower threshold of VCPCPGOOD due to overloading. The two shuffle capacitors should have the same value. The value of the reservoir capacitor should be at least twice the value of one shuffle capacitor. Two external shuffle capacitors and an external reservoir capacitor have to be provided. The typical values for the two shuffle capacitor is 100 nF, and for the reservoir capacitor is 470 nF. All capacitors should be ceramic. It is advisable to pick a reservoir capacitor with twice or three-times the size of the two equally-sized shuffle capacitors. The greater the capacitors, the greater the output current capability.
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3.6
VG Regulator
The VG regulator provides a stable voltage to supply the low-side gate drivers and to deliver sufficient voltage for the external low-side Power-NMOS transistors. Typically the output voltage is 12V. In order to guarantee reliable operation even with a low battery voltage, the VG regulator is supplied by the charge pump output. For stability, an external ceramic capacitor of typically 470 nF has to be provided. There is no internal supervision of the VG output voltage.
3.7
Output Drivers and Control Inputs IL1-IL3, IH1-IH3
This IC offers six push-pull output drivers for the external low-side and high-side power-NMOS transistors. To guarantee reliable operation, the low-side drivers are supplied by the VG regulator while the high-side drivers are supplied directly by the charge pump. All drivers are designed to operate at switching frequencies in the range of DC up to 50 kHz. The maximum gate charge that can be delivered to each external Power-NMOS transistor at 50 kHz is 100 nC. The output drivers are directly controlled by the digital input pins IL1 to IL3 and IH1 to IH3 (see Table 3-1). All pins are equipped with an internal pull-down resistor. To operate the output drivers properly the following requirements have to be fulfilled: 1. Device is in Active Mode. 2. In case of watchdog is enabled, at least one valid watchdog trigger has been accepted. 3. The voltage at pin PBAT lies within its operation range. Neither undervoltage nor overvoltage is present. 4. The charge pump output voltage has been accepted as good, thus it exceeded VCPCPGOOD. 5. No overtemperature shutdown has occurred. If a short circuit is detected by one of the sense inputs S1 to S3, the output drivers will be switched off after a debounce time of 6 µs and the output DG1 will be flagged (see also Section 3.8 “Short Circuit Detection” on page 11). The output drivers will be enabled again and DG1 will be cleared with a rising edge at one of the control inputs (IL1 to IL3, IH1 to IH3). Additional logic prevents short circuits due to switching on one power-NMOS transistor while the opposite one in the same branch is switched on already.
Table 3-1.
Status of the Output Drivers Depending on the Control Inputs
Control Inputs IL[1..3] X 0 1 0 1 Control Inputs IH[1..3] X 0 0 1 1 Driver Stage for External Power MOS L[1..3], H[1..3] OFF OFF L[1..3] ON, H[1..3] OFF H[1..3] ON, L[1..3] OFF OFF Shoot-through protection
Mode Sleep Active Active Active Active
Comments Sleep Mode
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3.8 Short Circuit Detection
Short circuits in the motor bridge circuitry are sensed by S1 to S3 inputs. Internal comparators monitor the voltage differences between the drain and the source terminals of the external power-NMOS transistors. If one transistor switches on and its drain-source voltage exceeds VSC threshold (typically 4V) after a blanking time tSC (typically 6 µs, see Figure 3-6), a short circuit in this branch will be detected. In this case, all output drivers will be switched off immediately and pin DG1 will be set to HIGH. With a rising edge at any of the pins IL1 to IL3 or IH1 to IH3, the diagnostic output DG1will be reset and the drivers can be switched on again.
3.9
Cross Conduction Timer
In order to prevent damage of the motor bridge due to peak currents a non-overlapping phase for switching the power-NMOS transistors is mandatory. Therefore, a cross conduction timer has been implemented to prevent switching on any output driver for a time tCC after any other driver has been switched off. This also accounts for toggling any other driver after a short circuit was detected. An external RC parallel combination defines the value for tCC and can be estimated as follows: tCC = KCC × RCC [kΩ] × CCC [nF], KCC is specified in Section 8. “Electrical Characteristics” on page 16. The RC combination is connected between CC and GND pins. When one of the drivers has been switched off the RC combination is charged to 5V (VINT) and discharged with its time constant. Any low to high transition at the control inputs will be masked out at the driver outputs until the voltage at CC pin drops below 67% of its initial value (VINT). The timer will be re-triggered at any time by any falling edge at the control inputs. This is shown in the following figure. Figure 3-6. Interaction of Short Circuit Detection and Cross Conduction Timer
IL1 L1
Ignore VS1
IH1 H1
Shut off if VPBAT - VS1 > 4V
for tSC = 6 µs
Shut off if VS1 > 4V
Ignore VPBAT - VS1 for tSC = 6 µs
IL3 L3
Ignore VS3
VCC = VVINT CC VCC = 67% VVINT tcc
for tSC = 6 µs
Shut off if VS3 > 4V
tcc
tcc
At least 5 kΩ minimum and 5 nF at maximum should be used as values for the RC combination. 10 kΩ is recommended. If the non-overlapping phase is controlled by the external microcontroller, it is possible to do without the external capacitor. The minimum time tCC is defined by the parasitic capacitance at CC pin. 11
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3.10
Diagnostic Outputs D1 - D3
As mentioned in the sections above, the diagnostic outputs DG1 to DG3 are used to signal failures. This is summarized in the following table.
Table 3-2.
CPOK 0 X X X X Note:
Status of the Diagnostic Outputs (Normal Operation)
Device Status OT1 X 1 X X X OV X X 1 X X UV X X X 1 X SC X X X X 1 Diagnostic Outputs DG1 – – – – 1 DG2 1 – 1 1 – DG3 – 1 – – – Charge pump failure Overtemperature prewarning Overvoltage Undervoltage Short circuit Comments
X represents: no effect) OT1: overtemperature warning OV: overvoltage of PBAT UV: undervoltage of PBAT SC: short circuit CPOK: charge pump OK
In order to differentiate between LIN and EN2 wake-up, DG1 output will be set to LOW or HIGH respectively. LOW indicates wake-up by LIN, HIGH indicates wake-up by EN2. DG1 output will be cleared by the first valid watchdog trigger after wake-up or by the first rising edge at one of the control inputs (IL1 to IL3 and IH1 toIH3) if the watchdog is disabled.
Table 3-3.
DG1 1 0
Indicating Wake-up Source
Diagnostic Outputs DG2 – – DG3 – – Wake-up Source EN2 LIN
3.11
LIN Transceiver
ATA6833 and ATA6834 include a fully integrated LIN transceiver complying with LIN specification 2.1 and SAEJ2602 2. The transceiver consists of a low-side driver with slew rate control, wave shaping, current limiting, and a high voltage comparator followed by a debouncing unit in the receiver. During transmission, the data applied at pin TXD will be transferred to the bus driver to generate a bus signal on LIN pin. TXD input has an internal pull-up resistor. To minimize the electromagnetic emission of the bus line, the bus driver has a built-in slew rate control and wave-shaping unit. The transmission will be aborted by a thermal shutdown or by a transition to Sleep Mode.
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ATA6833/ATA6834 [Preliminary]
Figure 3-7. Definition of Bus Timing Parameters
tBit TXD (Input to transmitting node) tBit tBit
tBus_dom(max)
tBus_rec(min)
THRec(max) VS (Transceiver supply of transmitting node) THDom(max) LIN Bus Signal THRec(min) THDom(min)
Thresholds of receiving node1
Thresholds of receiving node2
tBus_dom(min)
tBus_rec(max)
RXD (Output of receiving node1) trx_pdf(1) trx_pdr(1)
RXD (Output of receiving node2) trx_pdr(2) trx_pdf(2)
The recessive BUS level is generated from the integrated 30 kΩ pull-up resistor in series with an active diode. This diode protects against reverse currents on the bus line in case of a voltage difference between the bus line and VSUP (VBUS > VSUP). No additional termination resistor is necessary to use the IC as a LIN slave. If this IC is used as a LIN master, the LIN pin is terminated by an external 1 kΩ resistor in series with a diode to VBAT. As PWM communication directly over the LIN transceiver in both directions is possible, there is no TXD timeout feature implemented in the LIN transceiver.
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4. Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All voltages are referenced to pin GND. [xxx] Values for the ATA6834. Parameters Input voltage Negative input current Negative input current Supply voltage Supply voltage Logic output voltage Logic input voltage Output voltage Analog input voltage Digital input voltage Digital input voltage Output voltage Input voltage Output voltage Output voltage Output voltage Charge pump Charge pump Output voltage Output voltage Storage temperature Note: Estimated values take TJ > 150°C into account. Pin PGND VBAT PBAT VBAT PBAT /RESET, DG1, DG2, DG3, RXD IL1-3, IH1-3, WD, WDD, EN1, TXD VINT, VCC RWD, CC EN2 VMODE VG LIN S1, S2, S3 L1, L2, L3 H1, H2, L3 CPLO1, 2 CPHI1, 2 CPOUT VBATSW Symbol VPGND IVBAT IPBAT VVBAT VPBAT V/RESET, VDG1, VDG2, VDG3, VRXD VIL1-3, VIH1-3, VWD, VEN1, VTXD VINT, VVVCC VRWD VEN2 VVMODE VVG VVLIN VS1, VS2, VS3 VL1, VL2, VL3 VH1, VH2, VH3 VCPLO1, VCPLO2 VCPHO1, VCPHO2 VCPOUT VVBATSW TStorage Min. –0.3 –15 –20 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –27 –6 VPGND – 0.3 VS1, 2, 3 – 1 –0.3 –0.3 –0.3 –0.3 –55 +40 (500 ms) +40 (500 ms) VVCC + 0.3 VVCC + 0.3 +5.5 VVCC + 0.3 VVBAT + 0.3 VVINT + 0.3 +16 VVBAT + 2 +30 VVG + 0.3 VS1, 2, 3 + 16 VPBAT + 0.3 VCPOUT + 0.3 +40 VVBAT + 0.3 +150 Max. +0.3 Unit V mA mA V V V V V V V V V V V V V V V V V °C
5. Thermal Resistance
Parameters Thermal resistance junction to heat slug Thermal resistance junction to ambient when heat slug is soldered to PCB Symbol Rthjc Rthja Value 7V Overvoltage lock-out threshold
1.5 Internal power supply 1.6
1.7 Overvoltage hysteresis Undervoltage lock-out 1.8 threshold 1.9 Undervoltage threshold hysteresis
1.10 RDSON VBAT-Switch switch 1.11 Thermal prewarning set 1.12 Thermal prewarning reset 1.13 Thermal prewarning hysteresis
VBATSW RON_VBATSW TJPW set TJPW reset ΔTJPW TJ switch off TJ switch on ΔTJ switch off TJ switch off/ TJPW set TJ switch on/ TJPW reset
1.14 Thermal shutdown off 1.15 Thermal shutdown on 1.16 1.17 Thermal shutdown hysteresis Ratio thermal shutdown off/thermal prewarning set
Ratio thermal shutdown 1.18 on/thermal prewarning reset 2 5V/3.3V Regulator VMODE = VINT, 7V < VBAT < 40V VMODE = GND, 5.5V < VBAT < 40V ILoad = 0 to 100 mA VMODE = VINT, 7V < VBAT < 40V VMODE = GND, 5.5V < VBAT < 40V ILoad = 0 to 80 mA 150°C < TJ < 200°C VCC
1.05
1.15
B
2.1 Regulated output voltage
VVCC
4.85 3.20 4.85 3.20
5.15 3.40 5.15 3.40
V
A
2.2 Regulated output voltage
VCC
VVCC
V
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
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8. Electrical Characteristics (Continued)
All parameters given are valid for 5.5V ≤ VVBAT ≤ 18V and for –40°C ≤ TJ ≤ 150°C (200°C) unless stated otherwise. All values refer to PIN GND. [xxx] Values for the ATA6834. No. Parameters 2.3 Regulated output voltage Test Conditions VMODE = VINT, 5.5V < VBAT < 7V VMODE = GND, 5V < VBAT < 5.5V ILoad = 0 to 60 mA VMODE = VINT, 5.5V < VBAT < 7V VMODE = GND, 5V < VBAT < 5.5V ILoad = 0 to 50 mA 150°C < TJ < 200°C VMODE = VINT, 7V < VBAT < 40V VMODE = GND, 5.5V < VBAT < 40V ILoad = 50 mA, –40°C < TJ < 150°C VMODE = VINT, VBAT > 7V VMODE = GND, VBAT > 5.5V ILoad = 0 to 100 mA ILoad = 0 to 80 mA, 150°C < TJ < 200°C VMODE = VINT, VBAT > 7V VMODE = GND, VBAT > 5.5V ILoad @ RESET VMODE = VINT, VBAT > 7V VMODE = GND, VBAT > 5.5V ILoad @ RESET, 150°C < TJ < 200°C Pin VCC Symbol VVCC Min. 4.50 2.97 4.50 2.97 Typ. Max. 5.15 3.40 5.15 3.40 Unit Type* V A
2.4 Regulated output voltage
VCC
VVCC
V
A
2.5 Line regulation
VCC
50 50 50 50
mV
A
2.6 Load regulation
VCC
mV
A
2.7 Output current limit
VCC
IOS1
100 100 70 70
360 360 360 360
mA
A
2.8 Output current limit
VCC
IOS1 VVMODE H VVMODE L
mA
C
2.12 HIGH threshold VMODE 2.13 LOW threshold VMODE 3 3.1 Reset and Watchdog VCC threshold voltage level VMODE = VINT for /RESET (VMODE = GND) VMODE = VINT (VMODE = GND)
4.0 0.7 3.8 2.5 0.2 0.13 8 1.6 400 4.2 2.8 0.6 0.4 12 2.4 600 2 11.09 980 × TOSC 780 × TOSC 0.4 5 10 15 13.55
V V
A A A B A B A A A C A A A
VtHRESHLow HYSRESth tres tresshort td tdelayRESL TOSC t1 t2
V V ms ms ms µs µs
3.2 Hysteresis 3.3 Length of pulse at /RESET 3.4 Length of short pulse at /RESET Time for VCC < VtHRESL before activating /RESET
3.5 Wait for the first WD trigger 3.6
3.8 Watchdog oscillator period RRWD = 33 kΩ 3.12 Close window 3.13 Open window 3.14 3.15 Output low-level at pin /RESET Internal pull-up resistor at pin /RESET IOLRES = 1 mA
VOLRES RPURES
V kΩ
A D
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
17
9122D–AUTO–09/09
8. Electrical Characteristics (Continued)
All parameters given are valid for 5.5V ≤ VVBAT ≤ 18V and for –40°C ≤ TJ ≤ 150°C (200°C) unless stated otherwise. All values refer to PIN GND. [xxx] Values for the ATA6834. No. Parameters 4 LIN Transceiver Normal mode; VLIN = 0V, VRXD = 0.4V Normal mode; VLIN = VBAT VRXD = VCC – 0.4V VTXD = VCC; ILIN = 0 mA VVBAT = 7.3V Rload = 500Ω VVBAT = 18V Rload = 500Ω VVBAT = 7.3V Rload = 1000Ω VVBAT = 18V Rload = 1000Ω serial diode required VBUS = VBAT_max ILRXD IHRXD VBUSrec V_LoSUP V_HiSUP V_LoSUP_1k V_HiSUP_1k_ RLIN IBUS_LIM IBUS_PAS_dom 0.6 0.8 20 50 47 200 0.9 × VBAT 1.2 2 2 –2 mA mA V V V V V kΩ mA D D A A A A A A A Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
4.1 Low-level output current 4.2 High-level output current 4.3 4.4 4.5 4.6 4.7 Driver recessive output voltage Driver dominant voltage VBUSdom_DRV_LoSUP Driver dominant voltage VBUSdom_DRV_HiSUP Driver dominant voltage VBUSdom_DRV_LoSUP Driver dominant voltage VBUSdom_DRV_HiSUP
4.8 Pull up resistor to VS 4.9 Current limitation
Input leakage current Input leakage current at the driver off 4.10 receiver including pull-up VBUS = 0V resistor as specified VBAT = 12V Leakage current LIN 4.11 recessive Driver off 8V < VBAT < 18V 8V < VBUS < 18V VBUS = VBAT
–1
mA
A
IBUS_PAS_rec
20
µA
A
Leakage current at ground loss Control unit disconnected GNDDevice = VS VBAT = 12V 4.12 from ground Loss of local ground must 0V < VBUS < 18V not affect communication in the residual network Node has to sustain the current that can flow under VBAT disconnected 4.13 this condition. Bus must VSUP_Device = GND remain operational under 0V < VBUS < 18V this condition 4.14 Center of receiver threshold 4.15 Receiver dominant state 4.16 Receiver recessive state 4.17 Receiver input hysteresis VBUS_CNT = (Vth_dom + Vth_rec)/2 VEN = 5V VEN = 5V VHYS = Vth_rec – Vth_dom
IBUS_NO_gnd
–1
+1
mA
A
IBUS
100
µA
A
VBUS_CNT VBUSdom VBUSrec VBUShys
0.475 × VVBAT
0.5 × VVBAT
0.525 × VVBAT 0.4 × VVBAT
V V V
A A A A
0.6 × VVBAT 0.175 × VVBAT
V
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
18
ATA6833/ATA6834 [Preliminary]
9122D–AUTO–09/09
ATA6833/ATA6834 [Preliminary]
8. Electrical Characteristics (Continued)
All parameters given are valid for 5.5V ≤ VVBAT ≤ 18V and for –40°C ≤ TJ ≤ 150°C (200°C) unless stated otherwise. All values refer to PIN GND. [xxx] Values for the ATA6834. No. Parameters Test Conditions 7V < VVBAT < 18V THrec(max) = 0.744 × VVBAT THDom(max) = 0.581 × VVBAT tBit = 50 µs D1 = tBus_rec(min)/(2 × tBit) Load1: 1 nF + 1 kΩ Load2: 10 nF + 500Ω 7V < VVBAT < 18V THrec(min) = 0.422 × VVBAT THDom(min) = 0.284 × VVBAT tBit = 50 µs D2 = tBus_rec(max)/(2×tBit) Load1: 1 nF + 1 kΩ Load2: 10 nF + 500Ω 7V < VVBAT < 18V THrec(max) = 0.778 × VVBAT THDom(max) = 0.616 × VVBAT tBit = 96 µs D3 = tBus_rec(min)/(2 × tBit) Load1: 1 nF + 1 kΩ Load2: 10 nF + 500Ω 7V < VVBAT < 18V THrec(max) = 0.389 × VVBAT THDom(max) = 0.251 × VVBAT tBit = 96 µs D4 = tBus_rec(min)/(2 × tBit) Load1: 1 nF + 1 kΩ Load2: 10 nF + 500Ω 7V < VVBAT < 18V trec_pd = max(trx_pdr, trx_pdf) 7V < VVBAT < 18V trx_sym = trx_pdr – trx_pdf Pin Symbol Min. Typ. Max. Unit Type*
4.18 Duty cycle 1
D1
0.396
A
4.19 Duty cycle 2
D2
0.581
A
4.20 Duty cycle 3
D3
0.417
A
4.21 Duty cycle 4
D4
0.590
A
4.22 Receiver propagation delay Symmetry of receiver 4.23 propagation delay rising edge minus falling edge 4.24 5
trx_pd trx_sym TBUS –2
6
µs
A
+2
µs
Dominant time for wake-up VLIN = 0V via LIN-bus Control Inputs EN1, IL1-3, IH1-3, WD, TX, WDD
30
90
150
µs
A
5.1 Input low-level threshold 5.2 Input high-level threshold 5.3 Hysteresis 5.4 Pull-down resistor 5.5 Pull-up resistor 5.7 Debounce time EN1 EN1, IL1-3, IH1-3, WD TXD, WDD
VIL VIH HYS RPD RPU tgotosleep 0.7 × VVCC 0.3 25 25 9 50 50 10
0.3 × VVCC
V V
A A C
100 100 11
kΩ kΩ µs
A A A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
19
9122D–AUTO–09/09
8. Electrical Characteristics (Continued)
All parameters given are valid for 5.5V ≤ VVBAT ≤ 18V and for –40°C ≤ TJ ≤ 150°C (200°C) unless stated otherwise. All values refer to PIN GND. [xxx] Values for the ATA6834. No. Parameters 6 Charge Pump VVBAT > 7V ILoadCPOUT = 0A ILoadVG = 0A CCP1,2 = 47 nF CCPOUT = 220 nF VVBAT > 7V ILoadCPOUT = 7.5 mA, ILoadVG = 0A CCP1,2 = 47 nF CCPOUT = 220 nF Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
6.1 Charge pump voltage
CPOUT
VCPOUT
VVBAT + 11V
VVBAT + 18
V
A
6.2 Charge pump voltage
CPOUT
VCPOUT
VVBAT +10V
V
A
6.3 6.4 7 7.1
Period charge pump oscillator Charge pump output voltage for active drivers VG Regulator VG Regulator Output Voltage VG Regulator Line Regulation VG Regulator Load Regulation H-bridge Driver Low-side driver HIGH output voltage ON-resistance of sink stage ILX = 100 mA of pins Lx ON-resistance of source stage of pins Lx ILX = 100 mA VBAT = 13.5V VCPOUT = 20V ILoadVG = 7.5 mA VBAT = 13.5V VCPOUT1 = 20V, VCPOUT2 = 35V ILoadVG = 7.5 mA VBAT = 13.5V VCPOUT = 25V ILoadVG1 = 1 mA, ILoadVG2 = 60 mA VG
TCP CPOUT VCPCPGOOD 5.25
2.5 8.0
µs V
B A
VVG
11
12.5
14
V
A
7.2
VG
ΔVVG_Line
100
mV
A
7.3 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8
VG
ΔVVG_Load
100
mV
A
VLxH RDSON_LxL RDSON_LxH ILxL ILxH Lx to GND RLxsink RDSON_HxL RDSON_HxH 45 75 –100
VVG 20 20
V Ω Ω mA
D A A D D A A A
Output peak current at pins VLx = 3V Lx switched to LOW Output peak current at pins VLx = 3V Lx switched to HIGH Sink resistance between Lx and GND ON-resistance of sink stage VSx = 0V of pins Hx ON-resistance of source stage of pins Hx VSx = VVBAT IHx = 100 mA
100 115 20 20
mA kΩ Ω Ω
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
20
ATA6833/ATA6834 [Preliminary]
9122D–AUTO–09/09
ATA6833/ATA6834 [Preliminary]
8. Electrical Characteristics (Continued)
All parameters given are valid for 5.5V ≤ VVBAT ≤ 18V and for –40°C ≤ TJ ≤ 150°C (200°C) unless stated otherwise. All values refer to PIN GND. [xxx] Values for the ATA6834. No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* V – VSx = 0V; Output peak current at pins Hx VVBAT = 7V – 20V 8.9 Hx (switched from low to C = 10 nF high R = 1Ω V – VSx = 10V; Output peak current at pins Hx VVBAT = 7 – 20V 8.10 Hx (switched from high to C = 10 nF low) R = 1Ω V = 0V; Output peak current at pins Lx VVBAT = 7 – 20V 8.11 Hx (switched from low to C = 10 nF high R = 1Ω V = 10V; Output peak current at pins LX VVBAT = 7 – 20V 8.12 Hx (switched from high to C = 10 nF low) R = 1Ω 8.13 8.14 8.15 8.16 Output voltage low level pins Hx Output voltage high level pins Hx Sink resistance between Hx and Sx Sink resistance between Sx and GND Dynamic Parameters Propagation delay time, 8.17 low-side driver from high to low Propagation delay time, 8.18 low-side driver from low to high 8.19 Fall time low-side driver 8.20 Rise time low-side driver Propagation delay time, 8.21 high-side driver from high to low Propagation delay time, 8.22 high-side driver from low to high 8.23 Fall time high-side driver 8.24 Rise time high-side driver VVBAT = 13.5V, CGx = 5 nF VVBAT = 13.5V, CGx = 5 nF VVBAT = 13.5V CGx = 5 nF VVBAT = 13.5V CGx = 5 nF tLxHL 0.9 µs A Sx to GND VSx = 0V IHx = 1 mA IHx = –100 µA
IHxH,
–200
mA
C
IHxL
200
mA
C
ILxH,
–200
mA
C
ILxL
200
mA
C
VHxL VHxHstat RHxsink RSxsink VVCPOUT – 1V 45 75 1
0.3 VVCPOUT 115
V V kΩ MΩ
A A A D
tLxLH tLxf tLxr tHxHL
0.9
µs
A
0.3 0.3
µs µs
A A
0.9
µs
A
tHxLH tHxf tHxr
0.9
µs
A
0.2 0.2
µs µs
A A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
21
9122D–AUTO–09/09
8. Electrical Characteristics (Continued)
All parameters given are valid for 5.5V ≤ VVBAT ≤ 18V and for –40°C ≤ TJ ≤ 150°C (200°C) unless stated otherwise. All values refer to PIN GND. [xxx] Values for the ATA6834. No. Parameters 8.25 Short circuit detection voltage Cross Conduction Timer 8.27 9 Cross conduction time constant Input EN2 VIL VIH HYS RPD tdb VDG = 0.4V VDG = VCC – 0.4V IL IH 50 10 2 –2 2.3 2.8 0.47 100 20 200 25 3.6 4.0 V V V kΩ µs mA mA A A C A A A A KCC 0.345 0.465 B Test Conditions Pin Symbol VSC tSC Min. 3.5 5.4 Typ. 4 6 Max. 4.5 6.6 Unit Type* V µs A A
8.26 Short circuit blanking time
9.1 Input low level threshold 9.2 Input high level threshold 9.3 Hysteresis 9.4 Pull-down resistor 9.5 Debounce time 10 Diagnostic Outputs DG1, DG2, DG3 10.1 Low level output current 10.2 High level output current
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
22
ATA6833/ATA6834 [Preliminary]
9122D–AUTO–09/09
ATA6833/ATA6834 [Preliminary]
9. Application
This section describes the principal application for which the ATA6833/ATA6834 was designed. Figure 9-1.
Battery + CCPOUT
Typical Application
CVINT
CVG
CCP1
CCP2
VBATSW
CPOUT
CPLO1
CPLO2
CPHI1
CPHI2
VBAT
CVCC
VMODE VCC
PBAT
VINT
VG
3.3/5V VCC Regulator
13V Regulator
CP
High-side Driver 3 High-side Driver 2
H3
H2
DG1 DG2 DG3
Supervisor: Short Circuit Overtemperature Undervoltage
VINT 5V Regulator
VBG
Oscillator
High-side Driver 1
H1 S1 S2
Microcontroller
/RESET WD IH1-3 IL1-3 EN1
S3
Logic Control
ATA6833/34
Low-side Driver 1 Low-side Driver 2
L1
L2
RX TX
LIN
WD Timer
CC Timer
Low-side Driver 3
L3
ADC Hall C Hall B Hall A CCC
RWD
RCC
LIN KL 15
PGND
GND
WDD
RWD
EN2
LIN
CC
23
9122D–AUTO–09/09
Table 9-1.
Component CVINT CVCC ESL (CVCC) ESR (CVCC) CVG CCP1 CCP2 CCPOUT RRWD RCC CCC
Typical External Components
Function Blocking capacitor at VINT Blocking capacitor at VCC Serial inductance to CVCC including PCB Serial resistance to CVCC including PCB Blocking capacitor at VG Charge pump shuffle capacitor Charge pump shuffle capacitor Charge pump reservoir capacitor Resistor defining internal bias currents for watchdog oscillator Cross conduction time definition resistor Cross conduction time definition capacitor Min. 100 nF 1.5 µF 1 nH 2Ω 220 nF 47 nF 47 nF 220 nF 10 kΩ 5 kΩ 470 nF, 25V 220 nF/25V 220 nF/25V 470 nF, 25V 33 kΩ 10 kΩ 330 pF 5 nF Typical 220 nF/10V Max. 470 nF 10 µF 20 nH 15Ω 1 µF 470 nF 470 nF 1 µF 91 kΩ
24
ATA6833/ATA6834 [Preliminary]
9122D–AUTO–09/09
ATA6833/ATA6834 [Preliminary]
10. Ordering Information
Extended Type Number ATA6833-PLQW ATA6834-PLQW Package QFN48 QFN48 Remarks
11. Package Information
Package: VQFN_7 x 7_48L Exposed pad 4.5 x 4.5 Dimensions in mm Not indicated tolerances ±0.05 Top 48 1 Pin 1 identification 36 37 48 1 Bottom 4.5±0.15
12
25 24 7 0.2 0.9±0.1 Z 5.5 13
12
0.5 nom.
Z 10:1
0.4±0.1
Drawing-No.: 6.543-5137.01-4 Issue: 1; 19.10.06 0.23±0.07
technical drawings according to DIN specifications
25
9122D–AUTO–09/09
12. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. 9122D-AUTO-09/09 History • Section 4 “Absolute Maximum Ratings” on page 14 changed • Section 8 “Electrical Characteristics” numbers 2.7, 2.8, 3.1, 3.2, 4.20, 4.21, 6.4, 8.19, 8.20, 8.23, 8.24 and 8.27 on pages 16 to 22 changed • Features on page 1 changed • Section 7 “Noise and Surge Immunity, ESD and Latch-up” on page 15 changed • Put datasheet in the latest template • Section 8 “Electrical Characteristics” on pages 15 to 21 changed
9122C-AUTO-04/09
9122B-AUTO-10/08
26
ATA6833/ATA6834 [Preliminary]
9122D–AUTO–09/09
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9122D–AUTO–09/09
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