ATA6870-PLPW

Features • • • • • • • • • • • • • 12-bit Battery-cell Voltage Measurement Simultaneous Battery Cells Measurement in Parallel Cell Temperature Measurement Charge Balancing Capability – Parallel Balancing of Cells Possible Integrated Power Supply for MCU Undervoltage Detection Less than 10 µA Standby Current Low Cell Imbalance Current (< 10 µA) Hot Plug-in Capable Interrupt Timer for Cycling MCU Wake-ups Cost-efficient Solution Due to Cost-optimized 30V CMOS Technology Reliable Communication between Stacked ICs Due to Level Shifters with Current Sources and Checksum Monitoring of Data Daisy-chainable – Each IC Monitors up to 6 Battery Cells – 16 ICs (96 Cells) per String – No Limit on Number of Strings Package QFN48 7 mm × 7 mm • Li-Ion, NiMH Battery Measuring, Charge Balancing and Power-supply Circuit ATA6870 Preliminary Applications • Battery Measurement, Supply and Monitoring IC for Li-ion and NiMH Battery Systems in Electric (EV) and Hybrid Electrical (HEV) Vehicles Benefits • Highest Safety Level for Li-ion Battery Systems in Combination with ATA6871 • Cost Reduction Due to Integrated Measurement Circuit and High Voltage Power-supply 1. Description The ATA6870 is a measurement and monitoring circuit designed for Li-ion and NiMH multicell battery stacks in hybrid electrical vehicles. The ATA6870 monitors the battery-cell voltage and the battery-cell temperature with a 12-bit ADC. The circuit also provides charge-balancing capability for each battery-cell. In addition, a linear regulator is integrated to supply a microcontroller or other external components. Reliable communication between stacked ICs is achieved by level-shifters with current sources. The ATA6870 can be connected to three, four, five or six battery-cells. Up to 16 circuits (96 cells) can be cascaded in one string. The number of strings is not limited. 9116B–AUTO–10/09 2. Block Diagram Figure 2-1. Block Diagram To ATA6870 above VDDHV MBAT7 PD_N DISCH6 Cell 6: Reference ADC Cell Balancing Digital Level Shifter Standby Control PD_N_OUT VDDHVP 3.3V Voltage Regulator POW_ENA VDDHVM AVDD MBAT6 MBAT2 3.3V Internal Voltage Regulator Digital Level Shifter DVDD BIASRES DISCH1 MBAT1 TEMPREF Cell 1: Reference ADC Cell Balancing Logic Internal Biasing TEMP2 TEMP1 NTC NTC TEMPVSS Test Cell Temperature Measuring Digital Level Shifter Interchip and Microcontroller Communication Interface MISO_IN MOSI_OUT SCK_OUT CS_N_OUT CLK_OUT IRQ_IN CS_N SCK MOSI MISO IRQ CLK MCU GND AVSS DVSS SCANMODE PWTST DTST VDDFUSE MFIRST CS_FUSE ATST To ATA6870 below 2 ATA6870 [Preliminary] 9116B–AUTO–10/09 ATA6870 [Preliminary] 3. Pin Configuration Figure 3-1. Pinning QFN48, 7 mm × 7 mm CS_N_OUT SCK_OUT MOSI_OUT CLK_OUT DISCH6 VDDHV MBAT6 MBAT7 IRQ_IN MISO_IN VDDHVP 37 48 47 46 45 44 43 42 41 40 39 38 DISCH5 MBAT5 DISCH4 MBAT4 DISCH3 MBAT3 DISCH2 MBAT2 DISCH1 MBAT1 IRQ CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 PD_N 36 35 34 33 32 VDDHVM PD_N_OUT POW_ENA PWTST BIASRES ATA6870 31 30 29 28 27 26 25 TEMPREF TEMP2 TEMP1 TEMPVSS AVSS AVDD ATST SCANMODE Table 3-1. Pin Description Pad Name DISCH5 MBAT5 DISCH4 MBAT4 DISCH3 MBAT3 DISCH2 MBAT2 DISCH1 MBAT1 IRQ CLK CS_N SCK MOSI MISO MFIRST Function Heatslug Output to drive external cell-balancing transistor Battery cell sensing line Output to drive external cell-balancing transistor Battery cell sensing line Output to drive external cell-balancing transistor Battery cell sensing line Output to drive external cell-balancing transistor Battery cell sensing line Output to drive external cell-balancing transistor Battery cell sensing line Interrupt output for MCU/ATA6870 below System clock Chip select input from MCU/ATA6870 below SPI clock input from MCU/ATA6870 below Master Out Slave In input from MCU Master In Slave Out output for MCU Select Master/Slave SPI data input SPI data output Remark Pad Number Exposed Pad 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 VDDFUSE MFIRST CS_FUSE DVDD MOSI DVSS CS_N MISO DTST GND SCK 3 9116B–AUTO–10/09 Table 3-1. 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Pin Description (Continued) Pad Name DTST SCANMODE CS_FUSE VDDFUSE DVSS DVDD GND ATST AVDD AVSS TEMPVSS TEMP1 TEMP2 TEMPREF BIASRES PWTST POW_ENA PD_N_OUT VDDHVM VDDHVP PD_N MISO_IN MOSI_OUT SCK_OUT CS_N_OUT CLK_OUT IRQ_IN VDDHV MBAT7 DISCH6 MBAT6 Function Test-mode pin Test-mode pin Test-mode pin Test-mode pin Digital negative supply Digital positive supply input (3.3V) Ground Test-mode pin 3.3V Regulator output Analog negative supply Ground for temperature measuring Temperature measuring input 1 Temperature measuring input 2 Reference voltage for temperature measuring Internal supply current adjustment Test - mode pin Power regulator enable/disable Power down output Power regulator output to supply e.g. an external microcontroller Power regulator supply voltage Power down input Master In Slave Out input from ATA6870 above Master Out Slave In output for ATA6870 above SPI clock output for input of ATA6870 above Chip select output for input of ATA6870 above System clock output for input of ATA6870 above Interrupt input from ATA6870 above Supply voltage Battery cell sensing line Output to drive external cell-balancing transistor Battery cell sensing line Keep pin open (output) Keep pin open (output) Connected to AVDD Remark Keep pin open (output) Connected to VSSA Connected to VSSA Connected to VSSA Pad Number 4 ATA6870 [Preliminary] 9116B–AUTO–10/09 ATA6870 [Preliminary] 4. ATA6870 System Overview The ATA6870 can be stacked up to 16 times in one string. The communication with MCU is carried out on the lowest level through an SPI bus. The data on the SPI bus is transmitted to the 15 other ATA6870s using the communication interface implemented inside ATA6870. Figure 4-1. Battery Management Architecture with One Battery String ATA6870 ATA6870 ATA6870 ATA6870 MCU 5 9116B–AUTO–10/09 Figure 4-2. Battery Management Architecture with Several Battery Strings ATA6870 ATA6870 MCU OPTO ATA6870 ATA6870 MCU To Battery Master Controller 6 ATA6870 [Preliminary] 9116B–AUTO–10/09 ATA6870 [Preliminary] 5. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Unless otherwise specified all voltages to pin VSSA. Parameters Ambient temperature Junction temperature Storage temperature Battery cell voltage VVDDHV - VVMBAT7max VMBAT1 Supply voltage power regulator Operating supply voltage Supply voltage DVDD (regulator is Off) Supply voltage AVDD (regulator is Off) Test-input Reference voltage for temperature measuring (regulator is Off) Supply voltage VDDHVM (regulator is Off) Digital Ground Analog Ground Digital/Analog Ground Ground voltage for temperature measuring MBAT1 VDDHVP VDDHV DVDD AVDD VDDFUSE TEMPREF VDDHVM DVSS AVSS AVSS, DVSS TEMPVSS CLK, CS_N, SCK, MOSI, DTST, ATST, SCANMODE, MFIRST, POW_ENA, CS_FUSE, PWTST IRQ, MISO Input voltage for analog I/O pins Input voltage for digital high voltage input pins MBAT(i+1), MBAT(i) Pin Symbol TA TJ TS VMBAT(i+1) VMBAT(i) VVDDHV - VVMBAT7 VMBAT1 VVDDHVP VVDDHV VDVDD VAVDD VVDDFUSE VTEMPREF V VDDHVM VAVSS - VGND VAVSS - VGND VAVSS - VDVSS VTEMPVSS VCLK, VCS_N, VSCK, VMOSI, VDTST, VATST, VSCANMODE, VMFIRST, VPOW_ENA, VCS_FUSE, VPWTST VIRQ, VMISO Min. –40 –40 –55 –0.3 –5.5 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 Max. +85 +125 +150 +5.5 +0.3 +0.3 +33.6 +30 +5.5 +5.5 +5.5 VDD+0.3 +5.5 +0.3 +0.3 +0.3 +0.3 Unit °C °C °C V V V V V V V V V V V V V V Input voltage for logic I/O pins –0.3 VDD + 0.3 V –0.3 –0.3 VDDHV – 0.3 +5.5 VDD + 0.3 VDDHV + 0.3 V V V TEMP1, TEMP2, VTEMP1, VTEMP2, VBIASRES BIASRES MISO_IN, IRQ_IN MOSI_OUT, SCK_OUT, CS_N_OUT, CLK_OUT PD_N PD_N_OUT DISCH(i) VMISO_IN, VIRQ_IN VMOSI_OUT, VSCK_OUT, VCS_N_OUT, VCLK_OUT V PD_N V PD_N_OUT VDISCH(i) Voltage at digital high voltage output pins VDDHV – 0.3 VDDHV + 0.3 V Input: PD_N Output: PD_N_OUT Voltage at cell balancing outputs VDDHV – 5.5 –5.5 VMBAT(i) – 0.3 VDDHV + 0.3 +0.3 VMBAT(i+1) + 0.3 V V V 7 9116B–AUTO–10/09 5. Absolute Maximum Ratings (Continued) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Unless otherwise specified all voltages to pin VSSA. Parameters HBM ESD ANSI/ESD-STM5.1 JESD22-A114 AEC-Q100 (002) CDM ESD STM 5.3.1 Latch-up acc. to AECQ100-004, JESD78A 1, 12, 13, 24, 25, 36, 37, 48 LATCH-UP Pin Symbol Min. Max. Unit ±2 ESD 500 750 ±100 kV V V mA 6. Thermal Resistance Parameters Package. QFN48 7× 7 Max. thermal resistance junction-ambient(1) Max. thermal resistance junction-case Note: Rthjamax RthjCmax 20 TBD K/W K/W Symbol Value Unit 1. Package mounted on 4 large PCB (per JESD51-7) under natural convention as defined in JESD51-2. 8 ATA6870 [Preliminary] 9116B–AUTO–10/09 ATA6870 [Preliminary] 7. Circuit Description and Electrical Characteristics Unless otherwise specified all parameters in this section are valid for a supply voltage range of 6.9V < V D D H V < 30V and a battery cell voltage of V M B A T ( i + 1 ) – V M B A T ( i ) = 0V to 5V, –40°C < TA < 85°C. All values refer to pin VSSA, unless otherwise specified. 7.1 Operating Modes The ATA6870 has two operation modes. 1. Power-down Mode (PDmode) 2. Normal Mode (NORM Mode) 7.1.1 Power-down Mode In Power-down Mode all blocks of the IC are switched off. The circuit can be switched from Power-down to ON Mode or back via the PD_N input. If the pin is connected to VDDHV via an external optocoupler, for example, the circuit is in ON Mode. If several ATA6870 are stacked, the power-down signal must be only provided for the IC on the top level of the stack. The next lower IC receives this information from the PD_N_OUT output of its upper IC. The PD_N_OUT pin must be connected to either the PD_N pin of the next lower ATA6870 or to VSSA. 9 9116B–AUTO–10/09 Figure 7-1. Power-down VDDHV MBAT7 PD_N DISCH6 Cell 6: Reference ADC Cell Balancing Digital Level Shifter Standby Control PD_N_OUT VDDHVP 3.3V Voltage Regulator POW_ENA VDDHVM AVDD MBAT6 ATA6870 MBAT2 3.3V Internal Voltage Regulator DVDD BIASRES Digital Level Shifter DISCH1 MBAT1 TEMPREF Cell 1: Reference ADC Cell Balancing Logic Internal Biasing TEMP2 TEMP1 NTC NTC TEMPVSS SCANMODE Test Cell Temperature Measuring Digital Level Shifter Interchip and Microcontroller Communication Interface MISO_IN MOSI_OUT SCK_OUT CS_N_OUT CLK_OUT IRQ_IN CS_N SCK MOSI MISO IRQ CLK VDDFUSE DVSS ATST CS_FUSE VDDHV MBAT7 PD_N DISCH6 Cell 6: Reference ADC Cell Balancing Digital Level Shifter Standby Control MFIRST AVSS PWTST DTST GND PD_N_OUT VDDHVP 3.3V Voltage Regulator POW_ENA VDDHVM AVDD MBAT6 ATA6870 MBAT2 3.3V Internal Voltage Regulator DVDD BIASRES Digital Level Shifter DISCH1 MBAT1 TEMPREF Cell 1: Reference ADC Cell Balancing Logic Internal Biasing TEMP1 NTC NTC TEMPVSS Cell Temperature Measuring Digital Level Shifter TEMP2 Interchip and Microcontroller Communication Interface MISO_IN MOSI_OUT SCK_OUT CS_N_OUT CLK_OUT IRQ_IN CS_N SCK MOSI MISO IRQ CLK VDDFUSE MFIRST Test MCU SCANMODE CS_FUSE AVSS DVSS DTST 10 ATA6870 [Preliminary] 9116B–AUTO–10/09 PWTST ATST GND ATA6870 [Preliminary] Table 7-1. Electrical Characteristics Test Conditions Pin Symbol Min. Typ. Max. Unit Type* No. Parameters Maximum allowed input current in Power-down 1.1 Mode (e.g., leakage current of an optocoupler) 1.2 Input current in ON Mode 1.3 Maximum voltage (pin PD_N left open) PD_N IPD_N IPD_N VVDDHV VPD_N tVDDON 2.5 50 µA A PD_N IPD_N = 0 to 50 µA min slope PD_N 5 5 mA V A A Propagation delay time 1.4 from Power-down Mode to NORM Mode Propagation delay time 1.5 from NORM Mode to Power-down Mode 1 mA I PD_N = ------------msec DVDD 3 ms A DVDD tVDDOFF 10 ms A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 7.1.2 Normal Operating Mode (NORM Mode) The ATA6870 turns on when the PD_N signal is switched from low to high. The power supplies AVDD and DVDD as well as VDDHVM (if the input signal POW_ENA = high) are turned on. The configuration registers are set to their default values. In NORM Mode the ATA6870 can acquire analog data (voltage or temperature channels) upon request from the host microcontroller. When the host microcontroller orders an acquisition through the SPI bus, the IC starts digitizing all voltage and one temperature channel in parallel. The on-chip digital signal processor filters, in real time, the channel samples. When conversion and filtering are done, the data-ready interrupt to the host processor indicates the data availability. The MCU can now read the ADC result registers. The MCU reads the ATA6870’s status registers to check each IC and to acknowledge the interrupt. When ATA6870 is in NORM Mode, the MCU can be active or in idle mode. In order to wake-up the MCU by an interrupt, the Low Frequency Timer (LFT) can be activated in ATA6870. Interrupt is signaled with a high level on IRQ pin. The LFT is re-programmable on the fly and can be reset through SPI, but is not stoppable. Figure 7-2. ATA6870 in NORM Mode Acquisition Idle Idle ASICs in NOMode IRQ Asserted SPI ACQ Cmd Read status register Read data burst mode MCU Background task Send SPI Command Background task/Idle Interrupt Handling Background task Processing 11 9116B–AUTO–10/09 Table 7-2. Electrical Characteristics Test Conditions Pin VDDHV VDDHV Symbol VVDDHV IVDDHV Min. 6.9 Typ. Max. 30 15 Unit V mA Type* A A No. Parameters 2.1 Supply voltage 2.2 Current consumption IVDDHV (Normal Mode) Current consumption in Power-down mode 2.3 (PDmode) IVDDHV + IMBAT(i)max(1) VMBAT(i+1) – VMBAT(i) = 3.7V VDDHV 10 µA A Imbalance from battery cell to battery cell in VMBAT(i+1) – 2.4 VMBAT(i) = 3.7V Power-down Mode (PDN Mode) Note: 1. Largest input current of the cell inputs MBAT(i) MBAT(i+1) IMBAT(i+1) 10 µA A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 7.2 Interface to Battery Cells Each input line MBAT(i) and the supply lines VDDHV, AVSS can be protected by additional resistors and a filter capacitor as shown below. Figure 7-3. External Components between ATA6870 and the Battery Cells R_VDDHV R_IN VDDHV MBAT(i+1) Discharge Resistor Battery cell(i) Cell(i) DISCH(i) R_IN R_VSS MBAT(i) AVSS ATA6870 Battery cell Board MBAT(i) are high impedance input (~2 MΩ). Thus, external components can be added to protect ATA6870 chip against current spikes and overvoltage at battery cell level. 12 ATA6870 [Preliminary] 9116B–AUTO–10/09 ATA6870 [Preliminary] Table 7-3. 3.1 R_IN 3.2 R_VDDHV 3.3 R_VSS Electrical Characteristics Test Conditions Pin MBAT(i) VDDHV AVSS Symbol Min. Typ. Max. 1 50 50 Unit kΩ Ω Ω Type* D D D No. Parameters *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 7.3 Reduced Number of Battery Cells Configuration It is possible for ATA6870 to operate with a reduced number of cells: 3, 4, 5, and 6 cell operation are possible. In these cases, the cell-chip inputs corresponding to the missing cells should be connected to the upper cell potential of the module. Figure 7-4. Connection with 4 Cells only VDDHV MBAT7 PD_N PD_N_OUT VDDHVP POW_ENA VDDHVM DISCH6 MBAT6 DISCH5 MBAT5 DISCH4 MBAT4 DISCH3 MBAT3 AVDD DVDD BIASRES ATA6870 MISO_IN MOSI_OUT SCK_OUT CS_N_OUT DISCH2 MBAT2 CLK_OUT IRQ_IN CS_N DISCH1 MBAT1 SCANMODE TEMPREF TEMP2 DVSS AVSS TEMP1 TEMPVSS GND SCK MOSI MISO VDDFUSE CS_FUSE MFIRST IRQ CLK DTST Battery cell 1 (MBAT1, MBAT2) and battery cell 6 (MBAT6, MBAT7) must always be used for the lowest/highest cell. ATST 13 9116B–AUTO–10/09 7.4 ATA6870 External MCU Supply The ATA6870 provides a 3.3V power-supply for external components such as the microcontroller unit (MCU). The input pin for this supply is pin VDDHVP, and the output pin is VDDHVM. This regulator is able to supply the MCU directly from the topmost battery cell of a string. The power regulators of all stacked ATA6870 are therefore put in serial configuration to avoid imbalance.The regulator can be disabled with the digital input pin POW_ENA. Table 7-4. Pin POW_ENA Truth Table Symbol Value Low High Function Voltage regulator disabled Voltage regulator enabled VPOW_ENA Logic levels: Low = VDVSS, High = VDVDD 14 ATA6870 [Preliminary] 9116B–AUTO–10/09 ATA6870 [Preliminary] Figure 7-5. MCU Supply with the Internal Power Supply VDDHV MBAT7 PD_N Cell 6: Reference ADC Cell Balancing DISCH6 MBAT6 Digital Level Shifter Standby Control PD_N_OUT VDDHVP 3.3V Voltage Regulator POW_ENA VDDHVM AVDD ATA6870 MBAT2 3.3V Internal Voltage Regulator DVDD BIASRES Digital Level Shifter DISCH1 MBAT1 TEMPREF TEMP2 Cell 1: Reference ADC Cell Balancing Logic Internal Biasing TEMP1 TEMPVSS SCANMODE Test Cell Temperature Measuring Digital Level Shifter Interchip and Microcontroller Communication Interface MISO_IN MOSI_OUT SCK_OUT CS_N_OUT CLK_OUT IRQ_IN CS_N SCK MOSI MISO IRQ CLK VDDFUSE AVSS DVSS CS_FUSE MFIRST PWTST DTST ATST GND + VDDHV MBAT7 PD_N Cell 6: Reference ADC Cell Balancing DISCH6 MBAT6 Digital Level Shifter Standby Control PD_N_OUT VDDHVP 3.3V Voltage Regulator POW_ENA VDDHVM AVDD ATA6870 MBAT2 3.3V Internal Voltage Regulator DVDD BIASRES Digital Level Shifter DISCH2 MBAT1 TEMPREF Cell 1: Reference ADC Cell Balancing Logic Internal Biasing + Cell Temperature Measuring TEMP1 TEMPVSS Digital Level Shifter TEMP2 Interchip and Microcontroller Communication Interface MISO_IN MOSI_OUT SCK_OUT CS_N_OUT CLK_OUT IRQ_IN CS_N SCK MOSI MISO IRQ CLK Test MCU SCANMODE CS_FUSE GND DVSS DTST VDDFUSE MFIRST AVSS PWTST ATST 15 9116B–AUTO–10/09 Table 7-5. Electrical Characteristics Test Conditions Pin VDDHVP VDDHVM VDDHVM (1) No. Parameters 4.1 Supply voltage 4.2 Output voltage 4.3 DC output current 4.4 Peak output current 4.5 Capacitor load (2) Symbol VVDDHVP VVDDHVM IVDDHVM IVDDHVM Min. 6.9 3.1 Typ. 3.3 Max. 33.3 3.5 20 50 Unit V V mA mA µF nF V Type* A A A A D D A A C A VDDHVM VDDHVM VDDHVM POW_ENA POW_ENA POW_ENA VPOW_ENA = 0V to VDVDD POW_ENA 30 200 VPOW_ENA VPOW_ENA VPOW_ENA IPOW_ENA 0.05 × VDVDD –1 0.7 × VDVDD 33 220 4.6 Capacitor load(2) 4.7 High level input voltage 4.8 Low level input voltage 4.9 Hysteresis 4.10 Input current 0.3 × VDVDD V V +1 µA *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. Maximum current the power regulator can provide, time limited by thermal consideration only 2. These capacitors are mandatory 16 ATA6870 [Preliminary] 9116B–AUTO–10/09 ATA6870 [Preliminary] Figure 7-6. MCU Supply with an External Power Supply VDDHV MBAT7 PD_N Cell 6: Reference ADC Cell Balancing DISCH6 MBAT6 Digital Level Shifter Standby Control PD_N_OUT VDDHVP 3.3V Voltage Regulator POW_ENA VDDHVM AVDD ATA6870 MBAT2 3.3V Internal Voltage Regulator DVDD BIASRES Digital Level Shifter DISCH2 MBAT1 TEMPREF TEMP2 Cell 1: Reference ADC Cell Balancing Logic Internal Biasing TEMP1 TEMPVSS SCANMODE Test Cell Temperature Measuring Digital Level Shifter Interchip and Microcontroller Communication Interface MISO_IN MOSI_OUT SCK_OUT CS_N_OUT CLK_OUT IRQ_IN CS_N SCK MOSI MISO IRQ CLK VDDFUSE DVSS CS_FUSE VDDHV MBAT7 PD_N Cell 6: Reference ADC Cell Balancing DISCH6 MBAT6 Digital Level Shifter Standby Control PD_N_OUT VDDHVP 3.3V Voltage Regulator MFIRST PWTST AVSS DTST ATST GND POW_ENA VDDHVM ATA6870 MBAT2 AVDD 3.3V Internal Voltage Regulator DVDD BIASRES Digital Level Shifter DISCH2 MBAT1 TEMPREF TEMP2 Cell 1: Reference ADC Cell Balancing Logic Internal Biasing TEMP1 TEMPVSS Test Cell Temperature Measuring Digital Level Shifter Interchip and Microcontroller Communication Interface MISO_IN MOSI_OUT SCK_OUT CS_N_OUT CLK_OUT IRQ_IN CS_N SCK MOSI MISO IRQ CLK MCU SCANMODE CS_FUSE VDDFUSE DVSS DTST ATST GND MFIRST AVSS PWTST 17 9116B–AUTO–10/09 7.5 7.5.1 Analog Blocks Battery Voltage Measuring Figure 7-7. Block Diagram Battery Voltage Measurement ATA6870 1.666V Reference gain MBAT(i+1) 12 bits incremental ADC External DVDD Cell i MBAT(i) High voltage level shifter (digital) Bitstream CLK DISCH(i) MUX Disch(i) DVSS The battery voltage measurement block contains • a 3-input multiplexer • a voltage reference, • a 12-bit ADC • the upper part of digital voltage level shifters 7.5.1.1 Input Multiplexer The multiplexer has 3 inputs. Each of the functions are described in the table below: Table 7-6. Inputs of the Multiplexer Input V(MBAT(i+1), MBAT(i)) V(VREF(i)) V(MBAT(i), MBAT(i)) Function Input voltage measurement Gain error acquisition of ADC Offset error acquisition of ADC The multiplexer inputs are controlled by SPI. 18 ATA6870 [Preliminary] 9116B–AUTO–10/09 ATA6870 [Preliminary] 7.5.1.2 12 Bits Incremental ADC The purpose of this cell is to convert an analog input into a 12-bit digital word. Table 7-7. Electrical Characteristics Test Conditions Maximum input noise 0.5 mVrms Pin MBAT(i+1), MBAT(i) Symbol Min. –10 Typ. Max. +10 Unit mV Type* A No. Parameters 5.1 Accuracy of voltage channel(1) Accuracy of voltage channel(1)(2) 5.2 Maximum input noise MBAT(i+1), 0.5 mVrms MBAT(i) VMBAT(i+1) – VMBAT(i) = 3.6V MBAT(i+1), MBAT(i) VMBAT(i+1), VMBAT(i) VLSB VRef MBAT(i+1), MBAT(i) MBAT(i+1), MBAT(i) CLK SCK tconv = (2 12 –7 +7 mV A 5.3 Input voltage range 5.4 Input resolution (1 LSB) 5.5 Reference voltage 5.6 Offset voltage 5.7 Gain voltage 5.8 System clock 5.9 SPI interface clock 5.10 Conversion rate (3) 0 1.5 1.667 410 655 450 500 8.194 50 5 V mV V LSB LSB/V A A D A A D D D D VMBAT(i+1), VMBAT(i) VMBAT(i+1), VMBAT(i) fCLK fSCK tconv 550 kHz ms Hz 0.5 × fCLK + 1) / fCLK MBAT(i+1), MBAT(i) 5.11 Input bandwidth fBW *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. The accuracy of the voltage channels is guaranteed with no external resistor in the MBAT(i), MBAT(i+1) lines. 2. Reduced temperature range (–20°C to + 65°C) 3. Conversion rate without readout times of SPI Figure 7-8. ADC output 3686D = 0.9D*212 Slope = (1502D - 410D)/1.667 = 655DLSB/V ADC (VREF) 1502D 410D = 0.1*212 0 0 VREF 5 Input Voltage (MBATi+1, MBATi) 19 9116B–AUTO–10/09 In order to correct offset and gain, MBATi and VREF are measured: adc ( VREF i ) – adc ( MBAT i ) Slope = ---------------------------------------------------------------------v ( VREFi ) (1) Offset = adc(MBATi) adc(MBATi+1) = Slope × v(MBATi+1, MBATi) + Offset adc ( MBATi+1 ) – adc ( MBAT i ) v ( MBAT i+1 MBAT i ) = ---------------------------------------------------------------------------- × v ( VREF i ) adc ( VREF i ) – adc ( MBATi ) (2) Table 7-8. Ideal ADC ADC Input 0V Ideal ADC Output Code 410 1502 1851 2048 2375 2834 3686 0.9 × 212 0.5 × 212 Comments 0.1 × 212 VREF = 1.667V 2.2V 2.5V 3V 3.7V 5V adc ( MBAT i+1 ) – 0.1 × 2 v ( MBAT i+1 MBAT i ) = 1.667 × ------------------------------------------------------------------12 1502 – 0.1 × 2 12 (3) v(MBATi+1, MBATi) = 1.52656 × 10–3 × (adc(MBATi+1) – 410) Using this equation, the round error is less than one mV. 5 LSB = ------------------------------------------------------ = 1.5 mV 12 12 0.9 × 2 – 0.1 × 2 Compensation with 1st Order Correction As the MCU cannot perform a division operation, 1 ---------------------------------------------------------------------- is approximated in a first order polynomial equation: adc ( VREF i ) – adc ( MBAT i ) [ adc ( VREF i ) – 1502 ] – [ adc ( MBAT i ) – 410 ] 1 --------------------------------- – ------------------------------------------------------------------------------------------------------------------2 ( 1502 – 410 ) ( 1502 – 410 ) (4) 20 ATA6870 [Preliminary] 9116B–AUTO–10/09 ATA6870 [Preliminary] With equation (3) and (4) we get the formula for calculating the analog input voltage (without division): [ adc ( VREF i ) – 1502 ] – [ adc ( MBAT i ) – 410 ] 1 v ( MBAT i+1 , MBAT i ) = 1.667 × --------------------------------- – ------------------------------------------------------------------------------------------------------------------- × [ adc ( MBATi+1 ) – adc ( MBAT i ) ] 2 ( 1502 – 410 ) ( 1502 – 410 ) 7.5.1.3 Acquisition Time and Clocking The acquisition time depends on the number of ATA6870s to be addressed. Table 7-9. Electrical Characteristics SCK Frequency (kHz) 250 250 250 250 250 125 125 125 125 62.5 62.5 62.5 62.5 62.5 62.5 62.5 CLK Frequency (kHz) 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 Conversion Time (ms) 8.2 8.2 8.2 8.2 8.2 8.2 8.2 8.2 8.2 8.2 8.2 8.2 8.2 8.2 8.2 8.2 Total Acquisition Duration (ms)(1) 9.5 10.2 10.8 11.5 12.2 17.0 18.4 19.7 21.1 36.1 38.8 41.5 44.2 46.8 49.5 52.2 Number of ATA6870 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Notes: 1. The total acquisition time takes the following into account: - ADC conversion - Reading of voltage values in burst mode for all ATA6870 devices, - Reading of temperature values for all ATA6870 devices (only one temperature input is read). SPI clock (pin SCK) must a maximum of half the frequency of the system clock CLK. 21 9116B–AUTO–10/09 7.5.2 Battery Cell Discharge Each battery cell can be discharged with an external resistor and an NMOS transistor. Figure 7-9. External Circuit for Cell Balancing R_VDDHV R_IN VDDHV MBAT(i+1) Discharge Resistor Battery cell(i) Cell(i) DISCH(i) R_IN R_VSS MBAT(i) AVSS ATA6870 Battery cell Board The pin DISCH(i) (Discharge for battery cell i) is intended to switch on the external discharge resistor in parallel to the battery cell to bypass charge current for cell balancing reasons. The pin DISCH(i) is a digital output: No discharge: VDISCH(i) = VMBAT(i) Discharge: VDISCH(i) = VMBAT(i+1) Table 7-10. Electrical Characteristics Test Conditions Pin MBAT(i) IDISCH(i) = –10 µA, MBAT(i+1) – MBAT(i) = 1.5V to 5V IDISCH(i) = –1 mA MBAT(i+1) – MBAT(i) = 3V to 5V Symbol MBAT(i+1) – MBAT(i) VDISCH(i) – VMBAT(i) VDISCH(i) – VMBAT(i) Min. 1.5 VMBAT(i+1) – 50 mV VMBAT(i+1) – 0.6V 60 140 Typ. Max. 5 Unit V Type* A No. Parameters 6.1 Operating voltage range 6.2 High-level output voltage DISCH(i) V A 6.3 High-level output voltage 6.4 Pull-down resistor(1) DISCH(i) DISCH(i)MBAT(i) V kΩ A A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Integrated pull-down resistor between pins DISCH(i) and MBAT(i) 22 ATA6870 [Preliminary] 9116B–AUTO–10/09 ATA6870 [Preliminary] 7.5.3 Temperature Channel The temperature sensors are based on a resistor divider using a standard resistor and an NTC resistor. This resistor divider is connected to the reference of the ADC for temperature measuring. As the ADC is sharing same reference value, the output of temperature measurement with ADC is ratio metric. Figure 7-10. Battery Cell Temperature Measurement AVDD TEMPREF 1.2V Reference RES_REF2 RES_REF1 TEMP1 12 bits Incremental ADC OUT TEMP2 RES_NTC2 RES_NTC1 Operation Register TEMPVSS During one measuring cycle only one temperature input can be measured by the ADC. The channel can be selected in the Operation Register (0x02) by the TempMode bit (bit 3). The ADC output is equal to: RES_NTC(1) 8- 8out = 2048 × ⎛ 1 + -------------------------------------------------------------------------------- × ----- – ----- ⎞ ⎝ (RES_NTC(1) + RES_REF(1)) 15 10⎠ Table 7-11. Electrical Characteristics Test Conditions Pin TEMPREF TEMPREF TEMP1 TEMP2 Symbol VTEMPREF – VTEMPVSS ITEMPREF VTEMP1 VTEMP2 RES_REF RES_NTC V(TEMPi, TEMPVSS) = 0.5 × V(TEMPREF, TEMPVSS) V(TEMPi, TEMPVSS) =0 931D 385D 1477D 956D 410D 1502D 0 0 1.2 Min. 1.1 Typ. 1.2 Max. 1.3 2 VTEMPREF VTEMPREF 22 800 981D 435D 1527D Unit V mA V V kΩ kΩ Type* A A A A D D A No. Parameters 7.1 Reference voltage 7.2 Reference voltage output current 7.3 Input voltage range 7.4 Input voltage range 7.5 Resistor RES_REF 7.6 Resistor RES_NTC Code output for 7.7 value(RES_NTCx) = value (RES_REFx) 7.8 7.9 Code output for value(RES_NTC) = 0 A A Code output for V(TEMPi, TEMPVSS) value(RES_NTC) = infinite = V(TEMPREF) *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 23 9116B–AUTO–10/09 7.5.4 Internal Voltage Regulator The regulator output is pin AVDD. The pins AVDD and DVDD have to be connected together. An external filtering capacitor (10 nF recommended) is used to filter and stabilize the function. The regulator output can be used to supply outside functions at the price of power supply imbalance between battery cells. Table 7-12. Electrical Characteristics Test Conditions Pin VDDHV AVDD AVDD Cload Symbol VVDDHV VAVDD IAVDD Min. 6.9 3.1 0 9 10 3.3 Typ. Max. 30 3.5 5 Unit V V mA nF Type* A A A D No. Parameters 8.1 Supply voltage range 8.2 Regulated output voltage 8.3 Output current 8.4 Cload (load capacitor) *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 7.5.5 Central Biasing This block generates a precise bias current to supply internal blocks of the IC. Connection of any external loads to this pin is not allowed. Table 7-13. Electrical Characteristics Test Conditions Pin BIASRES Symbol VBIASRES RRefbias ΔRRefbias BIASRES CExternal –1 Min. Typ. 1.2 121 +1 50 Max. Unit V kΩ % pF Type* A D D D No. Parameters 9.1 Biasing voltage 9.2 External resistor 9.3 Tolerance Maximum external parasitic 9.4 capacitor *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Figure 7-11. Internal Bias Current Generation IBIAS Bandgap 1.2V BIASRES RREFBIAS 121 kΩ 24 ATA6870 [Preliminary] 9116B–AUTO–10/09 ATA6870 [Preliminary] 7.5.6 RC Oscillator Internal RC Oscillator Frequency Test Conditions Pin Symbol fOsc Min. 45 Typ. 50 Max. 55 Unit kHz Type* A Table 7-14. No. Parameters 10.1 Oscillator frequency *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 7.5.7 Power On Reset The Power On Reset is used to initialize the digital part at power-up. The Power On Reset circuit is functional when the voltage at pin DVDD is larger than VPOROP. There are two reset sources: System “hard reset” System hard reset occurs when the voltage at pin DVVD goes below the Power On Reset threshold. ATA6870 registers are set to their initial values. After t = tRESET, the MCU can access the ATA6870. Figure 7-12. Power On Reset VPOROFF VPORON VPOROP VDVDD VPOR Table 7-15. Electrical Characteristics Test Conditions Pin DVDD DVDD DVDD Symbol VPOROP VPOROFF VPOROFF – VPORON tRESET 1.5 0.03 800 Min. Typ. Max. 0.8 2.5 Unit V V V µs Type* A A C A No. Parameters 11.1 Power On Reset Functional 11.2 Power On Reset Off 11.3 Power On Reset Hysteresis 11.4 Power On Reset Time *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 25 9116B–AUTO–10/09 7.6 7.6.1 Digital Part General Features The digital parts of the ATA6870 includes the following blocks: • 4-Wire-SPI Full Duplex Communication with External Host MCU • SPI System Protocol Management (Frames Decoding) and Configuration Registers Bank • Interrupt to MCU Management • Operations Decoding (Voltage and/or Temperature Acquisition) and Analog Part Control • Low Frequency Timer (50 kHz) for Wake-up Management 7.6.2 Host Interface Figure 7-13. Host Interface VDDMicrocontroller Unit CS_N SCK VDVDD SPI Master MCU MOSI MISO IRQ SPI MFIRST SPI Slave ATA6870 (1) The communication between ATA6870 (1) and its host MCU, as well as ATA6870 (n) and ATA6870(n-1) is based on a 4 wire serial/parallel SPI interface (CS_N, SCK, MISO, MOSI) and an interrupt line (IRQ). The SPI interface allows register read and write operations. The interrupt line indicates events that require host intervention. ATA6870(n)’s 4 wire-SPI bus inputs (CS_N, SCK, MOSI) are up-shifted through level shifters. They are internally connected to the outputs CS_N_OUT, SCK_OUT, MOSI_OUT and connected to ATA6870(n+1) (CS_N, SCK, MOSI). ATA6870(n)’s 4 wire-SPI bus output (MISO) and ATA6870(n)’s interrupt (IRQ) are down-shifted through level shifters and connected to ATA6870(n-1) (MOSI_IN, IRQ_IN) or host MCU (n = 1). 26 ATA6870 [Preliminary] 9116B–AUTO–10/09 ATA6870 [Preliminary] 7.6.3 Interrupt In NORM Mode (Normal Mode), the reasons for an interrupt request are: • The availability of measured data (data ready) When a voltage measurement is completed, the dataRdy flag is set in the status register. The ATA6870 cannot decode any new incoming operation until the dataRdy flag is released. • The low frequency timer (LFT) elapses (wakeup) The wakeup flag is set in the status register when the LFT elapses. The LFT is controlled via the SPI interface. • A transmission error is flagged during the last SPI transaction (the commError bit is set in the status register). • If an undervoltage condition occurs. The undervoltage function is controllable via SPI interface. A mask bit in the irqMask register corresponds to each interrupt source. The MCU must read the ATA6870 status register before the interrupt is cleared. With each SPI access a 16-bit IRQ state is sent via MISO to the MCU with the interrupt state of all stacked ATA6870 (see Section 7.6.4.1 “SPI Transaction Fields” on page 27). In PDmode (Power Down), if the digital control part and MCU are not supplied, neither SPI command nor interrupt are transmitted over the interface. 7.6.4 SPI Interface The full duplex SPI interface block allows communication with the host MCU using four wires (MISO, MOSI, SCK and CS_N). SPI transactions are based on a byte-access MSB first protocol. 7.6.4.1 SPI Transaction Fields Most of the time, the SPI frame is defined by 4 distinct fields: IDENTIFICATION (2 bytes): 16-bit chip identification (MOSI), in parallel 16-bit IRQ state (MISO) CONTROL (1 byte): 7-bit register address + 1-bit read/write information (MOSI) DATA (k byte): k*8 bits data (MOSI or MISO depending on the access direction) CHKSUM (1 byte): 8 bits if the Chksum_ena bit is set in the Ctrl register (register 0x01, bit 4) 27 9116B–AUTO–10/09 Figure 7-14. SPI Transaction Fields Organization byte1 byte2 byte3 byte4 byte5 to n-1 byte n CS_N MOSI ChipID1 ChipID0 CONTROL DATA .... CHKSUM (1) MISO IRQID1 IRQID0 SPI write access CS_N (1) MOSI ChipID1 ChipID0 CONTROL CHKSUM MISO IRQID1 IRQID0 SPI read access DATA .... Note: 1. Only send if chksum_ena bit set to 1 in the Ctrl register 7.6.4.2 Identification Field ATA6870 Chip Identification The two chip identification bytes are sent over MOSI to the ATA6870(n) in the chain. The ATA6870(n) checks the LSB. When LSB=1, the information is for this device. The SPI address will be decoded and the information processed. Independent from this the identification bytes are shifted by one bit to the right and transferred to the next ATA6870(n) in the chain. The 2 identification bytes allows the identification of up to 16 ATA6870s. . 28 ATA6870 [Preliminary] 9116B–AUTO–10/09 ATA6870 [Preliminary] Figure 7-15. Identification Field: Chip-ID Reception IDENTIFICATION FIELD CS_N ATA6870 (1) MOSI_IN ATA6870 (2) MOSI_IN ATA6870 (3) MOSI_IN ATA6870 (4) MOSI_IN ATA6870 (n>4) MOSI_IN 0x00 0x00 0x00 0x00 0x00 0x08 0x04 0x02 0x01 0x00 CONTROL CONTROL CONTROL CONTROL CONTROL DATA DATA DATA DATA DATA ATA6870 (1->3) identification field has lsb = 0 => device is not affected. ATA6870 (4) identification Shift it ”on the fly” once field has lsb = 1 => decode to the right SPI access. Shift it ”on the fly” once to the right ATA6870 (>4) identification field has lsb = 0 => device is not affected. Shift it ”on the fly” once to the right 7.6.4.3 ATA6870 IRQ Identification Figure 7-16. IRQ Propagation Scheme IRQ_IN irq_int ATA6870 (n) IRQ IRQ_IN irq_int ATA6870 (n-1) IRQ IRQ_IN irq_int ATA6870 (1) IRQ MCU 29 9116B–AUTO–10/09 ATA6870(n) IRQ output is connected to ATA6870(n-1) IRQ_IN input. ATA6870(n-1) IRQ output is a logic OR between IRQ_IN and its internal irq_int signal. ATA6870(1) IRQ output is connected to MCU. Figure 7-17. Identification Field: Interrupt State Emission CS_N ATA6870 (1) MISO ATA6870 (2) MISO ATA6870 (3) MISO Master SPI receives identification word = 0x2000 = 213 = 2m. This means ATA6870 number (16-m = 16-13) = 3 has IRQ pending. 0x20 0x40 0x80 0x00 0x00 0x00 ATA6870 (16) MISO 0x00 0x00 ATA6870 (3) IRQ is set. => ATA6870 (3) sets the MSB of the first byte to be shifted out. Others bits are those coming from upper ATA6870, shifted once to the right. Others ATA6870s assert the MSB of the first byte to 0. Others bits are those coming from upper ATA6870, shifted once to the right. Note: n = IC number m = bit number m = n -1 1 < = n < = 16 0 < = m < = 15 With each SPI access, a 16- bit IRQ state is send via MISO synchronous to the identification field to the MCU with the interrupt state of all stacked ATA6870. The MCU, interrupted by an ATA6870, has to send the identification field to check the IRQ levels (in that case the checksum is not considered). It is also possible to continue the transaction with CONTROL and DATA field. The MCU decodes the identification field shifted in MISO input. When bit m is set, ATA6870(16-m) is requesting interrupt. Figure 7-18. Identification Field CS_N SCK MOSI M(16) M(15) M(14) M(13) M(12) M(11) M(10) M(9) M(8) M(7) M(6) M(5) M(4) M(3) M(2) M(1) MISO I(1) I(2) I(3) I(4) I(5) I(6) I(7) I(8) I(9) I(10) I(11) I(12) I(13) I(14) I(15) I(16) 30 ATA6870 [Preliminary] 9116B–AUTO–10/09 ATA6870 [Preliminary] 7.6.4.4 CONTROL Field The CONTROL field defines the register to access and the direction (read/write). The size of the data (8, 16, or 112 bits) is defined by the address value in the CONTROL field. Table 7-16. Control Field Bit7 A6 Bit6 A5 Bit5 A4 Bit4 A3 Bit3 A2 Bit2 A1 Bit1 A0 Bit0 W/Rd CONTROL Field 7.6.4.5 DATA Field The DATA field can be composed of 1, 2, or 14 bytes depending on the accessed register. Irrespective of the data direction, a byte is always transmitted with MSB first; a multi-byte word is transmitted with MSByte first. Figure 7-19. CONTROL and DATA Fields - 8-bits Register Write CS_N SCK MOSI A(6) A(5) A(4) A(3) A(2) A(1) A(0) 1 D(7) D(6) D(5) D(4) D(3) D(2) D(1) D(0) MISO Data not relevant Data not relevant Figure 7-20. CONTROL and DATA Fields - 8-bits Register Read CS_N SCK MOSI A(6) A(5) A(4) A(3) A(2) A(1) A(0) 0 Data not relevant MISO Data not relevant D(7) D(6) D(5) D(4) D(3) D(2) D(1) D(0) Figure 7-21. CONTROL and DATA Fields - 16-bits Register Write CS_N SCK MOSI A(6) A(5) A(4) A(3) A(2) A(1) A(0) 1 D(15) D(14) D(13) D(12) D(11) D(10) D(9) D(8) D(7) D(6) D(5) D(4) D(3) D(2) D(1) D(0) MISO Data not relevant Data not relevant Data not relevant 31 9116B–AUTO–10/09 Figure 7-22. CONTROL and DATA Fields - 16-bits Register Read CS_N SCK MOSI A(6) A(5) A(4) A(3) A(2) A(1) A(0) 0 MISO Data not relevant D(15) D(14) D(13) D(12) D(11) D(10) D(9) D(8) D(7) D(6) D(5) D(4) D(3) D(2) D(1) D(0) In order to retrieve results from all channels in one ATA6870 without having to request for each channel, an SPI 112-bit read-only "burst access" (dataRd16Burst register; address = 0x7F) is implemented. When requested, the ATA6870 outputs its 6 voltage channels V6 to V1 and one of the two temperature channels T2 and T1 in sequence on the SPI bus. The diagrams below show the CONTROL and DATA fields of such an access. Figure 7-23. CONTROL and DATA Fields - 112-bits Register Read CS_N SCK MOSI 1 1 1 1 1 1 1 0 MISO Data not relevant 0 0 0 0 D(11) D(10) D(9) D(8) D(7) D(6) D(5) D(4) D(3) D(2) D(1) D(0) Channel V6 CS_N SCK MOSI MISO 0 0 0 0 D(11) D(10) D(9) D(8) D(7) D(6) D(5) D(4) D(3) D(2) D(1) D(0) Channel V1 CS_N SCK MOSI MISO 0 0 0 0 D(11) D(10) D(9) D(8) D(7) D(6) D(5) D(4) D(3) D(2) D(1) D(0) Channel temperature T1 or T2 32 ATA6870 [Preliminary] 9116B–AUTO–10/09 ATA6870 [Preliminary] One ATA6870 frame corresponds to the set of results obtained in one ATA6870. An ATA6870 frame is formatted as follows: Figure 7-24. SPI Access to dataRd16burst Register 0x7F Voltage channels 16 bit ADC6 16 bit ADC5 16 bit ADC4 16 bit ADC3 16 bit ADC2 16 bit ADC1 Temp channel 16 bit ADCT Padding: 0x00 msb 12-bit ADC data lsb When reading data of chained ATA6870, data is transferred as follow: Figure 7-25. Example with two ATA6870 in a Chain CS_N SCK MOSI MISO SPI Clock Rd Reg command chip1 SPI Clock Rd Reg command chip2 ATA6870 #1 Frame ATA6870 #2 Frame 7.6.4.6 Communication Error Correct communication can be verified using various functions of the ATA6870. For internal synchronization, it is mandatory to keep CLK running during any SPI access; CLK must be set on 4 clock cycles (at least) before SPI access starts, and must be kept on 4 clock cycles (at least) after SPI access ends up. Keeping at least 4 CLK clock cycles between two consecutive SPI accesses is mandatory. If this is not the case, the ATA6870s will detect an error in communication. The CommError bit will be set in the Status Register 0x06). Figure 7-26. SPI Access and CLK Activity CLK OFF 4 clk_ticks SPI ACCESS CLK ON 4 clk_ticks SPI ACCESS 4 clk ticks CLK_OFF The ATA6870 verifies that complete bytes (8 bits long) are always transmitted. A transition starts when CS_N goes to low and it ends when CS_N goes to high. The number of clock cycles (signal CLK) is monitored during the transition. This number of clock cycles has to be modulo 8. If the CS_N length is not modulo 8 clock cycles, the bit CommError is set in the Status register. This will cause an interrupt to the MCU if the CommError is not masked by the commErrorMsk bit in the IrqMask register. 33 9116B–AUTO–10/09 7.6.4.7 CHKSUM Field The ATA6870 provides the possibility of verifying the transmitted data using a checksum. Setting chksum_ena bit to 1 in the Ctrl register (default = 0) activates the checksum feature. The chksum field is an 8-bit checksum computed from the proceeding data (control and data fields, byte 3 to byte n-1). It is based on the polynomial x8+x2+x1+1. The way it is computed is depicted below: Figure 7-27. LFSR-based Checksum Computation F0i serial bitstream MSB first z-1 F1i z-1 F2i z-1 F3i z-1 F4i z-1 F5i z-1 F6i F6o z-1 The checksum is calculated from the CONTROL field and DATA field by a polynomial division. The DATA field can consist of 1 byte up to 14 bytes (112-bit read-only “burst access”). The IDENTIFICATION field (2 bytes) is not used to generate the checksum. The checksum is always sent by the microcontroller, independent of read write mode. The checksum is in the LFSR (Linear Feedback Shift Register) when the complete bitstream (the whole fields of the transaction) followed by 0x00 have been shifted in the LFSR. The checksum verification on the complete data transmission was OK when the complete bitstream followed by the checksum have been shifted in the LFSR, and the content of the LFSR is 0x00. If this is not the case, the receiving ATA6870 will set the chkError bit in the status register. This will cause an interrupt to the MCU if the chkError is not masked by the chkErrorMsk bit in the IrqMask register. See the example below. The checksum is serially computed from the 8-bit value 0x57. So the bitstream 0x5700 is shifted in the LFSR. The resulting checksum is [f6o, f6i, f5i … f0i] at the last shift in cycle: Table 7-17. checksum = [f6o, f6i, ... f0i] = 0xA2 Input X 0 1 0 1 0 1 1 1 0 0 0 0 f01 0 0 1 0 1 0 1 1 1 0 1 0 1 f1i 0 0 0 1 0 1 0 1 1 1 1 1 1 f2i 0 0 0 0 1 0 1 0 1 1 0 1 0 f3i 0 0 0 0 0 1 0 1 0 1 1 0 1 f4i 0 0 0 0 0 0 1 0 1 0 1 1 0 f5i 0 0 0 0 0 0 0 1 0 1 0 1 1 f6i 0 0 0 0 0 0 0 0 1 0 1 0 1 f6o 0 0 0 0 0 0 0 0 0 1 0 1 0 5D 7D 0D 34 ATA6870 [Preliminary] 9116B–AUTO–10/09 ATA6870 [Preliminary] Table 7-17. checksum = [f6o, f6i, ... f0i] = 0xA2 (Continued) Input X 0 0D 0 0 0 f01 0 0 1 1 0 f1i 0 1 1 0 1 0x2 f2i 0 1 0 0 0 f3i 0 0 1 0 0 f4i 0 1 0 1 0 f5i 0 0 1 0 1 0xA f6i 0 1 0 1 0 f6o 0 1 1 0 1 During an SPI write access, the checksum is computed by the MCU and sent MSB first in the CHKSUM field. For an SPI read access, the checksum is computed by the ATA6870 and is checked by the MCU. During CHKSUM, MCU has to send 0x00 on MOSI, and must check that its own LFSR equals 0x00 at the end of CHKSUM field. 7.6.4.8 Device Position For the ATA6870 (1), this is the device on the lowest level, the SPI has to work as a standard logic CMOS interface to the MCU. The SPI’s between stacked ATA6870 have to work as level-shifters based on current sources. These different physical interfaces can be selected by the Pin MFIRST. Table 7-18. Device Position Configuration ATA6870 (2) to ATA6870 (n) ATA6870 (1) 0 1 MFIRST Table 7-19. Electrical Characteristics Test Conditions Pin MFIRST MFIRST MFIRST VMFIRST = 0V to VDVDD MFIRST Symbol MFIRST MFIRST MFIRST MFIRST 0.05 × DVDD –1 +1 Min. 0.7 × DVDD 0.3 × DVDD Typ. Max. Unit V V V µA Type* A A C A No. Parameters 12.1 High level input voltage 12.2 Low level input voltage 12.3 Hysteresis 12.4 Input current *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 35 9116B–AUTO–10/09 7.6.5 7.6.5.1 Digital Inputs and Outputs Digital Output Characteristics Digital Output Characteristics (MISO, IRQ) If the ATA6870 is configured as first IC (master) in a string (MFIRST = 1), these pins are configured as an open drain output. If the ATA6870 is configured to be a stacked IC (MFIRST = 0), the output signals MISO and IRQ coming from the upper IC need to be transferred to the MISO and IRQ outputs of the master in the string via the MISO_IN and IRQ_IN inputs. In this case the MISO and IRQ outputs act as level shifters based on current sources. Table 7-20. Electrical Characteristics Test Conditions IOUT = +5 mA MFIRST = 1 ±0.3V, MFIRST = 0 ±0.3V, MFIRST = 0 Pin MISO, IRQ MISO, IRQ MISO, IRQ Symbol VMISO, VIRQ IMISO, IIRQ IMISO, IIRQ –13 –65 Min. Typ. Max. 0.2 × VDD –8 –40 Unit V µA µA Type* A A A No. Parameters 13.1 Low level output voltage 13.2 Low level output current 13.3 High level output current *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Digital Output Characteristics (MOSI_OUT, SCK_OUT, CS_N_OUT, CLK_OUT) These outputs act as level shifters based on current sources. They transfer the input signals MOSI_OUT, SCK_OUT, CS_N_OUT, CLK_OUT to the next IC above. If the ATA6870 is the IC on the top level of a string, these outputs must be connected to VDDHV. Table 7-21. Electrical Characteristics Test Conditions VDDHV + 1V to VDDHV + 2V VDDHV + 1V to VDDHV + 2V Pin (1) No. Parameters 14.1 Low level output current 14.2 High level output current Symbol V(1) V(1) Min. 25 –1 Typ. Max. 55 +1 Unit µA µA Type* A A (1) *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. MOSI_OUT, SCK_OUT, CS_N_OUT, CLK_OUT 36 ATA6870 [Preliminary] 9116B–AUTO–10/09 ATA6870 [Preliminary] 7.6.5.2 Digital Input Characteristics Digital Input Characteristics (MISO_IN, IRQ_IN) Table 7-22. Electrical Characteristics Test Conditions (VDDHV + 1.4V) ±0.3V (VDDHV + 1.4V) ±0.3V Pin MISO_IN, IRQ_IN MISO_IN, IRQ_IN Symbol IMISO_IN IIRQ_IN IMISO_IN IIRQ_IN Min. 13 40 Typ. Max. Unit µA µA Type* A A No. Parameters 15.1 Low level input current 15.2 High level input current *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Digital Input Characteristics (CS_N, SCK, MOSI, CLK) Table 7-23. Electrical Characteristics Test Conditions MFIRST = 1 MFIRST = 1 MFIRST = 1 MFIRST = 1 MFIRST = 1 MFIRST = 0, V(1) = 1V to 2V MFIRST = 0 V(1) = 1V to 2V (1) No. Parameters 16.1 High level input voltage 16.2 Low level input voltage 16.3 Hysteresis 16.4 High level input current 16.5 Low level input current 16.6 Low level input current 16.7 High level input current Pin (1) Symbol V(1) V(1) V(1) I(1) I(1) I(1) I(1) Min. 0.7 × DVDD Typ. Max. DVDD 0.3 × DVDD Unit V V V Type* A A C A A A A (1) (1) 0.1 × DVDD 50 –130 –55 –1 100 –70 –35 +1 µA µA µA µA (1) *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. CS_N, SCK, MOSI, CLK Table 7-24. Propagation Delay Timing Test Conditions Rpull-up = 5.1 kΩ Load capacitor max. = 15 pF MFIRST = 0, 1 > 10% input to > 90% output Rpull-up = 5.1 kΩ Load capacitor max. = 15 pF MFIRST = 0, 1 > 10% input to > 90% output Pin (1) No. Parameters 17.1 Propagation delay Upper IC to lower IC Symbol Min. Typ. Max. 110 Unit ns Type* A Propagation delay 17.2 Lower IC to upper IC (2) 140 ns A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. MISO_IN, IRQ_IN to MISO, IRQ 2. SCK, MOSI, CS_N, CLK to SCK_OUT, MOSI_OUT, CS_N_OUT, CLK_OUT 37 9116B–AUTO–10/09 7.6.5.3 Test-mode Pins The test-mode pins DTST, ATST, PWTST (outputs) have to be kept open in the application. The test-mode pins SCANMODE and CS_FUSE (inputs) have to be connected to VSSA. These inputs have an internal pull-down resistor. The test-mode pin VDDFUSE is a supply pin. It must also be connected to VSSA. Table 7-25. Input Characteristics Pins SCANMODE, CS_FUSE, VDDFUSE Test Conditions Pin Symbol Min. 50 Typ. Max. 200 Unit kΩ Type* A SCANMODE, RSCANMODE, CS_FUSE RCS_FUSE No. Parameters 18.1 Pull-down resistor *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 7.7 7.7.1 Operations Voltage and Temperature Measurement At startup, the ATA6870 is supplied and is waiting for any operation request. The available operations are: • 6 channels voltage acquisition with a temperature acquisition – with voltage = V(MBATi+1, MBATi) (standard operation) and with voltage = V(TEMP1 or TEMP2, TEMPVSS) (standard operation) – with voltage = V(MBATi, MBATi) (offset calibration: CalOffset operation) and with voltage = V(TEMPVSS, TEMPVSS) (offset calibration: CalOffset operation) – with voltage = V(VREFi, MBATi) (gain calibration: CalGain operation) and with voltage = V(TEMPREF, TEMPVSS) (gain calibration: CalGain operation) Operation completion is flagged to the host MCU via the IRQ output in conjunction with dataRdy bit set in the status register. In order to retrieve the full results in a single access, the user has to access the dataRd16burst register (112 bits). Getting the results of a single channel (voltage or temperature) is also possible. For this, first select the channel to read through the ChannelReadSel register, then retrieve the channel value through the DataRd16 register. It is not possible to order a new operation until the previous operation has been acknowledged. The host MCU acknowledges the interrupt by reading the status register. This resets the dataRdy bit as well as the IRQ output, and enables the ATA6870 to start the next operation. Writing NoOp in the Operation register during an operation running aborts the current operation. In this case, the dataRdy bit is not set and interrupt is not requested to the host MCU. The Opstatus register flags whether operation is running, aborted, ended, or no operation is running. 38 ATA6870 [Preliminary] 9116B–AUTO–10/09 ATA6870 [Preliminary] 7.7.2 Discharge Function Each channel is independently dischargeable. Discharge is activated or deactivated by the register ChannelDischSel. Low Frequency Timer Function A low frequency timer (LFT), synchronous to internal 50 kHz oscillator provides the host MCU with a low power timer, which useful to either synchronize operations in the host MCU or monitor the ATA6870’s activity. The LFT elapsing asserts an interrupt to the host MCU if the corresponding mask bit in the IrqMask register is not set. Default is LFT not enabled. To enable the LFT, set the LFTimer_ena bit to 1 in the Ctrl register. LFT counting time is fully programmable in the register LFTimer. Changing the LFTimer register restarts the LFT if the new counting time is smaller than the current value of the LFT. Otherwise, LFT runs until it reaches the new end value. Asserting LFTRst bit in the Rstr register resets and restarts the LFT if the LFT is enabled. Otherwise, LFT is reset but not started. Each ATA6870 will assert its own interrupt when the timer elapses. Depending on how the timer is used, the host MCU may mask LFTdone interrupts in the whole ATA6870s chain, except the first one. As internal RC oscillators are not synchronized, this prevents the MCU from being interrupted each time one of the LFT elapses. 7.7.4 Undervoltage Detection A programmable undervoltage detection function is embedded in the ATA6870. After being digitalized, each of the 6 voltages is compared to a programmable threshold defined in the UdvThresh register. If one of the six channels is out of the range defined by the threshold, an interrupt is requested to the host MCU if the corresponding udv mask bit is not set in the IrqMask register. The default threshold is 1.5V. As soon as MCU has acknowledged, undervoltage information is no more available to MCU, because status register is cleared when MCU reads it out. As a consequence, the next undervoltage interrupt cannot occur until the ATA6870 leaves its current undervoltage state. 7.7.3 39 9116B–AUTO–10/09 7.8 Registers Registers are read and written through the SPI interface. Table 7-26. Register Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x10 0x11 0x12 0x7F Register Mapping Control Field Control Field Read Mode Write Mode 0x00 0x02 0x04 0x06 0x0A 0x0C 0x10 0x12 0x14 0x16 0x18 0x1A 0x20 0x22 0x24 0xFE 0x03 0x05 0x09 0x0B 0x13 0x15 0x17 0x1B 0x21 0x25 Register Name RevID Ctrl Operation OpStatus Rstr IrqMask Status ChannelUdvStatus ChannelDischSel ChannelReadSel LFTimer CalibStatus FuseCtrl UdvThresh DataRd16 ATA6870Test DataRd16Burst Access R RW RW R W RW R R RW RW RW R RW RW R RW R Type 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 16 bits 16 bits 16 bits 112 bits Function Revision ID/value Mfirst, pow_on Control Register Operation request Operation status Software reset Mask interrupt sources Status interrupt sources Channels undervoltage status Select channel to discharge Select channel to read Low Frequency Timer control Reserved Reserved Undervoltage detection threshold Single access to selected channel value Reserved Burst Access to the whole channels (6 voltage and 1 temperature) 40 ATA6870 [Preliminary] 9116B–AUTO–10/09 ATA6870 [Preliminary] 7.8.1 7.8.1.1 Registers Content RevID Register Table 7-27. RevId Register Overview RevID 0x00 6 x 5 x 4 pow_en 3 Mfirst Reset Value 2 1 RevID 0x02 0 (lsb) Register Address 7 (msb) x Table 7-28. RevId Register Content Description ATA6870 revision number, revision B: 0x02 Status input pin MFIRST Status input pin POW_EN Bit Field RevID Mfirst pow_en 7.8.1.2 Ctrl Register Table 7-29. Ctrl Register Overview Ctrl 0x01 6 x 5 x 4 3 Reset Value 2 1 x 0x00 0 (lsb) x Register Address 7 (msb) x Chksum_ena LFTimer_ena TFMODE_ena Table 7-30. Ctrl Register Content Description 0: Prevent ATA6870 to switch to test mode 1: Not allowed for customer use 0: Disable internal Low Frequency Timer 1: Enable internal Low Frequency Timer 0: Disable SPI transaction checksum computation/check 1: Enable SPI transaction checksum computation/check Bit Field TFMode_ena LFTimer_ena Chksum_ena 7.8.1.3 Operation Register Table 7-31. Operation Register Overview Operation 0x02 6 x 5 OpMode 4 3 TempMode Reset Value 2 VoltMode 1 0x02 0 (lsb) OpRqst Register Address 7 (msb) x 41 9116B–AUTO–10/09 Table 7-32. Operation Register Content Description 0: NoOp: No Operation, or abort current operation 1: AcqRqst: Start the analog to digital conversion An interrupt is generated when data is available in DataRd16/DataRd16Burst. 00: Caloffset: select V(MBAT(i), MBAT(i)) as input of voltage channels. (offset calibration) 01: AcqV: select V(MBAT(i+1), MBAT(i)) as input of voltage channels (default) 10: Not allowed 11: Calgain: select V(vref(i)) as input of voltage channels. (gain calibration) 0: Select TEMP1 input pin as input of temperature channel 1: Select TEMP2 input pin as input of temperature channel 00: 6 voltage channels and temperature acquisition 01: No acquisition performed 10: No acquisition performed 11: No acquisition performed Bit Field OpRqst VoltMode TempMode OpMode When a conversion operation is finished and the interrupt has been acknowledged by the MCU the Operation register is automatically reset to “NoOp”. Writing “NoOp” in the register when conversion operation is running, aborts the current operation. Other changes are not accepted during any operation. Figure 7-28. Typical Data Acquisition Flow ASIC3 (MFIRST = 0) ASIC2 (MFIRST = 0) ASIC1 (MFIRST = 1) MCU Init State Opstatus = NoOP Status Cleared Init State Opstatus = NoOP Status Cleared Init State Opstatus = NoOP Status Cleared ... Set Operation = ACQ*/CAL* Runs Conversion Opstatus = Running Conversion Finished Opstatus = Result Available Status = Data Ready IRQ DATA RDY Runs Conversion Opstatus = Running Conversion Finished Opstatus = Result Available Status = Data Ready IRQ DATA RDY Runs Conversion Opstatus = Running Conversion Finished Opstatus = Result Available Status = Data Ready IRQ DATA RDY Background Tasks/Idle Opstatus = NoOP Status Cleared ASIC3 Read/Check Opstatus Read/Check Status Opstatus = NoOP Status Cleared ASIC2 Read/Check Opstatus Read/Check Status Opstatus = NoOP IRQ Acknowledged Status Cleared ASIC1 Read/Check Opstatus Read/Check Status ASIC3 Burst Read Data ASIC2 Burst Read Data ASIC1 Burst Read Data ... 42 ATA6870 [Preliminary] 9116B–AUTO–10/09 ATA6870 [Preliminary] 7.8.1.4 OpStatus Register Table 7-33. OpStatus Register Overview OpStatus 0x03 6 x 5 x 4 x 3 x Reset Value 2 x 1 0x00 0 (lsb) OpStatus Register Address 7 (msb) x Table 7-34. OpStatus Register Content Description 00: No Operation 01: Operation is ongoing 10: Operation is finished, result is available 11: Operation is cancelled, result is not available Bit Field OpStatus Figure 7-29. Operation Status Register Management User reads Operation Status Register, Reset NO OP Users programs conversions operation Operation Running Users programs NoOp End of conversion Operation Aborted, Result not Available Operation Finished, Result Available User programs conversion operation or reads operation status register Status reg has been read and: User programs conversion operation or reads operation status register The OPStatus register is reset when read after a completed or aborted operation. Reading the register before starting an operation is not mandatory. Reading data conversion results or reading the OpStatus Register during an operation does not affect the OpStatus register. 43 9116B–AUTO–10/09 7.8.1.5 Rstr Register Table 7-35. Rstr Register Overview Rstr 0x04 6 x 5 x 4 x 3 x Reset Value 2 x 1 LFTRst 0x00 0 (lsb) 0 Register Address 7 (msb) x Table 7-36. Rstr Register Content Description 0: No reset 1: Low Frequency Timer software reset Bit Field LFTRst LFTRst resets and restarts the low frequency timer if not disabled (LFTimer_ena = 0). 7.8.1.6 IrqMask Register Table 7-37. Register Address 7 (msb) x 6 x 5 x 0x05 4 3 IrqMask Register Overview IrqMask Reset Value 2 1 0x00 0 (lsb) chkErrorMask udvmask commErrorMask LFTdoneMask dataDryMask Table 7-38. Bit Field IrqMask Register Content Description Mask data ready interrupt when set to 1 Mask LFTdone interrupt when set to 1 Mask commError interrupt when set to 1 Mask undervoltage detection interrupt when set to 1 Mask checksum error interrupt when set to 1 dataRdyMask WakeupMask commErrorMask udvMask chkErrorMask 44 ATA6870 [Preliminary] 9116B–AUTO–10/09 ATA6870 [Preliminary] 7.8.1.7 Status Register Table 7-39. Status Register Overview Status 0x06 6 TFMdeOn 5 por 4 chkError 3 udv Reset Value 2 commError 1 LFTdone 0x10 0 (lsb) dataRdy Register Address 7 (msb) x Table 7-40. Bit Field dataRdy LFTdone Status Register Content Description Conversion finished Low frequency timer elapsed Bad SPI command detected (wrong length) Undervoltage detected Error on checksum check Power on reset detected Test mode on commError udv chkError Por TFMdeOn Any bit among {dataRdy, LFTdone, commError, udv, chkError} set in the status register requests an interrupt to the external MCU if the corresponding mask bit in the IrqMask register is 0. Reading the status register acknowledges the interrupt and resets its content. Por and TFMdeOn cause no interrupt. 45 9116B–AUTO–10/09 7.8.1.8 ChannelUdvStatus Register Table 7-41. Register Address 7 (msb) x 6 x 5 0x08 4 3 ChannelUdvStatus Register Overview ChannelUdvStatus Reset Value 2 1 0x00 0 (lsb) chUdv6_stat chUdv5_stat chUdv4_stat chUdv3_stat chUdv2_stat chUdv1_stat Table 7-42. ChannelUdvStatus Register Content Description 1: Undervoltage detected on channel 1 0: No undervoltage detected on channel 1 1: Undervoltage detected on channel 2 0: No undervoltage detected on channel 2 1: Undervoltage detected on channel 3 0: No undervoltage detected on channel 3 1: Undervoltage detected on channel 4 0: No undervoltage detected on channel 4 1: Undervoltage detected on channel 5 0: No undervoltage detected on channel 5 1: Undervoltage detected on channel 6 0: No undervoltage detected on channel 6 Bit Field chUdv1_stat chUdv2_stat chUdv3_stat chUdv4_stat chUdv5_stat chUdv6_stat Undervoltage is detected when voltage decreases under the threshold value defined in udvThresh register. When undervoltage is detected on a channel, the ATA6870 requests an interrupt if the UDVmask bit in the IRQMask register is 0. 46 ATA6870 [Preliminary] 9116B–AUTO–10/09 ATA6870 [Preliminary] 7.8.1.9 ChannelDischSel Register Table 7-43. ChannelDischSel Register Overview ChannelDischSel 0x09 6 x 5 4 3 chV6_disch chV5_disch chV4_disch Reset Value 2 1 0x00 0 (lsb) Register Address 7 (msb) x chV3_disch chV2_disch chV1_disch Table 7-44. ChannelDischSel Register Content Description 1: Enable voltage channel 1 discharge 0: Disable voltage channel 1 discharge 1: Enable voltage channel 2 discharge 0: Disable voltage channel 2 discharge 1: Enable voltage channel 3 discharge 0: Disable voltage channel 3 discharge 1: Enable voltage channel 4 discharge 0: Disable voltage channel 4 discharge 1: Enable voltage channel 5 discharge 0: Disable voltage channel 5 discharge 1: Enable voltage channel 6 discharge 0: Disable voltage channel 6 discharge Bit Field chV1_disch chV2_disch chV3_disch chV4_disch chV5_disch chV6_disch The channels are dischargeable simultaneously. 7.8.1.10 ChannelReadSel Register Table 7-45. ChannelReadSel Register Overview ChannelReadSel 0x0A 6 5 4 3 Reset Value 2 1 ChannelReadSel 0x00 0 (lsb) Register Address 7 (msb) 47 9116B–AUTO–10/09 Table 7-46. Bit Field ChannelReadSel Register Content Description 111: Value of the LFT is returned in DataRd16 register 110: Temperature channel available in DataRd16 register 101: Voltage channel6, value available in DataRd16 register 100: Voltage channel5, value available in DataRd16 register 011: Voltage channel4, value available in DataRd16 register 010: Voltage channel3, value available in DataRd16 register 001: Voltage channel2, value available in DataRd16 register 000: Voltage channel1, value available in DataRd16 register ChannelReadSel This register can be used to quickly read a single channel without using a full burst access. The value of the selected channel will be available in the DataRd16 register. The value will always be updated by writing a channel address to the ChannelReadSel register. Data in this register is not valid during ongoing data conversion. 7.8.1.11 LFTimer Register LFTimer Register Overview Register Address 7 (msb) LFTPrescaler 6 5 0x0B 4 3 LFTDelay LFTimer Reset Value 2 1 0xF9 0 (lsb) Table 7-47. Bit Field LFTimer Register Content Description Contains the present Low Frequency Timer delay value 0: PrescalerValue = 1 1: PrescalerValue = 6 LFTDelay LFTPrescaler The default timer value is 59.965s (0xF9) for fOSC = 50 kHz. Figure 7-30. Block Diagram LFTimer LFTprescaler LFTdelay 50 kHz /4096 /6 7-bit counter Comp Delay Time elapsed clear Formula for Delay Time calculation: LFTprescaler D 1Delay Time = ------------------------ × 4096 × ( 6 ) × ( LFTdelay D + 1 ) T OSC [Hz] 48 ATA6870 [Preliminary] 9116B–AUTO–10/09 ATA6870 [Preliminary] The LFT can be programmed to the following values (fOSC = 50 kHz): LFTprescaler = 0: LFTprescaler = 1: 0.082s