ATA8402

Features • Integrated PLL Loop Filter • ESD Protection (4 kV HBM/200V MM; Except Pin 2: 4 kV HBM/100V MM) also at ANT1/ANT2 • High Output Power (7.5 dBm) with Low Supply Current (9.0 mA) • Modulation Scheme ASK/FSK – FSK Modulation is Achieved by Connecting an Additional Capacitor Between the XTAL Load Capacitor and the Open Drain Output of the Modulating Microcontroller Easy to Design-in Due to Excellent Isolation of the PLL from the PA and Power Supply Single Li-cell for Power Supply Supply Voltage 2.0V to 4.0V in the Temperature Range of –40°C to +85°C Package TSSOP8L Single-ended Antenna Output with High Efficient Power Amplifier CLK Output for Clocking the Microcontroller One-chip Solution with Minimum External Circuitry • • • • • • • UHF ASK/FSK Industrial Transmitter ATA8402 Applications • • • • • • • Industrial/Aftermarket Remote Keyless Entry Systems Alarm, Telemetering, and Energy Metering Systems Remote Control Systems for Consumer and Industrial Markets Access Control Systems Home Automation Home Entertainment Toys 1. Description The ATA8402 is a PLL transmitter IC, which has been developed for the demands of RF low-cost transmission systems for industrial applications at data rates up to 50 kBaud ASK and 32 kBaud FSK modulation scheme. The transmitting frequency range is 429 MHz to 439 MHz. It can be used in both FSK and ASK systems. Figure 1-1. 1 Li cell System Block Diagram UHF ASK/FSK Remote control transmitter ATA8402 UHF ASK/FSK Remote control receiver ATA3741/ ATA3745/ ATA5743/ ATA5744 ATA8202 Antenna XTO VCO Antenna PLL XTO 1 to 3 Demod Control Microcontroller Keys Encoder ATARx9x PLL Power amp. LNA VCO 4982A–IND–02/07 2. Pin Configuration Figure 2-1. Pinning TSSOP8L CLK PA_ENABLE ANT2 ANT1 1 2 3 4 8 7 6 5 ENABLE GND VS XTAL Table 2-1. Pin Pin Description Symbol Function Configuration VS 1 CLK Clock output signal for microconroller The clock output frequency is set by the crystal to fXTAL/4 100Ω CLK 100Ω PA_ENABLE 50 kΩ UREF = 1.1V 2 PA_ENABLE Switches on power amplifier, which is used for ASK modulation 20 µA ANT1 3 4 ANT2 ANT1 Emitter of antenna output stage Open collector antenna output ANT2 2 ATA8402 4982A–IND–02/07 ATA8402 Table 2-1. Pin Pin Description (Continued) Symbol Function Configuration VS VS 1.5 kΩ 1.2 kΩ 5 XTAL Connection for crystal XTAL 182 µA 6 7 VS GND Supply voltage Ground See ESD protection circuitry (see Figure 4-5 on page 9) See ESD protection circuitry (see Figure 4-5 on page 9) ENABLE 200 kΩ 8 ENABLE Enable input Figure 2-2. Block Diagram ATA8402 Power up/down f 1 4 8 CLK ENABLE f 32 PA_ENABLE 2 PDF 7 GND CP ANT2 3 LF 6 VS ANT1 4 PA PLL VCO XTO 5 XTAL 3 4982A–IND–02/07 3. General Description This fully integrated PLL transmitter allows particularly simple, low-cost RF miniature transmitters to be assembled. The VCO is locked to 32 f XTAL, and therefore a 13.56 MHz crystal is needed for a 433.92 MHz transmitter. All other PLL and VCO peripheral elements are integrated. The XTO is a series resonance oscillator so that only one capacitor together with a crystal connected in series to GND are needed as external elements. The crystal oscillator together with the PLL typically needs < 1 ms until the PLL is locked and the CLK output is stable. There is a wait time of ≥ 1 ms until the CLK is used for the microcontroller and the PA is switched on. The power amplifier is an open-collector output delivering a current pulse, which is nearly independent from the load impedance. The delivered output power is therefore controllable via the connected load impedance. This output configuration enables a simple matching to any kind of antenna or to 50Ω. A high power efficiency of η= Pout/(IS,PA VS) of 36% for the power amplifier results when an optimized load impedance of ZLoad = (166 + j223)Ω is used at 3V supply voltage. 4. Functional Description If ENABLE = L and the PA_ENABLE = L, the circuit is in standby mode, consuming only a very small amount of current, so that a lithium cell used as power supply can work for several years. With ENABLE = H the XTO, PLL, and the CLK driver are switched on. If PA_ENABLE remains L, only the PLL and the XTO are running, and the CLK signal is delivered to the microcontroller. The VCO locks to 32 times the XTO frequency. With ENABLE = H and PA_ENABLE = H the PLL, XTO, CLK driver, and the power amplifier are on. The power amplifier can be switched on and off with PA_ENABLE. This is used to perform the ASK modulation. 4.1 ASK Transmission The ATA8402 is activated by ENABLE = H. PA_ENABLE must remain L for t ≥1 ms, then the CLK signal can be taken to clock the microcontroller and the output power can be modulated by means of the PA_ENABLE pin. After transmission, PA_ENABLE is switched to L and the microcontroller switches back to internal clocking. The ATA8402 is switched back to standby mode with ENABLE = L. 4.2 FSK Transmission The ATA8402 is activated by ENABLE = H. PA_ENABLE must remain L for t ≥1 ms, then the CLK signal can be taken to clock the microcontroller, and the power amplifier is switched on with PA_ENABLE = H. The chip is then ready for FSK modulation. The microcontroller starts to switch on and off the capacitor between the XTAL load capacitor and GND with an open-drain output port, thus changing the reference frequency of the PLL. If the switch is closed, the output frequency is lower than if the switch is open. After transmission, PA_ENABLE is switched to L, and the microcontroller switches back to internal clocking. The ATA8402 is switched back to standby mode with ENABLE = L. The accuracy of the frequency deviation with XTAL pulling method is about ±25% when the following tolerances are considered. 4 ATA8402 4982A–IND–02/07 ATA8402 Figure 4-1. Tolerances of Frequency Modulation VS CStray1 LM XTAL CM RS CStray2 C4 C0 Crystal equivalent circuit C5 CSwitch Using C4 = 9.2 pF ±2%, C5 = 6.8 pF ±5%, a switch port with CSwitch = 3 pF ±10%, stray capacitances on each side of the crystal of CStray1 = CStray2 = 1 pF ±10%, a parallel capacitance of the crystal of C0 = 3.2 pF ±10% and a crystal with CM = 13 fF ±10%, typically results in an FSK deviation of ±21 kHz with worst case tolerances of ±16.3 kHz to ±28.8 kHz. 4.3 CLK Output An output CLK signal is provided for a connected microcontroller. The delivered signal is CMOS compatible if the load capacitance is lower than 10 pF. 4.3.1 Clock Pulse Take-over The clock of the crystal oscillator can be used for clocking the microcontroller. A special feature of Atmel®’s ATARx9x is that it starts with an integrated RC-oscillator to switch on the ATA8402 with ENABLE = H, and after 1 ms assumes the clock signal of the transmission IC, so that the message can be sent with crystal accuracy. Output Matching and Power Setting The output power is set by the load impedance of the antenna. The maximum output power is achieved with a load impedance of ZLoad,opt = (166 + j223)Ω. There must be a low resistive path to VS to deliver the DC current. The delivered current pulse of the power amplifier is 9 mA. The maximum output power is delivered to a resistive load of 465Ω i f the 1.0 pF output capacitance of the power amplifier is compensated by the load impedance. An optimum load impedance of: ZLoad = 465Ω || j/(2 × π 1.0 pF) = (166 + j223)Ω thus results for the maximum output power of 7.5 dBm. The load impedance is defined as the impedance seen from the ATA8402’s ANT1, ANT2 into the matching network. Do not confuse this large signal load impedance with a small signal input impedance delivered as input characteristic of RF amplifiers and measured from the application into the IC instead of from the IC into the application for a power amplifier. Less output power is achieved by lowering the real parallel part of 465Ω where the parallel imaginary part should be kept constant. Output power measurement can be done with the circuit shown in Figure 4-2 on page 6. Note that the component values must be changed to compensate for individual board parasitics until the ATA8402 has the right load impedance ZLoad,opt = (166 + j223)Ω. Also the damping of the cable used to measure the output power must be calibrated out. 4.3.2 5 4982A–IND–02/07 Figure 4-2. Output Power Measurement VS C1 1 nF L1 ANT1 ZLopt ANT2 33 nH C2 2.2 pF Z = 50Ω Power meter Rin 50Ω 4.4 Application Circuit A value of 68 nF/X7R is recommended for the supply-voltage blocking capacitor C3 (see Figure 4-3 on page 7 and Figure 4-4 on page 8). C1 and C2 are used to match the loop antenna to the power amplifier where C1 typically is 8.2 pF/NP0 and C2 is 6 pF/NP0 (10 pF + 15 pF in series). For C2, two capacitors in series should be used to achieve a better tolerance value and to have the possibility of realizing the ZLoad,opt using standard valued capacitors. C1, together with the pins of ATA8402 and the PCB board wires, forms a series resonance loop that suppresses the 1st harmonic. Therefore, the position of C1 on the PCB is important. Normally the best suppression is achieved when C1 is placed as close as possible to the pins ANT1 and ANT2. The loop antenna should not exceed a width of 1.5 mm, otherwise the Q-factor of the loop antenna is too high. L1 ([50 nH to 100 nH) can be printed on PCB. C4 should be selected so that the XTO runs on the load resonance frequency of the crystal. Normally, a 15 pF load-capacitance crystal results in a value of 12 pF. 6 ATA8402 4982A–IND–02/07 ATA8402 Figure 4-3. ASK Application Circuit S1 BPXY ATARx9x 1 VDD VS VSS 20 S2 BPXY BPXY OSC1 7 BPXY ATA8402 Power up/down CLK 1 f 4 8 ENABLE f 32 PA_ENABLE 2 PDF 7 GND C3 CP ANT2 3 Loop Antenna C1 LF 6 VS VS C2 ANT1 4 L1 PA PLL VCO XTO 5 XTAL XTAL C4 VS 7 4982A–IND–02/07 Figure 4-4. FSK Application Circuit S1 BPXY ATARx9x 1 VDD VS VSS 20 S2 BPXY BPXY 18 OSC1 7 BP42/T2O BPXY ATA8402 Power up/down CLK 1 f 4 8 ENABLE f 32 PA_ENABLE 2 PDF 7 GND C3 CP ANT2 3 Loop Antenna C1 LF 6 VS C5 ANT1 4 L1 PA PLL VCO XTO 5 C4 XTAL XTAL VS C2 VS 8 ATA8402 4982A–IND–02/07 ATA8402 Figure 4-5. ESD Protection Circuit VS ANT1 CLK PA_ENABLE ANT2 XTAL ENABLE GND 5. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Supply voltage Power dissipation Junction temperature Storage temperature Ambient temperature Input voltage Note: Symbol VS Ptot Tj Tstg Tamb VmaxPA_ENABLE –55 –55 –0.3 Minimum Maximum 5 100 150 +85 +85 (VS + 0.3) (1) Unit V mW °C °C °C V 1. If VS + 0.3 is higher than 3.7V, the maximum voltage will be reduced to 3.7V. 6. Thermal Resistance Parameters Junction ambient Symbol RthJA Value 170 Unit K/W 7. Electrical Characteristics VS = 2.0V to 4.0V, Tamb = 25°C unless otherwise specified. Typical values are given at VS = 3.0 V and Tamb = 25°C. All parameters are referred to GND (pin 7). Parameters Test Conditions Power down VENABLE < 0.25V, –40°C to 85°C VPA-ENABLE < 0.25V, 25°C (100% correlation tested) Power up, PA off, VS = 3V, VENABLE > 1.7V, VPA-ENABLE < 0.25V Power up, VS = 3.0V, VENABLE > 1.7V, VPA-ENABLE > 1.7V VS = 3.0V, Tamb = 25°C, f = 433.92 MHz, ZLoad = (166 + j233)Ω Symbol Min. Typ. Max. 350 < 10 Unit nA nA Supply current IS_Off Supply current Supply current Output power Note: IS IS_Transmit PRef 5.5 3.7 9 7.5 4.8 11.6 10 mA mA dBm 1. If VS is higher than 3.6V, the maximum voltage will be reduced to 3.6V. 9 4982A–IND–02/07 7. Electrical Characteristics (Continued) VS = 2.0V to 4.0V, Tamb = 25°C unless otherwise specified. Typical values are given at VS = 3.0 V and Tamb = 25°C. All parameters are referred to GND (pin 7). Parameters Output power variation for the full temperature range Test Conditions Tamb = 25°C, VS = 3.0V VS = 2.0V Tamb = 25°C, VS = 3.0V VS = 2.0V POut = PRef + ∆PRef Selectable by load impedance fCLK = f0/128 Load capacitance at pin CLK = 10 pF fO ±1 × fCLK fO ±4 × fCLK Other spurious are lower fXTO = f0/32 fXTAL = resonant frequency of the XTAL, CM ≤ 10 fF, load capacitance selected accordingly Tamb = 25°C Referred to fPC = fXT0, 25 kHz distance to carrier 25 kHz distance to carrier At 1 MHz At 36 MHz fVCO 429 f0/128 CLoad ≤10 pF V0h V0l Rs Duty cycle of the modulation signal = 50% Duty cycle of the modulation signal = 50% Low level input voltage High level input voltage Input current high Low level input voltage High level input voltage Input current high VIl VIh IIn VIl VIh IIn 0 0 1.7 20 1.7 0.25 VS(1) 5 VS × 0.8 VS × 0.2 110 7 32 50 0.25 Symbol ∆PRef ∆PRef ∆PRef ∆PRef POut_typ 0 Min. Typ. Max. –1.5 –4.0 –2.0 –4.5 7.5 Unit dB dB dB dB dBm Output power variation for the full temperature range Achievable output-power range Spurious emission –55 –52 dBc dBc Oscillator frequency XTO (= phase comparator frequency) fXTO fXTAL ppm PLL loop bandwidth Phase noise of phase comparator In-loop phase noise PLL Phase noise VCO Frequency range of VCO Clock output frequency (CMOS microcontroller compatible) Voltage swing at pin CLK Series resonance R of the crystal Capacitive load at pin XT0 FSK modulation frequency rate ASK modulation frequency rate ENABLE input 250 –116 –86 –94 –125 –110 –80 –90 –121 439 kHz dBc/Hz dBc/Hz dBc/Hz dBc/Hz MHz MHz V V Ω pF kHz kHz V V µA V V µA PA_ENABLE input Note: 1. If VS is higher than 3.6V, the maximum voltage will be reduced to 3.6V. 10 ATA8402 4982A–IND–02/07 ATA8402 8. Ordering Information Extended Type Number ATA8402-6AQY Package TSSOP8L MOQ 5000 pcs Remarks Taped and reeled, Pb-free 9. Package Information Package: TSSOP 8L Dimensions in mm 0.85±0.05 1-0.15 +0.05 3±0.1 3±0.1 0.31-0.07 0.65 nom. 3 x 0.65 = 1.95 nom. 8 5 3.8±0.3 4.9±0.1 technical drawings according to DIN specifications Drawing-No.: 6.543-5083.01-4 Issue: 2; 15.03.04 1 4 5 0.15-0.02 +0.0 +0.06 0.1±0.05 11 4982A–IND–02/07 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. 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