ATC18M

Features • Comprehensive Library of Standard Logic and I/O Cells • ATC18 Core and I/O Cells Designed to Operate with VDD = 1.8V ± 0.15V as Main Target Operating Conditions • IO33 Pad Libraries Provide Interfaces to 3V Environments • Memory Cells Compiled to the Precise Requirements of the Design • Compatible with Atmel’s Extensive Range of Microcontroller, DSP, Standard-interface • • • • • • • • • and Application-specific Cells EDAC Library SEU Hardened DFF’s Cold Sparring Buffers High Speed LVDS Buffers PCI Buffer Predefined die Sizes to Easily Accommodate Specified Packages MQFP Packages up to 352 pins (340 Signal Pins) MCGA Packages up to 625 pins (581 Signal Pins) Offered to QML Q Grade 0.18 µm CMOS Cell-based ASIC for Military Use ATC18M Advanced Information Description The Atmel ATC18M is fabricated on a proprietary 0.18 µm, up to six-layer-metal CMOS process intended for use with a supply voltage of 1.8V ± 0.15V. Table 1 shows the range for which Atmel library cells have been characterized. Table 1. Recommended Operating Conditions Symbol VDD VDD3.3 VI VO TEMP Parameter DC Supply Voltage DC Supply Voltage DC Input Voltage DC Output Voltage Operating Free Air Temperature Range Military Conditions Core and Standard I/Os 3V Interface I/Os Min 1.65 3 0 0 -55 Typ 1.8 3.3 Max 1.95 3.6 VDD VDD +125 Unit V V V V °C The Atmel cell libraries and megacell compilers have been designed in order to be compatible with each other. Simulation representations exist for three types of operating conditions. They correspond to three characterization conditions defined as follows: • MIN conditions: – – – • – – – • – – – TJ = -55°C VDD (cell) = 1.95V Process = fast TJ = +25°C VDD (cell) = 1.8V Process = typ TJ = +125°C VDD (cell) = 1.65V Process = slow Rev. 4262A–AERO–07/03 TYP conditions: MAX conditions: 1 Delays to tri-state are defined as delay to turn off (VGS < VT) of the driving devices. Output pad drain current corresponds to the output current of the pad when the output voltage is VOL or VOH. The output resistor of the pad and the voltage drop due to access resistors (in and out of the die) are taken into account. In order to have accurate timing estimates, all characterization has been run on electrical netlists extracted from the layout database. Standard Cell Library SClib The Atmel Standard Cell Library, SClib, contains a comprehensive set of a combination of logic and storage cells. The SClib library includes cells that belong to the following categories: • Buffers and Gates • Multiplexers • Flip-flops • Scan Flip-flops • Latches • Adders and Subtractors Table 2 shows the naming conventions for the cells in the SClib library. Each cell name begins with either a two-, three-, or four-letter code that defines the type of cell. This indicates the range of standard cells available. Decoding the Cell Name Table 2. Cell Codes Code AD AH AS AN AOI AON AOR BUFB BUFF BUFT CG CLK2 DF DLA H... INV0 Description Adder Half Adder Adder/Subtractor AND Gate AND-OR-Invert Gate AND-OR-AND-Invert Gates AND-OR Gate Balanced Buffer Non-Inverting Buffer Non-Inverting Tri-state Buffer Carry Generator Clock Buffer D Flip-flop Dual Input Latches SEU Hardened Versions Inverter Code INVB INVT LA MI MX ND NR OAI OAN OR ORA SD SRLA SU XN XR Description Balanced Inverter Inverting Tri-state Buffer D Latch Inverting Multiplexer Multiplexer NAND Gate NOR Gate OR-AND-Invert Gate OR-AND-OR-Invert Gates OR Gate OR-AND Gate Multiplexed Scan D Flip-flop Set/Reset Latches with NAND input Subtractor Exclusive NOR Gate Exclusive OR Gate 2 ATC18M 4262A–AERO–07/03 ATC18M Cell Matrices Table 3 and Table 4 provide a quick reference to the storage elements in the SClib library. Note that all storage elements feature buffered clock inputs and buffered output. Table 3. D Flip-flops Macro Name DFBRBx DFCRBx HDFBRBx HDFCRBx DFNRBx HDFVRBx DFPRBx HDFPRBx DENRQx • • • • Set • Clear • • • • Enabled D Input 1xDrive • • • • • • • • • 2xDrive • • • • • • • • • • • • • • Single Output SEU Hardened Table 4. Scan Flip-flops Macro Name SDBRBx SDCRBx HSDBRBx HSDCRBx SDNRBx HSDNPBx SDNRQx HSDNRQx • Set • Clear • • • • 1xDrive • • • • • • • • 2xDrive • • • • • • • • • • • • • Single Output SEU Hardened 3 4262A–AERO–07/03 Input/Output Pad Cell Libraries IO18lib and IO33lib The Atmel Input/Output Cell Library, IO18lib, contains a comprehensive list of input, output, bi-directional and tri-state cells. The ATC18M (1.8V) cell library includes one special sets of I/O cells, IO25lib and IO33lib, for interfacing with external 3.3V devices. They will encompass the following types of cells: • Bi-directional • • • • • • Tri-state outport Outputs Inputs PCI PECL LVDS (EIA-644) All buffers will be capable of being used as “Cold Sparing” Buffers. Compiled Memories Based on Virage Logic Memory Compilers, for synchronized memories. Its maximum memory size compilation capability is: SRAM DPRAM TPSF 16K x 32 bits 8K x 32 bits 1K x 16 bits A set of EDAC can be used in combination with these memories so as to alleviate their SEU susceptibility. Synthesized Memory The synthesis of memories is based on Atmel GENESYS within the GATEAID software. It must be used only for small memories and when SEU hardened cells are needed. The maximum memory sizes are as follows: RAM TPRAM DPRAM 4K bits 4K bits 2K bits 4 ATC18M 4262A–AERO–07/03 ATC18M Design Flow Though only MODELSIM and NCSIM will be used as the golden simulators, the design kit will include the data and libraries needed for the following tools: Tool GATEAID2 ® Supplier Atmel Mentor Cadence Synopsys® Cadence ® Purpose Atmel Support tools VHDL®/VITAL® RTL + gate level simulation VERILOG® RTL + gate level simulation HDL synthesis HDL synthesis Synthesis power optimization Scan+ATPG (FastScan), JTAG (BSDArchitect), BIST (MBIST-Architect) Floor-planning, physical knowledgeable synthesis, layout prototyping Static timing analysis Equivalence checking, formal proof MODELSIM® NCSIM® DESIGN COMPILER® BUILDGATES ® POWER COMPILER DFT SUITE FE-ULTRA PRIMETIME® FORMALITY Synopsys Mentor® Cadence Synopsys Synopsys The Design flow can be described in two sections: • • The front-end done at the customer’s premises The back-end at Atmel Technical Centers, provided that the front-end activity has been validated and accepted by Atmel during the Logic Review (LR) meeting. The following table lists the activities and tools that will be used during the front-end design. Function RTL SIMULATION Tool MODELSIM NC-SIM CODE COVERAGE RTL TO GATE SYNTHESIS VHDL-COVER DESIGN-COMPILER BUILD-GATES POWER OPTIMIZATION POWER ANALYSIS TEST INSERTION + ATPG GATE LEVEL SIMULATION POWER-COMPILER PRIME-POWER DFT-SUITE MODELSIM NC-SIM NETLIST TRANSLATION DESIGN RULES CHECK NETCVT STAR Supplier Mentor Cadence Transeda Synopsys Cadence Synopsys Synopsys Mentor Mentor Cadence Atmel Atmel 5 4262A–AERO–07/03 The following table lists the activities and the tools that will be used during the back-end design: Activities Bonding Diagram Function Array Definition Pads Coordinates Bonding Diagram Pads Preplacement Periphery Check Ibis Model Physical Implementation Blocks Preplacement Virtual Layout Prototyping Physically Knowledgeable Synthesis Power Routing Placement Scan Chains Ordering Placement-driven Violations Fix Clock Tree Synthesis Routing Parasitics Extraction Final Violations Fix Eco Place & Route Layout Edition 3d Extraction Tool MGTECHGEN PACO PIMTOOL P2DEF CAP GENIBIS SILVER FIRST ENCOUNTER PKS Supplier Atmel Atmel Atmel Atmel Atmel Atmel Atmel Cadence Cadence SNOW QPLACE QP/SCAN QP/OPT CTGEN® NANOROUTE HYPEREXTRACT QP/OPT SILICON ENSEMBLE SILVER FIRE&ICE Atmel Cadence Cadence Cadence Cadence Cadence Cadence Cadence Cadence Atmel Cadence 6 ATC18M 4262A–AERO–07/03 ATC18M Activities Final Verifications Function Static Timing Analysis Equivalence Checking Back-annotated Simulation Consumption Analysis Power Scheme Check Test Patterns Gdsii Generation Cross-talk Analysis Cross-talk Errors Fix Final Analysis Tool PRIMETIME FORMALITY MODELSIM NC-SIM MGCOMET VOLTAGESTORM PATFORM SE2GDS CELTIC SILICON ENSEMBLE SIGNALSTORM Supplier Synopsys Synopsys Mentor Cadence Atmel Cadence Atmel Atmel Cadence Cadence Cadence 7 4262A–AERO–07/03 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131 Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. 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Blvd. Colorado Springs, CO 80906 Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000 Fax: (44) 1355-242-743 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 e-mail literature@atmel.com Web Site http://www.atmel.com Disclaimer. A tmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. 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