ATC20

Features • Comprehensive Library of Standard Logic and I/O Cells • ATC20 Core and I/O Cells Designed to Operate with VDD = 1.8V ± 0.15V as Main Target Operating Conditions • IO25 and IO33 Pad Libraries Provide Interfaces to 2.5V and 3V Environments • Oscillators Provide Stable Clock Sources • Basic Analog Input/Output, Power, Ground and Multiplexer Cells Available, High-performance Analog Cells Can Be Developed on Request • Memory Cells Compiled to the Precise Requirements of the Design • Compatible with Atmel’s Extensive Range of Microcontroller, DSP, Standard-interface and Application-specific Cells Cell-based ASIC ATC20 Summary Description The Atmel ATC20 CBIC family is fabricated on a proprietary 0.21 micron five-layermetal CMOS process intended for use with a supply voltage of 1.8V ± 0.15V. The following table shows the range for which Atmel library cells have been characterized. Table 1. Recommended Operating Conditions Symbol VDD VDD2.5 VDD3.3 VI VO TEMP Parameter DC Supply Voltage DC Supply Voltage DC Supply Voltage DC Input Voltage DC Output Voltage Operating Free Air Temperature Range Industrial Conditions Core and Standard I/Os 2.5V Interface I/Os 3V Interface I/Os Min 1.65 2.25 3 0 0 -40 Typ 1.8 2.5 3.3 Max 1.95 2.75 3.6 VDD VDD +85 Unit V V V V V °C The Atmel cell libraries and megacell compilers have been designed in order to be compatible with each other. Simulation representations exist for three types of operating conditions. They correspond to three characterization conditions defined as follows: • MIN conditions: – – – • – – – • – – – TJ = -40°C VDD (cell) = 1.95V Process = fast (industrial best case) TJ = +25°C VDD (cell) = 1.8V Process = typ (industrial typical case) TJ = +100°C VDD (cell) = 1.65V Process = slow (industrial worst case) TYP conditions: MAX conditions: Delays to tri-state are defined as delay to turn off (VGS < VT) of the driving devices. Output pad drain current corresponds to the output current of the pad when the output voltage is VOL or VOH. The output resistor of the pad and the voltage drop due to access resistors (in and out of the die) are taken into account. In order to have accurate timing estimates, all characterization has been run on electrical netlists extracted from the layout database. Rev. 1361BS–CBIC–09/02 1 Standard Cell Library SClib The Atmel Standard Cell Library, SClib, contains a comprehensive set of combinational logic and storage cells. The SClib library includes cells which belong to the following categories: • • • • • • Buffers and Gates Multiplexers Flip-flops Scan Flip-flops Latches Adders and Subtractors Decoding the Cell Name The table below shows the naming conventions for the cells in the SClib library. Each cell name begins with either a two-, three-, or four-letter code that defines the type of cell. This indicates the range of standard cells available. Table 2. Cell Codes Code AD AH AS AN AOI AON AOR BH BUFB BUFF BUFT CG CLK2 DE DF INV0 INVB Description Adder Half Adder Adder/Subtractor AND Gate AND-OR-Invert Gate AND-OR-AND-Invert Gates AND-OR Gate Bus Holder Balanced Buffer Non-Inverting Buffer Non-Inverting 3-State Buffer Carry Generator Clock Buffer D-Enabled Flip-Flop D Flip-Flop Inverter Balanced Inverter Code INVT JK LA MI MX ND NR OAI OAN OR ORA SD SE SRLA SU XN XR Description Inverting 3-State Buffer JK Flip-Flop D Latch Inverting Multiplexer Multiplexer NAND Gate NOR Gate OR-AND-Invert Gate OR-AND-OR-Invert Gates OR Gate OR-AND Gate Multiplexed Scan D Flip-Flop Multiplexed Scan Enable D Flip-Flop Set/Reset Latches with NAND input Subtractor Exclusive NOR Gate Exclusive OR Gate 2 ATC20 Summary 1361BS–CBIC–09/02 ATC20 Summary Cell Matrices The following three tables provide a quick reference to the storage elements in the SClib library. Note that all storage elements feature buffered clock inputs and buffered output. Table 3. JK Flip-flops Macro Name JKBRBx Set Clear 1x Drive 2x Drive • • • • Table 4. D Flip-flops Macro Name DFBRBx DFCRBx DFCRQx DFCRNx DFNRBx DFNRQx DFPRBx DEPRQx DENRQx DENRBx DECRQx Set Clear Enabled D Input 1x Drive 2x Drive Single Output • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • Table 5. Scan Flip-flops Macro Name SDBRBx SDCRBx SDCRNx SDCRQx SDNRBx SDNRNx SDNRQx SDPRBx SECRQx SENRQx SEPRQx Set Clear 1x Drive 2x Drive Single Output • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 3 1361BS–CBIC–09/02 Input/Output Pad Cell Libraries IO18lib, IO25lib and IO33lib Voltage Levels The Atmel Input/Output Cell Library, IO18lib, contains a comprehensive list of input, output, bidirectional and tristate cells. The ATC20 (1.8V) cell library includes two special sets of I/O cells, IO25lib and IO33lib, for interfacing with external 2.5V and 3.3V devices. The IO18lib library is made up exclusively of low-voltage chip interface circuits powered by a voltage in the range of 1.65V to 1.95V. The library is compatible with the SClib 1.8volt standard cells library. Designers are strongly encouraged to provide three kinds of power pairs for the IO18lib library. These are “AC”, “DC” and core power pairs. AC power is used by the I/O to switch its output from one state to the other. This switching generates noise in the AC power buses on the chip. DC power is used by the I/O to maintain its output in a steady state. The best noise performance is achieved when the DC power buses on the chip are free of noise; designers are encouraged to use separate power pairs for AC and DC power to prevent most of the noise in the AC power buses from reaching the DC power buses. The same power pairs can be used to supply both DC power to the I/Os and power to the core without affecting noise performance. Power and Ground Pads Table 6. VSS Power Pad Combinations Core Vssi Switching I/O VssAC Quiet I/O VssDC Library Cell Name pv18i00 Signal Name VSS VSS VSS VSS VSS VSS • • • • • • • • • • pv18a00 pv18d00 pv18e00 pv18b00 pv18f00 Table 7. VDD Power Pad Combinations Core Vddi Switching I/O VddAC Quiet I/O VddDC Library Cell Name pv18i18 Signal Name VDD VDD VDD VDD VDD VDD • • • • • • • • • • pv18a18 pv18d18 pv18e18 pv18b18 pv18f18 4 ATC20 Summary 1361BS–CBIC–09/02 ATC20 Summary Cell Matrices Table 8. CMOS Pads CMOS Cell Name PC18B01 PC18B02 PC18B03 PC18B04 PC18B05 PC18O01 PC18O02 PC18O03 PC18O04 PC18O05 PC18T01 PC18T02 PC18T03 PC18T04 PC18T05 Output 3-State I/O Only 3-State Output Only Drive Strength 1x 2x 3x 4x 5x Pad Sites Used 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 • • • • • • • • • • • • • • • 1x 2x 3x 4x 5x 1x 2x 3x 4x 5x Table 9. TTL Pads TTL Cell Name PT18B01 PT18B02 PT18B03 PT18O01 PT18O02 PT18O03 PT18T01 PT18T02 PT18T03 3-State I/O Output Only 3-State Output Only Drive Strength 2 mA 4 mA 8 mA Pad Sites Used 1 1 1 1 1 1 1 1 1 • • • • • • • • • 2 mA 4 mA 8 mA 2 mA 4 mA 8 mA Table 10. CMOS/TTL Input Only Pad CMOS Cell Name PC18D01 PC18D11 PC18D21 PC18D31 Input Levels CMOS CMOS CMOS CMOS Schmitt Input Level Shifter Non-Inverting Inverting Pad Sites Used 1 • • • • • • 1 1 1 Note: All 3-state I/Os, 3-state output only and input pads are also available with pull-up and pull-down device. 5 1361BS–CBIC–09/02 IO25lib and IO33lib Low Slew Rate Cells The IO25lib (IO33lib) cells comprise a series of 1.8V/2.5V (1.8V/3.3V) input/output pads developed for low supply voltage processes in order to interface 1.8V ASICs to 2.5V (3.3V) environments. All IO25lib (IO33lib) cells are slew rate controlled. Advantage has been taken of the 1.8V to 2.5V (3.3V) level shifter (slow by construction) to reduce the slew rate without reducing speed. Table 11. IO25lib/IO33lib Pads 3V Interface Pad Name pc25b0x/pc33b0x pc25d00/pc33d00 pc25o0x/pc33o0x pc25t0x/pc33t0x 3-State I/O Output Only 3-State Output Only Input Only Drive Strength 2 mA, 4 mA, 8 mA, 16 mA Pad Sites Used 1 1 2 mA, 4 mA, 8 mA, 16 mA 1 1 • • • • 2 mA, 4 mA, 8 mA, 16 mA Note: All 3-state I/Os, 3-state output only and input pads are also available with pull-up and pull-down device. Table 12. IO25lib/IO33lib Power Pads Power Bus Connections Cell Name pv25e00/pv33e00 pv25i00/pv33i00 pv25i25/pv33i25 pv25e33/pv33e33 pv25ecrn/pv33ecrn vssi mixvss vddi mixvdd Pad Sites Used 1 1 • • • • • • 1 1 2 6 ATC20 Summary 1361BS–CBIC–09/02 ATC20 Summary Oscillator Cell Library Osc18lib The Atmel Oscillator Library provides stable clock sources. It comprises five oscillators and one power-on-reset. The Atmel two-pad oscillators are designed with the Pierce three-point oscillator structure. For the 32.768 kHz oscillator, the load capacitance must be between 6 pF and 12.5 pF. For high-frequency oscillators, the load capacitance must be between 15 pF and 20 pF. External capacitors must be added in order to obtain the correct load capacitance. Clock output is high at off state (onosc = 0). The oscillators provide a bypass mode (onosc = 0), clock = not (xin). Table 13 gives the available Osc18lib cells and their major characteristics. Table 13. Oscillator and POR Cells Cell Name OSC18f33K OSC18f9M OSC18f16M OSC18f27M OSC33KLP POR18 Description Low frequency, optimized for 32.786 kHz crystal 4 - 9 MHz crystal oscillator 8 - 16 MHz crystal oscillator 10 - 27 MHz crystal oscillator 32.786 Hz uPower crystal oscillator. Low frequency, optimized for 32.786 kHz crystal Static and dynamic reset with internal hysterisis Basic Analog Cell Library ANA18lib, ANA25lib, ANA33lib The Atmel CBIC analog library makes the following parts available: • Multiplexer modules – – • • Multiplexers to minimize cross-talk (for use with high-impedance nodes). Multiplexers to minimize ON resistance. Analog input and output cells Analog power and ground cells A special set of basic analog I/O cells, ANA25lib (ANA33lib), is available for interfacing with external 2.5V (3.3V) devices. General-purpose Analog Cell Library GPlib The General-purpose Analog Cell Library (GPlib) is composed of cells performing various analog functions. Currently available are regulators, power management cells, op amps, comparators, ADCs and DACs. All these cells are on request only. Additional high-performance, complex analog cells can be developed according to specific customer requirements. 7 1361BS–CBIC–09/02 Atmel Compiled Megacell Library The Atmel Compiled Megacell Library enables compilation of megacells for the functions Synchronous RAM, Asynchronous RAM, Asynchronous Dual-port RAM and Synchronous ROM, according to the user’s precise requirements. The Atmel megacells can be instanced as often as required in designs and can be used in parallel with cells from all other Atmel CBIC libraries. All the megacell representations required for schematic entry, simulation, place and route, layout generation, and verification are created automatically. Compiled Synchronous RAM Megacells The Atmel Synchronous RAM compiler has bidirectional or separate I/O ports, and can be configured in multi-bank form, with a maximum of four banks. The range of permitted Synchronous RAM megacell configurations is as follows: Number of bits Number of words Word Size 128, .. 144K bits 32, .. 8K 4, .. 36 bits The following table shows the range of performances for particular Synchronous RAM configurations under typical conditions. Configuration Density (Kbits/mm ) Frequency (MHz) Dynamic Power (mW/MHz) 2 1K x 8 (8K bits) 51 237 0.17 2K x 16 (32K bits) 58 157 0.36 4K x 32 (128K bits) 62 112 0.73 Compiled Asynchronous RAM Megacells The Atmel Asynchronous RAM compiler has bidirectional or separate I/O ports, and can be configured in multi-bank form, with a maximum of four banks. The range of permitted Asynchronous RAM megacell configurations is as follows: Number of bits Number of words Word Size 128, .. 128K bits 16, .. 4K 8, .. 36 bits The following table shows the range of performances for particular Asynchronous RAM configurations under typical conditions. Configuration Density (Kbits/mm ) Frequency (MHz) Dynamic Power (mW/MHz) 2 1K x 8 (8K bits) 40 270 0.24 2K x 16 (32K bits) 40 268 0.38 4K x 32 (128K bits) 50 185 0.63 8 ATC20 Summary 1361BS–CBIC–09/02 ATC20 Summary Compiled Asynchronous Dual-port RAM Megacells The Atmel Asynchronous Dual-port RAM has bidirectional or separate I/O ports, and can be configured in multi-bank form, with a maximum of four banks. The range of permitted Asynchronous Dual-port RAM Megacell configurations is as follows: Number of bits Number of words(1) Word Size(1) 128, .. 16K 64, .. 2K 2, .. 36 bits Note: 1. Must be the same for both ports. The following table shows the range of performances for particular Asynchronous Dualport RAM configurations under typical conditions. Configuration Density (Kbits/mm ) Frequency (MHz) Dynamic Power (mW/MHz) 2 128 x 8 (1K bits) 22 305 0.09 256 x 16 (4K bits) 32 274 0.31 512 x 32 (16K bits) 36 248 0.41 Compiled Synchronous ROM Megacells The Atmel Synchronous ROM is diffusion programmable and is applicable in low power solutions. It can be configured in multi-bank form, with a maximum of four banks. The range of permitted Synchronous ROM Megacell configurations is as follows: Number of bits Number of words Word Size 256, .. 512K 64, .. 8K 4, .. 72 bits The following table shows the range of performances for particular Synchronous ROM configurations under typical conditions. Configuration Density (Kbits/mm ) Frequency (MHz) Dynamic Power (mW/MHz) 2 2K x 8 (16K bits) 400 190 0.13 4K x 16 (64K bits) 568 170 0.26 8K x 32 (256K bits) 669 120 0.54 9 1361BS–CBIC–09/02 Document Details Title Literature Number ATC20 Summary 1361S Revision History Version A Version B Publication Date: Mar-00 Publication Date: 06-Sep-02 Adds description of Oscillator Cell Library, Basic Analog Cell Library, General-purpose Analog Cell Library. Page: 7 10 ATC20 Summary 1361BS–CBIC–09/02 Atmel Headquarters Corporate Headquarters 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 487-2600 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany TEL (49) 71-31-67-0 FAX (49) 71-31-67-2340 1150 East Cheyenne Mtn. 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