ATF1504ASZ-20JC84

Features • High Density, High Performance Electrically Erasable Complex Programmable Logic Device – 64 Macrocells – 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell – 44, 68, 84, 100 pins – 7 ns Maximum Pin-to-Pin Delay – Registered Operation Up To 100 MHz – Enhanced Routing Resources In-System Programmability (ISP) via JTAG Flexible Logic Macrocell – D/T/Latch Configurable Flip Flops – Global and Individual Register Control Signals – Global and Individual Output Enable – Programmable Output Slew Rate – Programmable Output Open Collector Option – Maximum Logic utilization by burying a register within a COM output Advanced Power Management Features – Automatic 100 µA Stand-By for “Z” Version – Pin-Controlled 4 mA Stand-By Mode (Typical) – Programmable Pin-Keeper Inputs and I/Os – Reduced-Power Feature Per Macrocell Available in Commercial and Industrial Temperature Ranges Available in 44-, 68-, and 84-pin PLCC; 44- and 100-pin TQFP; and 100-pin PQFP Advanced EE Technology – 100% Tested – Completely Reprogrammable – 100 Program/Erase Cycles – 20 Year Data Retention – 2000V ESD Protection – 200 mA Latch-Up Immunity JTAG Boundary-Scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported PCI-compliant 3.3 or 5.0V I/O pins Security Fuse Feature • • HighPerformance EE CPLD ATF1504AS ATF1504ASZ • • • • • • • • Enhanced Features • • • • • • • • • • • Improved Connectivity (Additional Feedback Routing, Alternate Input Routing) Output Enable Product Terms D - Latch Mode Combinatorial Output with Registered Feedback within any Macrocell Three Global Clock Pins ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O Fast Registered Input from Product Term Programmable “Pin-Keeper” Option VCC Power-Up Reset Option Pull-Up Option on JTAG Pins TMS and TDI Advanced Power Management Features – Edge Controlled Power Down “L” – Individual Macrocell Power Option – Disable ITD on Global Clocks, Inputs and I/O Description The ATF1504AS is a high performance, high density Complex Programmable Logic Device (CPLD) which utilizes Atmel’s proven electrically erasable memory technology. With 64 logic macrocells and up to 68 inputs, it easily integrates logic from several (continued) Rev. 0950D–07/98 1 44-Lead TQFP Top View I/O I/O I/O VCC I/OE2/GCK2 GCLR/I I/OE1 GCK1/I GND GCK3 I/O 44-Lead PLCC Top View I/O I/O I/O VCC GCK2/OE2/I GCLR/I OE1/I GCK1/I GND I/O/GCLK3 I/O 33 32 31 30 29 28 27 26 25 24 23 I/O I/O/TDO I/O I/O VCC I/O I/O I/O/TCK I/O GND I/O I/O VCC I/O/TDI I/O I/O I/O I/O GND I/O/PD1 I/O I/O I/O/TMS I/O I/O VCC I/O I/O I/O I/O I/O GND 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 I/O I/O I/O I/O GND I/O I/O I/O VCC I/OE2/GCK2 I/GCLR I/OE1 I/GCK1 GND I/GCK3 I/O I/O VCC 1/O I/O I/O I/O I/O GND I/O/TDO I/O I/O I/O VCC I/O I/O I/O/TCK I/O GND I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC I/O I/O I/O GND VCC I/O I/O I/O/PD2 GND I/O I/O I/O I/O I/O VCC 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 I/O I/O GND I/O/TDO I/O I/O I/O I/O VCC I/O I/O I/O I/O/TCK I/O I/O GND I/O I/O I/O I/O I/O 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 I/O I/O I/O I/O GND VCC I/O PD2/I/O I/O I/O I/O 18 19 20 21 22 23 24 25 26 27 28 TDI/I/O I/O I/O GND PD1/I/O I/O I/O/TMS I/O VCC I/O I/O 7 8 9 10 11 12 13 14 15 16 17 6 5 4 3 2 1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 I/O I/O/TDO I/O I/O VCC I/O I/O I/O/TCK I/O GND I/O I/O/TDI I/O I/O GND PD1/I/O I/O TMS/I/O I/O VCC I/O I/O 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 I/O I/O I/O I/O GND VCC I/O I/O/PD2 I/O I/O I/O 44 43 42 41 40 39 38 37 36 35 34 68-Lead PLCC Top View I/O I/O I/O GND I/O I/O VCC I/OE2/GCK2 GCLR/I OE1/I I/GCK1 GND I/GCK3 I/O VCC I/O/TCK I/O 84-Lead PLCC Top View 2 I/O I/O I/O I/O VCC I/O I/O GND VCC I/O I/O/PD2 GND I/O I/O I/O I/O VCC 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 I/O VCC I/O/TD1 I/O I/O I/O GND I/O/PD1 I/O I/O/TMS I/O VCC I/O I/O I/O I/O GND 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 ATF1504AS(Z) ATF1504AS(Z) 100-Lead PQFP Top View I/O I/O I/O GND I/O I/O I/O VCCINT INPUT/OE2/GCLK2 INPUT/GCLR INPUT/OE1 INPUT/GCLK1 GND I/O/GCLK3 I/O I/O VCCIO I/O I/O I/O 100-Lead TQFP Top View I/O I/O I/O I/O I/O GND I/O I/O I/O VCCINT INPUT/OE2/GCLK2 INPUT/GCLR INPUT/OE1 INPUT/GCLK1 GND I/O/GCLK3 I/O I/O VCCIO I/O I/O I/O NC NC I/O NC NC VCCIO I/O/TDI NC I/O NC I/O I/O I/O GND I/O/PD1 I/O I/O I/O/TMS I/O I/O VCCIO I/O I/O I/O NC I/O NC I/O 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 NC NC I/O I/O VCCIO I/O/TDI NC I/O NC I/O I/O I/O GND I/O/PD1 I/O I/O I/O/TMS I/O I/O VCCIO I/O I/O I/O NC I/O NC I/O GND NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 NC NC I/O I/O GND I/O/TDO NC I/O NC I/O I/O I/O VCCIO I/O I/O I/O I/O/TCK I/O I/O GND I/O I/O I/O NC I/O NC I/O VCCIO NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 I/O GND I/O/TDO NC I/O NC I/O I/O I/O VCCIO I/O I/O I/O I/O/TCK I/O I/O GND I/O I/O I/O NC I/O NC I/O VCCIO I/O I/O I/O I/O I/O VCCIO I/O I/O I/O GND VCCINT I/O I/O I/O/PD2 GND I/O I/O I/O I/O I/O GND NC NC I/O I/O I/O I/O I/O VCCIO I/O I/O I/O GND VCCINT I/O I/O I/O/PD2 GND I/O I/O I/O I/O I/O NC NC 3 TTL, SSI, MSI, LSI and classic PLDs. The ATF1504AS’s enhanced routing switch matrices increase usable gate count, and the odds of successful pin-locked design modifications. The ATF1504AS has up to 68 bi-directional I/O pins and 4 dedicated input pins, depending on the type of device package selected. Each dedicated pin can also serve as a global control signal; register clock, register reset or output enable. Each of these control signals can be selected for use individually within each macrocell. Each of the 64 macrocells generates a buried feedback, which goes to the global bus. Each input and I/O pin also feeds into the global bus. The switch matrix in each logic block then selects 40 individual signals from the global bus. Each macrocell also generates a foldback logic term, which goes to a regional bus. Cascade logic between macrocells in the ATF1504AS allows fast, efficient generation of complex logic functions. The ATF1504AS contains four such logic chains, each capable of creating sum term logic with a fan in of up to 40 product terms. The ATF1504AS macrocell shown in Figure 1, is flexible enough to support highly complex logic functions operating at high speed. The macrocell consists of five sections: product terms and product term select multiplexer; OR/XOR/CASCADE logic; a flip-flop; output select and enable; and logic array inputs. Block Diagram Unused product terms are automatically disabled by the compiler to decrease power consumption. A Security Fuse, when programmed, protects the contents of the ATF1504AS. Two bytes (16-bits) of User Signature are accessible to the user for purposes such as storing project name, part number, revision or date. The User Signature is accessible regardless of the state of the Security Fuse. The ATF1504AS device is an In-System Programmable (ISP) device. It uses the industry standard 4-pin JTAG interface (IEEE Std. 1149.1), and is fully compliant with JTAG’s Boundary Scan Description Language (BSDL). ISP allows the device to be programmed without removing it from the printed circuit board. In addition to simplifying the manufacturing flow, ISP also allows design modifications to be made in the field via software. 4 ATF1504ASZ ATF1504ASZ Product Terms and Select MUX Each ATF1504AS macrocell has five product terms. Each product term receives as its inputs all signals from both the global bus and regional bus. The product term select multiplexer (PTMUX) allocates the five product terms as needed to the macrocell logic gates and control signals. The PTMUX programming is determined by the design compiler, which selects the optimum macrocell configuration. OR/XOR/CASCADE Logic The ATF1504AS’s logic structure is designed to efficiently support all types of logic. Within a single macrocell, all the product terms can be routed to the OR gate, creating a 5input AND/OR sum term. With the addition of the CASIN from neighboring macrocells, this can be expanded to as many as 40 product terms with a very small additional delay. The macrocell’s XOR gate allows efficient implementation of compare and arithmetic functions. One input to the XOR comes from the OR sum term. The other XOR input can be a product term or a fixed high or low level. For combinatorial outputs, the fixed level input allows polarity selection. For registered functions, the fixed levels allow DeMorgan minimization of product terms. The XOR gate is also used to emulate T- and JK-type flip-flops. Flip Flop The ATF1504AS’s flip flop has very flexible data and control functions. The data input can come from either the XOR gate, from a separate product term or directly from the I/O pin. Selecting the separate product term allows creation of a buried registered feedback within a combinatorial output macrocell. (This feature is automatically implemented by the fitter software). In addition to D, T, JK and SR operation, the flip flop can also be configured as a flow-through latch. In this mode, data passes through when the clock is high and is latched when the clock is low. The clock itself can either be one of the Global CLK Signal GCK[0 : 2] or an individual product term. The flip flop changes state on the clock’s rising edge. When the GCK signal is used as the clock, one of the macrocell product terms can be selected as a clock enable. When the clock enable function is active and the enable signal (product term) is low, all clock edges are ignored. The flip flop’s asynchronous reset signal (AR) can be either the Global Clear (GCLEAR), a product term, or always off. AR can also be a logic OR of GCLEAR with a product term. The asynchronous preset (AP) can be a product term or always off. Output Select and Enable The ATF1504AS macrocell output can be selected as registered or combinatorial. The buried feedback signal can be either combinatorial or registered signal regardless of whether the output is combinatorial or registered. The output enable multiplexer (MOE) controls the output enable signals. Any buffer can be permanently enabled for simple output operation. Buffers can also be permanently disabled to allow use of the pin as an input. In this configuration all the macrocell resources are still available, including the buried feedback, expander and CASCADE logic. The output enable for each macrocell can be selected as either of the two dedicated OE input pins as an I/O pin configured as an input, or as an individual product term. Global Bus/Switch Matrix The global bus contains all input and I/O pin signals as well as the buried feedback signal from all 64 macrocells. The Switch Matrix in each Logic Block receives as its inputs all signals from the global bus. Under software control, up to 40 of these signals can be selected as inputs to the Logic Block. Foldback Bus Each macrocell also generates a foldback product term. This signal goes to the regional bus and is available to 4 macrocells. The foldback is an inverse polarity of one of the macrocell’s product terms. The 4 foldback terms in each region allows generation of high fan-in sum terms (up to 9 product terms) with a small additional delay. 5 Figure 1. ATF1504AS Macrocell Programmable Pin-Keeper Option for Inputs and I/Os The ATF1504AS offers the option of programming all input and I/O pins so that pin keeper circuits can be utilized. When any pin is driven high or low and then subsequently left floating, it will stay at that previous high or low level. This circuitry prevents unused input and I/O lines from floating to intermediate voltage levels, which cause unnecessary power consumption and system noise. The keeper circuits eliminate the need for external pull-up resistors and eliminate their DC power consumption. by mode when no logic transitions are occurring. This not only reduces power consumption during inactive periods, but also provides a proportional power savings for most applications running at system speeds below 50 MHz. This feature may be selected as a design option. I/O Diagram Input Diagram Speed/Power Management The ATF1504AS has several built-in speed and power management features. The ATF1504AS contains circuitry that automatically puts the device into a low power stand6 To further reduce power, each ATF1504AS macrocell has a Reduced Power bit feature. This feature allows individual macrocells to be configured for maximum power savings. This feature may be selected as a design option. All ATF1504ASs also have an optional power down mode. In this mode, current drops to below 10 mA. When the power down option is selected, either PD1 or PD2 pins (or both) can be used to power down the part. The power down option is selected in the design source file. When enabled, ATF1504ASZ ATF1504ASZ the device goes into power down when either PD1 or PD2 is high. In the power down mode, all internal logic signals are latched and held, as are any enabled outputs. All pin transitions are ignored until the PD pin is brought low. When the power down feature is enabled, the PD1 or PD2 pin cannot be used as a logic input or output. However, the pin’s macrocell may still be used to generate buried foldback and cascade logic signals. All Power-Down AC Characteristic parameters are computed from external input or I/O pins, with Reduced Power Bit turned on. For macrocells in reduced-power mode (Reduced power bit turned on), the reduced power adder, tRPA, must be added to the AC parameters, which include the data paths tLAD, tLAC, tIC, tACL, tACH and tSEXP. The ATF1504AS macrocell also has an option whereby the power can be reduced on a per macrocell basis. By enabling this power down option, macrocells that are not used in an application can be turned down thereby reducing the overall power consumption of the device. Each output also has individual slew rate control. This may be used to reduce system noise by slowing down outputs that do not need to operate at maximum speed. Outputs default to slow switching, and may be specified as fast switching in the design file. 1. The VCC rise must be monotonic, 2. After reset occurs, all input and feedback setup times must be met before driving the clock pinhigh, and, 3. The clock must remain stable during TD. Security Fuse Usage A single fuse is provided to prevent unauthorized copying of the ATF1504AS fuse patterns. Once programmed, fuse verify is inhibited. However, the 16-bit User Signature remains accessible. Programming ATF1504AS devices are In-System Programmable (ISP) devices utilizing the 4-pin JTAG protocol. This capability eliminates package handling normally required for program and facilitates rapid design iterations and field changes. Atmel provides ISP hardware and software to allow programming of the ATF1504AS via the PC. ISP is performed by using either a download cable, or a comparable board tester or a simple microprocessor interface. To facilitate ISP programming by the Automated Test Equipment (ATE) vendors. Serial Vector Format (SVF) files can be created by Atmel provided Software utilities. ATF1504AS devices can also be programmed using standard 3rd party programmers. With 3rd party programmer the JTAG ISP port can be disabled thereby allowing 4 additional I/O pins to be used for logic. Contact your local Atmel representatives or Atmel PLD applications for details. Design Software Support ATF1504AS designs are supported by several third party tools. Automated fitters allow logic synthesis using a variety of high level description languages and formats. Power Up Reset The ATF1504AS has a power-up reset option at two different voltage trip levels when the device is being powered down. Within the fitter, or during a conversion, if the “power-reset” option is turned “on” (which is the default option), the trip levels during power up or power down is at 2.8V. The user can change this default option from “on” to “off” (within the fitter or specify it as a switch during conversion). When this is done, the voltage trip level during power-down changes from 2.8V to 0.7V. This is to ensure a robust operating environment. The registers in the ATF1504AS are designed to reset during power up. At a point delayed slightly from VCC crossing Vrst, all registers will be reset to the low state. The output state will depend on the polarity of the buffer. This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the uncertainty of how VCC actually rises in the system, the following conditions are required: ISP Programming Protection The ATF1504AS has a special feature which locks the device and prevents the inputs and I/O from driving if the programming process is interrupted due to any reason. The inputs and I/O default to high-Z state during such a condition. In addition the pin keeper option preserves the former state during device programming. All ATF1504AS devices are initially shipped in the erased state thereby making them ready to use for ISP. Note: For more information refer to the “Designing for In-System Programmability with Atmel CPLDs” application note. 7 DC and AC Operating Conditions Commercial Operating Temperature (Case) VCCINT or VCCIO (5V) Power Supply VCCIO (3.3V) Power Supply 0 °C - 70°C 5V ± 5% 3.0V - 3.6V Industrial -40°C - 85°C 5V ± 10% 3.0V - 3.6V DC Characteristics Symbol IIL IIH IOZ Parameter Input or I/O Low Leakage Current Input or I/O High Leakage Current Tri-State Output Off-State Current VO = VCC or GND Com. Std Mode ICC1 Power Supply Current, Stand-by VCC = Max VIN = 0, VCC “Z” Mode Ind. ICC2 IOS VCCIO VCCIO VIL VIH VOL VOH Note: Power Supply Current, Power Down Mode Output Short Circuit Current Supply Voltage Supply Voltage Input Low Voltage Input High Voltage VIN = VIH or VIL VCCIO = MIN, IOL = 12 mA VIN = VIH or VIL VCCIO = MIN, IOH = -4.0 mA Com. Ind. 2.4 V VCC = Max VIN = 0, VCC VOUT = 0.5V Com. 5.0V Device Output Ind. 3.3V Device Output 4.5 3.0 -0.3 2.0 5.5 3.6 0.8 VCCINT + 0.3 0.45 V V V V V 4.75 “PD” Mode 4 100 10 -150 5.25 Ind. Com. 150 100 mA µA µA mA mA V -40 120 Condition VIN = VCC Min Typ -2 2 Max -10 10 40 µA mA Units µA Output Low Voltage Output High Voltage Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec. Pin Capacitance Typ CIN CI/O Note: 8 8 Max 10 10 Units pF pF Conditions VIN = 0V; f = 1.0 MHz VOUT = 0V; f = 1.0 MHz Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. The OGI pin (high-voltage pin during programming) has a maximum capacitance of 12 pf. 8 ATF1504ASZ ATF1504AS(Z) Absolute Maximum Ratings* Temperature Under Bias .................................. -40°C to +85°C Storage Temperature ..................................... -65°C to +150°C Voltage on Any Pin with Respect to Ground .........................................-2.0V to +7.0V(1) Voltage on Input Pins with Respect to Ground During Programming.....................................-2.0V to +14.0V(1) Note: Programming Voltage with Respect to Ground .......................................-2.0V to +14.0V(1) 1. *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Minimum voltage is -0.6V DC, which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is VCC + 0.75V DC, which may overshoot to 7.0V for pulses of less than 20 ns. AC Characteristics -7 Symbol tPD1 tPD2 tSU tH tFSU tFH tCOP tCH tCL tASU tAH tACOP tACH tACL tCNT fCNT tACNT fACNT Parameter Input or Feedback to Non-Registered Output I/O Input or Feedback to Non-Registered Feedback Global Clock Setup Time Global Clock Hold Time Global Clock Setup Time of Fast Input Global Clock Hold Time of Fast Input Global Clock to Output Delay Global Clock High Time Global Clock Low Time Array Clock Setup Time Array Clock Hold Time Array Clock Output Delay Array Clock High Time Array Clock Low Time Minimum Clock Global Period Maximum Internal Global Clock Frequency Minimum Array Clock Period Maximum Internal Array Clock Frequency 125 125 8 100 3 3 8 100 10 76.9 3 3 3 2 7.5 4 4 10 76.9 13 66 6 0 3 0.5 4.5 4 4 3 3 10 6 6 13 66 17 50 Min Max 7.5 7 7 0 3 0.5 5 5 5 4 4 15 8 8 17 50 22 Min -10 Max 10 9 Min 3 3 11 0 3 1.0 8 6 6 4 5 20 10 10 22 -15 Max 15 12 16 0 3 1.5 10 7 7 5 6 25 Min -20 Max 20 16 20 0 5 2 13 Min -25 Max 25 25 Units ns ns ns ns ns MHz ns ns ns ns ns ns ns ns ns MHz ns MHz (continued) = Preliminary Information 9 AC Characteristics (Continued) -7 Symbol FMAX tIN tIO tFIN tSEXP tPEXP tLAD tLAC tIOE tOD1 Parameter Maximum Clock Frequency Input Pad and Buffer Delay I/O Input Pad and Buffer Delay Fast Input Delay Foldback Term Delay Cascade Logic Delay Logic Array Delay Logic Control Delay Internal Output Enable Delay Output Buffer and Pad Delay (Slow slew rate = OFF; VCCIO = 5V; CL = 35 pF) Output Buffer and Pad Delay (Slow slew rate = OFF; VCCIO = 3.3V; CL = 35 pF) Output Buffer and Pad Delay (Slow slew rate = ON; VCCIO = 5V or 3.3V; CL = 35 pF) See ordering information for valid part numbers. Min 166.7 0.5 0.5 1 4 0.8 3 3 2 2 Max Min 125 0.5 0.5 1 5 0.8 5 5 2 1.5 -10 Max Min 100 2 2 2 8 1 6 6 3 4 -15 Max Min 83.3 2 2 2 10 1 7 7 3 5 -20 Max Min 60 2 2 2 12 1.2 8 8 4 6 -25 Max Units MHz ns ns ns ns ns ns ns ns ns tOD2 2.5 2.0 5 6 7 ns tOD3 Note: 5 5.5 8 10 10 ns (continued) = Preliminary Information Timing Model 10 ATF1504ASZ ATF1504ASZ AC Characteristics (Continued) -7 Symbol tZX1 Parameter Output Buffer Enable Delay (Slow slew rate = OFF; VCCIO = 5.0V; CL = 35 pF) Output Buffer Enable Delay (Slow slew rate = OFF; VCCIO = 3.3V; CL = 35 pF) Output Buffer Enable Delay (Slow slew rate = ON; VCCIO = 5.0V/3.3V; CL = 35 pF) Output Buffer Disable Delay (CL = 5 pF) Register Setup Time Register Hold Time Register Setup Time of Fast Input Register Hold Time of Fast Input Register Delay Combinatorial Delay Array Clock Delay Register Enable Time Global Control Delay Register Preset Time Register Clear Time Switch Matrix Delay Reduced-Power Adder (2) -10 Max 4.0 Min Max 5.0 Min -15 Max 7 Min -20 Max 9 Min -25 Max 10 Units ns Min tZX2 4.5 5.5 7 9 10 ns tZX3 9 9 10 11 12 ns tXZ tSU tH tFSU tFH tRD tCOMB tIC tEN tGLOB tPRE tCLR tUIM tRPA Notes: 4 3 2 3 0.5 1 1 3 3 1 2 2 1 10 3 3 3 0.5 5 4 4 2 2 2 2 5 5 1 3 3 1 11 6 5 5 2 2 1 1 6 6 1 4 4 2 13 7 6 6 3 2.5 2 2 7 7 1 5 5 2 14 8 ns ns ns ns ns 2 2 8 8 1 6 6 2 15 ns ns ns ns ns ns ns ns ns 1. See ordering information for valid part numbers. 2. The tRPA parameter must be added to the tLAD, tLAC,tTIC, tACL, and tSEXP parameters for macrocells running in the reducedpower mode. = Preliminary Information Input Test Waveforms and Measurement Levels Output AC Test Loads (3.0V)* (703 )* tR, tF = 1.5 ns typical Note: (8060 )* *Numbers in parenthesis refer to 3.0V operating conditions (preliminary). 11 Power Down Mode The ATF1504AS includes an optional pin controlled power down feature.When this mode is enabled, the PD pin acts as the power down pin. When the PD pin is high, the device supply current is reduced to less than 3 mA. During power down, all output data and internal logic states are latched and held. Therefore, all registered and combinatorial output data remain valid. Any outputs which were in a Hi-Z state at the onset will remain at Hi-Z. During power down, all input (1)(2) signals except the power down pin are blocked. Input and I/O hold latches remain active to insure that pins do not float to indeterminate levels, further reducing system power. The power down pin feature is enabled in the logic design file. Designs using the power down pin may not use the PD pin logic array input. However, all other PD pin macrocell resources may still be used, including the buried feedback and foldback product term array inputs. Power Down AC Characteristics Symbol tIVDH tGVDH tCVDH tDHIX tDHGX tDHCX tDLIV tDLGV tDLCV tDLOV Notes: Parameter Valid I, I/O Before PD High Valid OE (2) -7 Min 7 7 7 12 12 12 1 1 1 1 Max Min 10 10 10 -10 Max Min 15 15 15 15 15 15 1 1 1 1 -15 Max Min 20 20 20 25 25 25 1 1 1 1 -20 Max Min 25 25 25 30 30 30 1 1 1 1 -25 Max Units ns ns ns 35 35 35 1 1 1 1 ns ns ns µs µs µs µs Before PD High (2) Valid Clock Before PD High I, I/O Don’t Care After PD High OE (2) Don’t Care After PD High (2) Clock Don’t Care After PD High PD Low to Valid I, I/O PD Low to Valid OE (Pin or Term) PD Low to Valid Clock (Pin or Term) PD Low to Valid Output 1. For slow slew outputs, add tSSO. 2. Pin or Product Term. = Preliminary Information JTAG-BST/ISP Overview The JTAG boundary-scan testing is controlled by the Test Access Port (TAP) controller in the ATF1504AS. The boundary-scan technique involves the inclusion of a shiftregister stage (contained in a boundary-scan cell) adjacent to each component so that signals at component boundaries can be controlled and observed using scan testing principles. Each input pin and I/O pin has its own boundary scan cell (BSC) in order to support boundary scan testing. The ATF1504AS does not currently include a Test Reset (TRST) input pin because the TAP controller is automatically reset at power up. The five JTAG modes supported i nc l u d e: S A MP L E /P R E LO AD , E X T E S T , B Y P A S S , IDCODE and HIGHZ. The ATF1504AS’s ISP can be fully described using JTAG’s BSDL as described in IEEE Standard 1149.1b. This allows ATF1504AS programming to be described and implemented using any one of the 3rd party development tools supporting this standard. The ATF1504AS has the option of using four JTAG-standard I/O pins for boundary scan testing (BST) and in-system programming (ISP) purposes. The ATF1504AS is programmable through the four JTAG pins using the IEEE 12 standard JTAG programming protocol established by IEEE Standard 1149.1 using 5V TTL-level programming signals from the ISP interface for in-system programming. The JTAG feature is a programmable option. If JTAG (BST or ISP) is not needed, then the four JTAG control pins are available as I/O pins. JTAG Boundary Scan Cell (BSC) Testing The ATF1504AS contains up to 68 I/O pins and 4 input pins, depending on the device type and package type selected. Each input pin and I/O pin has its own boundary scan cell (BSC) in order to support boundary scan testing as described in detail by IEEE Standard 1149.1. Typical BSC consists of three capture registers or scan registers and up to two update registers. There are two types of BSCs, one for input or I/O pin, and one for the macrocells. The BSCs in the device are chained together through the capture registers. Input to the capture register chain is fed in from the TDI pin while the output is directed to the TDO pin. Capture registers are used to capture active device data signals, to shift data in and out of the device and to ATF1504ASZ ATF1504ASZ load data into the update registers. Control signals are generated internally by the JTAG TAP controller. The BSC configuration for the input and I/O pins and macrocells are shown below. BSC Configuration for Macrocell Pin BSC TDO BSC Configuration for Input and I/O Pins (except JTAG TAP Pins) Pin 0 1 DQ Capture DR TDI Clock Shift TDO Note: The ATF1504AS has pull-up option on TMS and TDI pins. This feature is selected as a design option. OEJ 0 0 1 1 DQ DQ OUTJ 0 0 1 1 DQ DQ Pin Capture DR TDI Shift Update DR Mode Clock Macrocell BSC 13 PCI Compliance The ATF1504AS also supports the growing need in the industry to support the new Peripheral Component Interconnect (PCI) interface standard in PCI-based designs and specifications. The PCI interface calls for high current drivers which are much larger than the traditional TTL drivers. In general, PLDs and FPGAs parallel outputs to support the high current load required by the PCI interface. The ATF1504AS allows this without contributing to system noise while delivering low output to output skew. Having a programmable high drive option is also possible without increasing output delay or pin capacitance. The PCI electrical characteristics appear on the next page. PCI Voltage-to-Current Curves for +5V Signaling in Pull-Down Mode Pull Down VCC Voltage AC drive point 2.2 DC drive point 0.55 PCI Voltage-to-Current Curves for +5V Signaling in Pull-Up Mode Pull Up Test Point 3.6 95 Current (mA) 380 VCC Voltage Test Point 2.4 1.4 DC drive point AC drive point -2 -44 Current (mA) -178 14 ATF1504ASZ ATF1504AS(Z) PCI DC Characteristics (Preliminary) Symbol VCC VIH VIL IIH IIL VOH VOL CIN CCLK CIDSEL LPIN Note: Parameter Supply Voltage Input High Voltage Input Low Voltage Input High Leakage Current Input Low Leakage Current Output High Voltage Output Low Voltage Input Pin Capacitance CLK Pin Capacitance IDSEL Pin Capacitance Pin Inductance Leakage Current is with Pin-Keeper off. VIN = 2.7V VIN = 0.5V IOUT = -2 mA IOUT = 3 mA, 6 mA 2.4 0.55 10 12 8 20 Conditions Min 4.75 2.0 -0.5 Max 5.25 VCC + 0.5 0.8 70 -70 Units V V V µA µA V V pF pF pF nH PCI AC Characteristics (Preliminary) Symbol IOH(AC) Parameter Switching Current High Conditions 0 < VOUT ≤ 1.4 1.4 < VOUT < 2.4 3.1 < VOUT < VCC (Test High) IOL(AC) Switching Current Low VOUT = 3.1V VOUT > 2.2V 2.2 > VOUT > 0 0.1 > VOUT > 0 (Test Point) ICL SLEWR SLEWF Notes: Low Clamp Current Output Rise Slew Rate Output Fall Slew Rate VOUT = 0.71 -5 < VIN ≤ -1 0.4V to 2.4V load 2.4V to 0.4V load -25+(VIN + 1)/0.015 0.5 0.5 3 3 95 VOUT/0.023 Equation B 206 Min -44 -44+(VOUT - 1.4)/0.024 Equation A -142 Max Units mA mA mA µA mA mA mA mA mA V/ns V/ns 1. Equation A: IOH = 11.9 (VOUT - 5.25) * (VOUT + 2.45) for VCC > VOUT > 3.1V. 2. Equation B: IOL = 78.5 * VOUT * (4.4 - VOUT) for 0V < VOUT < 0.71V. 15 ATF1504AS Dedicated Pinouts Dedicated Pin INPUT/OE2/GCLK2 INPUT/GCLR INPUT/OE1 INPUT/GCLK1 I/O /GCLK3 I/O / PD (1,2) I/O / TDI (JTAG) I/O / TMS (JTAG) I/O / TCK (JTAG) I/O / TDO (JTAG) GND VCCINT VCCIO 44-Pin TQFP 40 39 38 37 35 5, 19 1 7 26 32 4, 16, 24, 36 9, 17, 29, 41 44-Pin J-Lead 2 1 44 43 41 11, 25 7 13 32 38 10, 22, 30, 42 3, 15, 23, 35 68-Pin J-Lead 2 1 68 67 65 17, 37 12 19 50 57 6, 16, 26, 34, 38, 48, 58, 66 3, 35 11, 21, 31, 43, 53, 63 84-Pin J-Lead 2 1 84 83 81 20, 46 14 23 62 71 7, 19, 32, 42, 47, 59, 72, 82 3, 43 13, 26, 38, 53, 66, 78 100-Pin PQFP 92 91 90 89 87 14, 44 6 17 64 75 13, 28, 40, 45, 61, 76, 88, 97 41, 93 5, 20, 36, 53, 68, 84 1, 2, 7, 9, 24, 26, 29, 30, 51, 52, 55, 57, 72, 74, 79, 80 68 64 100-Pin TQFP 90 89 88 87 85 12, 42 4 15 62 73 11, 26, 38, 43, 59, 74, 86, 95 39, 91 3, 18, 34, 51, 66, 82 1, 2, 5, 7, 22, 24, 27, 28, 49, 50, 53, 55, 70, 72, 77, 78 68 64 N/C - - - - # of Signal Pins # User I/O Pins 36 32 36 32 52 48 68 64 OE (1, 2) GCLR GCLK (1, 2, 3) PD (1, 2) TDI, TMS, TCK, TDO GND VCCINT VCCIO Global OE Pins Global Clear Pin Global Clock Pins Power down pins JTAG pins used for Boundary Scan Testing or In-System Programming Ground Pins VCC pins for the device (+5V - Internal) VCC pins for output drivers (for I/O pins) (+5V or 3.3V - I/Os) 16 ATF1504AS(Z) ATF1504AS(Z) ATF1504AS I/O Pinouts MC 1 2 3 4 5 6 7 8/ TDI 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32/ TMS PLC A A A/ PD1 A A A A A A A A A A A A A B B B B B B B B B B B B B B B B 44-Pin PLCC 12 11 9 8 7 6 5 4 21 20 19 18 17 16 14 13 44-Pin TQFP 6 5 3 2 1 44 43 42 15 14 13 12 11 10 8 7 68-Pin PLCC 18 17 15 14 13 12 10 9 8 7 5 4 33 32 30 29 28 27 25 24 23 22 20 19 84-Pin PLCC 22 21 20 18 17 16 15 14 12 11 10 9 8 6 5 4 41 40 39 37 36 35 34 33 31 30 29 28 27 25 24 23 100-Pin PQFP 16 15 14 12 11 10 8 6 4 3 100 99 98 96 95 94 39 38 37 35 34 33 32 31 27 25 23 22 21 19 18 17 100-Pin TQFP 14 13 12 10 9 8 6 4 2 1 98 97 96 94 93 92 37 36 35 33 32 31 30 29 25 22 21 20 19 17 16 15 MC 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48/ TCK 49 50 51 52 53 54 55 56/ TDO 57 58 59 60 61 62 63 64 PLC C C C/ PD2 C C C C C C C C C C C C C D D D D D D D D D D D D D D D D/ GCLK3 44-Pin PLCC 24 25 26 27 28 29 31 32 33 34 36 37 38 39 40 41 44-Pin TQFP 18 19 20 21 22 23 25 26 27 28 30 31 32 33 34 35 68-Pin PLCC 36 37 39 40 41 42 44 45 46 47 49 50 51 52 54 55 56 57 59 60 61 62 64 65 84-Pin PLCC 44 45 46 48 49 50 51 52 54 55 56 57 58 60 61 62 63 64 65 67 68 69 70 71 73 74 75 76 77 79 80 81 100-Pin PQFP 42 43 44 46 47 48 49 50 54 56 58 59 60 62 63 64 65 66 67 69 70 71 73 75 77 78 81 82 83 85 86 87 100-Pin TQFP 40 41 42 44 45 46 47 48 52 54 56 57 58 60 61 62 63 64 65 67 68 69 71 73 75 76 79 80 81 83 84 85 17 Ordering Information tPD (ns) 7.5 tCO1 (ns) 4.5 fMAX (MHz) 166.7 Ordering Code ATF1504AS-7 AC44 ATF1504AS-7 JC44 ATF1504AS-7 JC68 ATF1504AS-7 JC84 ATF1504AS-7 QC100 ATF1504AS-7 AC100 ATF1504AS-10 AC44 ATF1504AS-10 JC44 ATF1504AS-10 JC68 ATF1504AS-10 JC84 ATF1504AS-10 QC100 ATF1504AS-10 AC100 ATF1504AS-10 AI44 ATF1504AS-10 JI44 ATF1504AS-10 JI68 ATF1504AS-10 JI84 ATF1504AS-10 QI100 ATF1504AS-10 AI100 ATF1504AS-15 AC44 ATF1504AS-15 JC44 ATF1504AS-15 JC68 ATF1504AS-15 JC84 ATF1504AS-15 QC100 ATF1500AS-15 AC100 ATF1504AS-15 AI44 ATF1504AS-15 JI44 ATF1504AS-15 JI68 ATF1504AS-15 JI84 ATF1504AS-15 QI100 ATF1504AS-15 AI100 Package 44A 44J 68J 84J 100Q1 100A 44A 44J 68J 84J 100Q1 100A 44A 44J 68J 84J 100Q1 100A 44A 44J 68J 84J 100Q1 100A 44A 44J 68J 84J 100Q1 100A Operation Range Commercial (0°C to 70°C) 10 5 125 Commercial (0°C to 70°C) 10 5 125 Industrial (-40°C to +85°C) 15 8 100 Commercial (0°C to 70°C) 15 8 100 Industrial (-40°C to +85°C) Package Type 44A 44J 68J 84J 100Q1 100A 44-Lead, Thin Plastic Gull Wing Quad Flatpack (TQFP) 44-Lead, Plastic J-Leaded Chip Carrier OTP (PLCC) 68-Lead, Plastic J-Leaded Chip Carrier (PLCC) 84-Lead, Plastic J-Leaded Chip Carrier (PLCC) 100-Lead, Plastic Quad Flat Pack (PQFP) 100-Lead, Thin Quad Flat Pack (TQFP) 18 ATF1504AS(Z) ATF1504AS(Z) Ordering Information (Continued) tPD (ns) 20 tCO1 (ns) 12 fMAX (MHz) 83.3 Ordering Code ATF1504ASZ-20 AC44 ATF1504ASZ-20 JC44 ATF1504ASZ-20 JC68 ATF1504ASZ-20 JC84 ATF1504ASZ-20 QC100 ATF1504ASZ-20 AC100 ATF1504ASZ-25 AC44 ATF1504ASZ-25 JC84 ATF1504ASZ-25 JC68 ATF1504ASZ-25 JC84 ATF1504ASZ-25 QC100 ATF1504ASZ-25 AC100 ATF1504ASZ-25 AI44 ATF1504ASZ-25 JI84 ATF1504ASZ-25 JI68 ATF1504ASZ-25 JI84 ATF1504ASZ-25 QI100 ATF1504ASZ-25 AI100 Package 44A 44J 68J 84J 100Q1 100A 44A 44J 68J 84J 100Q1 100A 44A 44J 68J 84J 100Q1 100A Operation Range Commercial (0°C to 70°C) 25 15 70 Commercial (0°C to 70°C) 25 15 70 Industrial (-40°C to +85°C) Package Type 44A 44J 68J 84J 100Q1 100A 44-Lead, Thin Plastic Gull Wing Quad Flatpack (TQFP) 44-Lead, Plastic J-Leaded Chip Carrier OTP (PLCC) 68-Lead, Plastic J-Leaded Chip Carrier (PLCC) 84-Lead, Plastic J-Leaded Chip Carrier (PLCC) 100-Lead, Plastic Quad Flat Pack (PQFP) 100-Lead, Thin Quad Flat Pack (TQFP) 19 Packaging Information 44A, 44-Lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP) Dimensions in Millimeters and (Inches)* 44J, 44-Lead, Plastic J-Leaded Chip Carrier (PLCC) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-018 AC .045(1.14) X 45° PIN NO. 1 IDENTIFY .045(1.14) X 30° - 45° .012(.305) .008(.203) .656(16.7) SQ .650(16.5) .032(.813) .026(.660) .695(17.7) SQ .685(17.4) .630(16.0) .590(15.0) .021(.533) .013(.330) .050(1.27) TYP .500(12.7) REF SQ .043(1.09) .020(.508) .120(3.05) .090(2.29) .180(4.57) .165(4.19) .022(.559) X 45° MAX (3X) * Controlling dimension: millimeters 68J, 68-Lead, Plastic J-Leaded Chip Carrier (PLCC) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-018 AE 84J, 84-Lead, Plastic J-Leaded Chip Carrier (PLCC) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-018 AF 20 ATF1504AS(Z) ATF1504AS(Z) Packaging Information 100A, 100-Lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP) Dimensions in Millimeters and (Inches)* 100Q1, 100-Lead, Plastic Gull Wing Quad Flat Package (PQFP) Dimensions in Millimeters and (Inches) 16.25(0.640) 15.75(0.620) PIN 1 ID 0.17(0.007) 0.27(0.011) 0.56(0.022) 0.44(0.018) PIN 1 ID .687(17.44) .667(16.95) 0.026(.65) BSC .016(0.41) .009(0.22) .792(20.12) .782(19.87) .923(23.45) .904(22.95) 14.10(0.555) 13.90(0.547) 0.20(0.008) 0.10(0.004) 0-7 0.45(0.018) 0.75(0.030) 0.05(0.002) 0.15(0.006) 0.95(0.037) 1.27(0.05) .010(0.25) .004(0.10) 7 0 .556(14.12) .546(13.87) .134(3.40) MAX .041(1.03) .004(0.10) MIN .028(0.73) *Controlling dimension: millimeters 21