ATF1504SE

Features • 2nd Generation EE PROM-based Complex Programmable Logic Devices – VCCIO of 5.0V or 3.3V with 3.3V Operation being 5V Tolerant – 32 - 256 Macrocells with Enhanced Features – Pin-compatible with Industry Standard Devices – Speeds to 5 ns Maximum Pin-to-pin Delay – Registered Operation to 250 MHz Enhanced Macrocells with Logic Doubling™ Features – Bury Either Register or COM while Using the Other for Output – Dual Independent Feedback Allows Multiple Latch Functions per Macrocell – 5 Product Terms per Macrocell, expandable to 40 per Macrocell with Cascade Logic, Plus 15 more with Foldback Logic – D/T/Latch Configurable Flip-flops plus Transparent Latches – Global and/or per Macrocell Register Control Signals – Global and/or per Macrocell Output Enable – Programmable Output Slew Rate per Macrocell – Programmable Output Open Collector Option per Macrocell – Fast Registered Input from Product Term Enhanced Connectivity – Single Level Switch Matrix for Maximum Routing Options – Up to 40 Inputs per Logic Block Advanced Power Management Features – ITD (Input Transition Detection) Available Individually on Global Clocks, Inputs and I/O for µA Level Standby Current for “L” Versions – Pin-controlled 1 mA Standby Mode – Reduced-power Option per Macrocell – Automatic Power Down of Unused Macrocells – Programmable Pin-keeper Inputs and I/Os Available in Commercial and Industrial Temperature Ranges Available in All Popular Packages Including PLCC, PQFP and TQFP EE PROM Technology – 100% Tested – Completely Reprogrammable – 10,000 Program/Erase Cycles – 20 Year Data Retention – 2000V ESD Protection – 200 mA Latch-up Immunity JTAG Boundary-scan Testing Port per IEEE 1149.1-1990 and 1149.1a-1993 – Pull-up Option on JTAG Pins TMS and TDI IEEE 1532 Compatibility for Fast In-System Programmability (ISP) via JTAG PCI-compliant Security Fuse Feature • ATF15xxSE Family Datasheet ATF1502SE(L) ATF1504SE(L) ATF1508SE(L) ATF1516SE(L) Preliminary • • • • • • • • • Rev. 2401D–PLD–09/02 1 General Description Beginning with the introduction of the 100% connected ATF1500 with 32 enhanced macrocells in 1996, Atmel’s CPLD products have delivered extra IO connectivity and logic reusability. Atmel’s commitment to efficient, flexible architecture has continued with the current Atmel ATF15xxSE Family of industry-standard, pin-compatible CPLDs. Atmel’s Logic Doubling architecture consists of wider fan-in, additional routing and clock options, combined with sophisticated, proprietary device fitters, extend CPLD place and route efficiency. Atmel enhanced macrocell includes double independent buried feedback that allows designers to pack more logic (particularly shifters and latches) into a smaller CPLD or leave spare room for later revisions. The Atmel ATF15xxSE family delivers enhanced functionality and flexibility with no additional design effort and is highly cost effective. The Atmel ATF15xxSE Family includes all popular configurations and speeds. Table 1. ATF15xxSE Family Device Features Feature Usable Gates Macrocells Logic Blocks Max. # Pins Max. User I/Os TPD Grades (ns) ATF1502SE(L) 750 32 2 44 36 5, 6, 7, 10(15) ATF1504SE(L) 1500 64 4 100 68 5, 6, 7, 10(15) ATF1508SE(L) 3000 128 8 256 100 6, 7, 10(15) ATF1516SE(L) 6000 256 16 256 164 7, 10(15) The Atmel ATF15xxSE Family includes pin-compatible products in all popular packages. Table 2. ATF15xxSE Family Device Packages and Number of Signal Pins(1)(2) Packages 44-pin PLCC 44-pin TQFP 84-pin PLCC 100-pin TQFP 100-pin PQFP 160-pin PQFP 208-pin PQFP 208-pin RQFP Notes: ATF1502SE(L) 36 36 ATF1504SE(L) 36 36 68 68 68 84 84 100 164 164 ATF1508SE(L) ATF1516SE(L) 1. Contact Atmel for up-to-date information on device and package availability. 2. When the JTAG port is used for In System Programming (ISP) or Boundary-scan Testing (BST), the four associated pins become JTAG pins and are unavailable for user I/O. 2 ATF15xxSE Family 2401D–PLD–09/02 ATF15xxSE Family Functional Description The ATF15xxSE Family of 5.0 Volt supply, high-performance, high-density complex programmable logic devices (CPLDs) utilizes Atmel’s proven electrically erasable non-volatile technology. With up to 512 macrocells, they easily integrate logic from several TTL, SSI, MSI, LSI and classic PLDs. The ATF15xxSE Family’s enhanced macrocell architecture, switch matrices and routing increase usable gate count for new designs and increase odds of successful pin-locked design modifications while maintaining pin-compatibility with industry standard CPLDs. The ATF15xxSE Family devices have four dedicated input pins and depending on the type of device and package, up to 208 bi-directional I/O pins. Each dedicated input pin can also serve as a global control signal, register clock, register reset or output enable. Each of these control signals can be selected for use individually within each macrocell. Each input and I/O pin also feeds into the global bus. The macrocells are organized into groups of sixteen called logic blocks. The switch matrix in each logic block selects 40 individual signals from the global bus. Macrocells within a given logic block may share their sixteen foldback signals on a regional foldback bus. Cascade logic between macrocells in the Logic Block allows fast, efficient generation of complex logic functions. All macrocells are capable of being I/Os, however, the actual number of I/O pins depends on the device and package type. The ATF15xxSE Family members contain two, four, eight, sixteen or thirty-two such logic blocks, each capable of creating sum term logic with a fan-in of 40 inputs from the switch matrix having access to up to 80 product terms. Unused macrocells are automatically disabled by the fitter software to decrease power consumption. A security fuse, when programmed, protects the contents of the other fuses. Two bytes (16 bits) of User Signature are accessible to the user for purposes such as storing project name, part number, revision or date. The User Signature is accessible regardless of the state of the security fuse. The ATF15xxSE Family devices are in-system programmable (ISP) devices. They use the industry-standard 4-pin JTAG interface (IEEE Std. 1149.1), and are fully-compliant with JTAG’s Boundary-scan Description Language (BSDL). ISP allows the device to be programmed without removing it from the printed circuit board. In addition to simplifying the manufacturing flow, ISP also allows design modifications to be made in the field via software. Global Bus/Switch Matrix The global bus (Figure 1) contains all input and I/O pin signals as well as the buried feedback signals from all macrocells. The switch matrix in each logic block receives as its inputs all signals from the global bus. Up to 40 of these signals can be selected as inputs to the individual logic blocks by the fitter software. Atmel’s ATF15xx Family of CPLDs use a single level switch matrix signal distribution structure, where each logic block input has access to the same number of global bus inputs, maximizing the number of possible ways to route a global bus signal. This single level structure is in contrast with split switch matrix structures used by others in which routing a particular global bus input to a particular logic block input makes that signal unavailable to some other logic blocks, thus greatly limiting the available opportunities to route. The ATF15xxSE Family macrocell, shown in Figure 2, consists of five sections: product terms and product term select multiplexer, OR/XOR/CASCADE logic, foldback bus, a flip-flop and output buffer. Extra fan-in and signal routing are provided throughout. Each macrocell can generate a foldback logic term from the product term mux and a buried feedback with extra routing that go to the global bus. 3 2401D–PLD–09/02 Figure 1. ATF15xxSE Family Typical Block Diagram 6 to 16 N 6 to 16 N-1 4 ATF15xxSE Family 2401D–PLD–09/02 ATF15xxSE Family Figure 2. ATF15xxSE Family Macrocell with Enhanced Features In Red SWITCH REGIONAL MATRIX FOLDBACK OUTPUTS BUS CASIN 80 16 LOGIC FOLDBACK SWITCH MATRIX 40 PT1 PT2 1 PT3 GOE[0:5] 6 Product Term MUX 2 Q !Q AP I/O Pin D/T*/L Q I/O Pin 3 4 CK/CK/LE GCK[0:2] 3 CE SLEW RATE AR !Q OPEN COLLECTOR GOE SWITCH MATRIX GOE [0:5] 5 PT4 PT5 GCLEAR GLOBAL BUS Reduced Power Option CASOUT * T flip-flop synthesised Product Terms and Select Mux Within each macrocell are five product terms. Each product term may receive as its inputs any combination of the signals from the switch matrix or regional foldback bus. The product term select multiplexer (PTMUX) allocates the five product terms as needed to the macrocell logic gates and control signals. The PTMUX programming is determined by the fitter software, which selects the optimum macrocell configuration. Within a single macrocell, all the product terms can be routed to the OR gate, creating a 5input AND/OR sum term. With the addition of the CASIN from neighboring macrocells, this can be expanded to as many as 40 product terms with little additional delay. The macrocell’s XOR gate allows efficient implementation of compare and arithmetic functions. One input to the XOR comes from the OR sum term. The other XOR input can be a product term or a fixed high- or low-level. For combinatorial outputs, the fixed level input allows polarity selection. For registered functions, the fixed levels allow DeMorgan minimization of product terms. The XOR gate may be fed from the flip-flop output to emulate T- and JKtype flip-flops, or fed to the buried feedback to synthesize an extra latch. OR/XOR/ CASCADE Logic Foldback Bus Each macrocell can also generate a foldback product term. This signal goes to the regional bus and is available to the 16 macrocells in a given logic block. The foldback is an inverse polarity of one of the macrocell’s product terms. Although Cascade Logic is the preferred method for expanding the number of macrocell inputs to as many as 40, the 16 foldback terms in each region can also generate additional fan-in sum terms with nominal additional delay. 5 2401D–PLD–09/02 Flip-flop The ATF15xxSE Family’s flip-flop has very flexible data and control functions. The data input can come from either the XOR gate, from a separate product term or directly from the I/O pin. Selecting the separate product term allows creation of a buried registered feedback within a combinatorial output or vice-versa. (This enhanced function is automatically implemented by the fitter software). The flip-flop can be configured for D, T, JK and SR operation, and changes state on the clock’s rising edge. It can also be configured as a flow-through latch. In this mode, data passes through when the clock is high and is latched when the clock is low. When a GCK signal is used as the clock, one of the macrocell product terms can be selected as a clock enable. When the clock enable function is active and the enable signal (product term) is low, all clock edges are ignored. The flip-flop has asynchronous reset and preset. The flip-flop’s asynchronous reset signal (AR) can be either the Global Clear (GCLEAR), a product term, or always off. AR can also be a logic OR of GCLEAR with a product term. The asynchronous preset (AP) can be a product term or always off. Extra Feedback The ATF15xxSE Family macrocell output can be selected as registered or combinatorial. The extra buried feedback signal can be either combinatorial or registered signal regardless of whether the output is combinatorial or registered. (This enhanced function is automatically implemented by the fitter software) Feedback of a buried combinatorial output allows the creation of a second latch within a macrocell. The output enable multiplexer (MOE) controls the output enable signal. Each I/O can be individually configured as an input, output or for bi-directional operation. The output enable for each macrocell can be selected from the true or compliment of the two output enable pins, a subset of the I/O pins, or a subset of the I/O macrocells. This selection is automatically done by the fitter software when the I/O is configured as an input, all macrocell resources are still available, including the buried feedback, expander and cascade logic. The buffer has a fast/slow slew rate option to control EMI and an open-collector option which enables the device to provide control signals such as an interrupt that can be asserted by any of the several devices. I/O Control Programmable Pin-keeper Option for Inputs and I/Os The ATF15xxSE Family offers the option of programming all input and I/O pins with pin-keeper circuits enabled. When any pin is driven high or low and then subsequently left floating, the pin keeper circuit will hold it at that previous high or low-level. This circuitry prevents unused input and I/O lines from floating to intermediate voltage levels, which causes unnecessary power consumption and system noise. The pin-keeper circuits eliminate the need for external pull-up resistors and eliminate their DC power consumption. 6 ATF15xxSE Family 2401D–PLD–09/02 ATF15xxSE Family Input Diagram PROGRAMMABLE OPTION (PIN KEEPER) I/O Diagram PROGRAMMABLE OPTION (PIN KEEPER) Speed/Power Management Multiple Power Supplies, Power Sequencing and Hot-Socketing The ATF15xxSE Family has several speed and power management features. Because the ATF15xxSE Family can be used in a system with mixture of power supplies, it has been designed to function with the V CCINT and V CCIO power supplies applied in any sequence. Also, until the power up sequence completes, the input/output buffers are kept in a high impedance state, and so may be driven but do not drive power out. 7 2401D–PLD–09/02 Power-on Reset The ATF15xx Family devices are designed with a power-on reset, a feature critical for state machine initialization. At a point delayed slightly from VCC crossing VRST, all registers will be initialized, and the state of each output will depend on the polarity of its buffer. However, due to the asynchronous nature of reset and uncertainty of how VCC actually rises in the system, the following conditions are required: 1. The VCC rise must be monotonic, 2. After reset occurs, all input and feedback setup times must be met before driving the clock pin high, and, 3. The clock must remain stable during TD. The ATF15xx Family has two options for the hysteresis about the reset level, VRST, Small and Large. In applications where the supply voltage may drop below 4.0V, Atmel recommends that during the fitting process users configure the device with the Power-on Reset hysteresis set to Large to ensure a robust operating environment. Power Down of Unused Macrocells Input Transition Detection/ Automatic Power Down To conserve power, Atmel fitters automatically power down all unused macrocells. The ATF15xxSEL versions provide automatic power-down to µA level stand-by power (the “L” suffix indicates “Low” power) through Atmel’s patented Input Transition Detection (ITD) circuitry on Global Clocks, Inputs and I/O. These ITD circuits automatically put the device into a low-power standby mode when no logic transitions are occurring. This reduces power consumption during inactive periods, and so provides proportional power savings for most applications running at system speeds below fCRITICAL (~5 MHz). In clocked applications, where the device is operated at a frequency high enough to keep the device from going into stand-by (above fCRITICAL), the device will perform at the faster speeds given in the next faster speed column. These higher speeds can be achieved in combinatorial designs as well, as long as once activated by an initial input transition, the device continues to receive input transitions often enough to keep the device from going into standby mode again. That is, the time between input transitions is less than 1/fCRITICAL. Reduced-Power per Macrocell To further reduce power, each ATF15xxSE Family macrocell has a reduced-power bit feature. With this feature the designer can reduce power by 50% or more for logic that does not need to operate at the maximum switching speed. The reduced-power bit may be activated by changing the default OFF to ON for any or all macrocells. For macrocells in reduced-power mode (reduced-power bit turned on), the reduced- power adder, tRPA, must be added to the AC parameters, which include the data paths tLAD, tLAC, tIC, tACL, tACH and tSEXP. All power-down AC characteristic parameters are computed from external input or I/O pins, with the reducedpower bit turned on. Each output also has individual slew rate control. This may be used to reduce system noise by slowing down outputs that do not need to operate at maximum speed. Outputs default to slow switching. The slew rate option is selected in the design source file. All ATF15xx Family devices also have an optional pin-controlled power-down mode. When activated, one or both of two pins, PD1 and PD2, can act as power-down pins. The device goes into power-down when either PD1 or PD2 pins (or both) are high, and the device supply current is reduced to less than 1 mA. Also, all internal logic signals are latched and held, as are any enabled outputs. Therefore, all registered and combinatorial output data remain valid. Any outputs that were in a high-Z state at the onset will remain at high-Z. Input and I/O hold Slew Rate Control Pin Controlled Power-down 8 ATF15xxSE Family 2401D–PLD–09/02 ATF15xxSE Family latches remain active to ensure that pins do not float to indeterminate levels, further reducing system power. All pin transitions are ignored until the PD pin is brought low. When the powerdown feature is enabled for PD1 or PD2, that pin cannot be used as a logic input or output. However, the pin’s macrocell may still be used to generate buried foldback and cascade logic signals. The power-down option is selected in the design source file. Power Consumption Estimates An estimate of power consumption can be made based on typical designs and operation conditions, but because it is sensitive to these factors, power consumption must be verified with actual pattern and operation conditions. The equations given below are based on a pattern of 16-bit up/down counters in each logic block and may be used to estimate power consumption for both operating modes. 1. Pstandby = Iccstandby x Vsupply Where: Iccstandby = the standby current given for the particular device and standby mode (e.g. pin controlled Power Down) Vsupply= the power supply voltage Standby Power Active Power 2. Pactive = Pinternal + Pload = Iccinternal x Vsupply + Pload Where: Iccinternal = the internal current estimated from equation 3 below Vsupply= the power supply voltage Pload = depends on the device output load capacitance and switching frequency on each output pin. Pload and additional power savings at low frequencies using Atmel Input Transition Detection (“L” versions) can be estimated according to the methods discussed in the Atmel Application Note “Saving Power with Atmel PLDs” 3. Iccinternal = [K1 x (MCinuse – MCreducedpower )] + (K2 x MCreducedpower) + (K3 x MCinuse x fop x NS) Where: MCreducedpower = the number of macrocells operating at reduced power (from fitter report file) MCinuse= the number of macrocells in use (from fitter report file. Unused macrocells are powered down.) NS = the proportion of logic nodes switching (typically 10-20%) fop = the switching frequency K1, K2,and K3 = device constants given in the table below. Device ATF1502SE ATF1504SE ATF1508SE ATF1516SE Note: K1 (mA/MC) 0.6 0.6 0.6 0.6 K2 (mA/MC) 0.3 0.3 0.3 0.3 K3 (mA/MC · MHz) 0.015 0.015 0.015 0.015 Shaded data is preliminary and subject to change without notice. 9 2401D–PLD–09/02 Design Software Atmel ATF15xxSE Family fitters allow logic synthesis using a variety of high-level description languages and formats. ATF15xxSE Family designs are supported by Atmel specific design tools as well as by several third-party tools. Free conversion software is also offered for industry standard devices. Check the Atmel web site or contact your authorized Atmel sales representative for up-to-date design software information. ATF15xxSE Family devices can be programmed using standard third-party programmers. With third-party programmers, the JTAG ISP port can be disabled thereby allowing four additional I/O pins to be used for logic. Check the Atmel web site, contact your authorized Atmel sales representative or Atmel PLD Applications for details of third-party programmers. ATF15xxSE Family devices are in-system programmable (ISP) devices utilizing the 4-pin JTAG protocol. This capability eliminates package handling normally required for programming and facilitates rapid design iterations and field changes. Atmel provides ISP hardware and software to allow programming of the ATF15xxSE Family via the PC. ISP is performed by using either a download cable, a compatible board tester or a simple microprocessor interface. It is most common to devote the JTAG pins to ISP, but it is possible to use ISP to program the part through the JTAG pins, and set these four pins I/O pins. However, this will effectively disable further ISP and the device will need to be erased on a programmer to re-enable ISP. Contact Atmel PLD Applications by email at pld@atmel.com or call our Hotline at (408) 4364333 for details. To allow ISP programming support by the Automated Test Equipment (ATE) vendors, Serial Vector Format (SVF) files can be created by the Atmel ISP software. Conversion to other ATE tester formats is also possible. Check the Atmel web site for up-to-date programming and software support information. Programming ISP Programming Protection The ATF15xxSE Family also incorporates a protection feature that locks the device and prevents the inputs and I/O from driving if the programming process is interrupted for any reason. The inputs and I/O default to high-Z state during such a condition. In addition the pin-keeper option preserves the former state during device programming. All ATF15xxSE Family devices are initially shipped in the erased state thereby making them ready to use for ISP. For more information refer to the “Designing for In-System Programmability with Atmel CPLDs” application note. Security Fuse Usage A single fuse is provided to prevent unauthorized copying of the ATF15xxSE Family fuse patterns. Once programmed, fuse verify is inhibited. However, the User Signature and device ID remain accessible. 10 ATF15xxSE Family 2401D–PLD–09/02 ATF15xxSE Family JTAG-BST Overview The JTAG-BST (JTAG boundary-scan testing) is controlled by the Test Access Port (TAP) controller. The boundary-scan technique involves the inclusion of a shift-register stage (contained in a boundary-scan cell) adjacent to each component so that signals at component boundaries can be controlled and observed using scan testing principles. Each input pin and I/O pin has its own Boundary-scan Cell (BSC) in order to support boundary-scan testing. The ATF15xxSE Family does not currently include a Test Reset (TRST) input pin because the TAP controller is automatically reset at power-up. The ATF15xxSE Family implements six BST instructions, and seven Atmel-defined In System Programming (ISP) instructions. All ATF15xx Family BST and ISP instructions have a length of 10 bits. JTAG BST Instructions SAMPLE/PRELOAD EXTEST Description Captures signals at the device pins for later examination, or loads a data pattern prior to an EXTEST instruction. Allows testing of off-chip circuitry and interconnections by forcing a pattern on the output pins or capturing signals from the input pins. Places a single shift register stage between TDI and TDO, allowing test BST data to pass through a particular device in a chain of devices. Places the 32-bit IDCODE register between TDI and TDO, allowing the IDCODE data to be shifted out of TDO. Places the 16-bit user electronic signature register between TDI and TDO, allowing the UESCODE data to be shifted out of TDO. Places the BYPASS register between TDI and TDO in a high impedance mode, protecting the device from damage from externally applied test signals. These seven instructions allow in-system programming via the four JTAG pins. BYPASS IDCODE UESCODE HIGHZ 7 ISP instructions The ATF15xxSE Family BST implementation complies with the Boundary-scan Definition Language (BSDL) described in the JTAG specification (IEEE Standard 1149.1). Any third-party tool that supports the BSDL format can be used to perform BST on the ATF15xxSE Family. The ATF15xxSE Family also has the option of using four JTAG-standard I/O pins for in-system programming (ISP). The ATF15xxSE Family is programmable through the four JTAG pins using programming-compatible with the IEEE JTAG Standard 1149.1. Programming is performed by using 5V TTL-level programming signals from the JTAG ISP interface. The JTAG feature is a programmable option. If JTAG (BST or ISP) is not needed, then the four JTAG control pins are available as I/O pins. Refer to Atmel Application Note “Designing for In-System Programmability with Atmel CPLDs for more details. 11 2401D–PLD–09/02 JTAG Boundary-scan Cell (BSC) Testing The ATF15xxSE Family has four dedicated input pins and a number of I/O pins depending on the device type and package type selected. Each input pin and I/O pin has a boundary-scan cell (BSC) which supports boundary-scan testing as described in detail by IEEE Standard 1149.1. A typical BSC consists of three capture registers or scan registers and up to two update registers. There are two types of BSCs, one for input or I/O pin, and one for the macrocells. The BSCs in the device are chained together through the (BST) capture registers. Input to the capture register chain is fed in from the TDI pin while the output is directed to the TDO pin. Capture registers are used to capture active device data signals, to shift data in and out of the device and to load data into the update registers. Control signals are generated internally by the JTAG TAP controller. IDCODE MSB LSB 0000,0001,0101,0100,0010,0000,0011,1111 0000,0001,0101,0100,0100,0000,0011,1111 0000,0001,0101,0100,1000,0000,0011,1111 0000,0001,0101,0101,0000,0000,0011,1111 Device ATF1502SE ATF1504SE ATF1508SE ATF1516SE Note: Boundary-Scan Register Length 96 192 352 672 Shaded data is preliminary and subject to change without notice. Boundary-scan Definition Language (BSDL) Models These are now available in all package types via the Atmel web site. These models conform to the IEEE 1149.1 standard and can be used for Boundary-scan Test Operation of the ATF15xxSE Family. The BSC configuration for the input and I/O pins and macrocells are shown on page 13. 12 ATF15xxSE Family 2401D–PLD–09/02 ATF15xxSE Family BSC Configuration for Pins (Except JTAG TAP Pins) BSC Configuration for Macrocell TDO OEJ 0 0 1 1 DQ DQ OUTJ 0 0 1 1 DQ DQ Pin Capture Register TDI Shift Update Register Mode Clock Macrocell BSC 13 2401D–PLD–09/02 PCI Compliance The ATF15xx Family also supports peripheral component interconnect (PCI) interface standard in PCI-based designs and specifications. The PCI interface calls for high current drivers, which are much larger than the traditional TTL drivers. 2.4 Voltage PCI Voltage-toCurrent Curves for +5V Signaling in Pull-up Mode Pull Up VCC Test Point 1.4 DC drive point AC drive point -2 -44 Current (mA) -178 2.2 DC drive point 0.55 Test Point Voltage PCI Voltage-toCurrent Curves for +5V Signaling in Pull-down Mode Pull Down VCC AC drive point 3,6 95 Current (mA) 380 14 ATF15xxSE Family 2401D–PLD–09/02 ATF15xxSE Family PCI DC Characteristics Symbol VCC VIH VIL IIH IIL VOH VOL CIN CCLK CIDSEL LPIN Note: Parameter Supply Voltage Input High Voltage Input Low Voltage Input High Leakage Current Input Low Leakage Current Output High Voltage Output Low Voltage Input Pin Capacitance CLK Pin Capacitance IDSEL Pin Capacitance Pin Inductance Leakage current is without pin-keeper off. VIN = 2.7V VIN = 0.5V IOUT = -2 mA IOUT = 3 mA, 6 mA 2.4 0.55 10 12 8 20 Conditions Min 4.75 2.0 -0.5 Max 5.25 VCC + 0.5 0.8 70 -70 Units V V V µA µA V V pF pF pF nH PCI AC Characteristics Symbol IOH(AC) Parameter Switching Current High Conditions 0 < VOUT ≤ 1.4 1.4 < VOUT < 2.4 3.1 < VOUT < V CC (Test High) IOL(AC) Switching Current Low VOUT = 3.1V VOUT > 2.2V 2.2 > VOUT > 0 0.1 > VOUT > 0 (Test Point) ICL SLEWR SLEWF Notes: Low Clamp Current Output Rise Slew Rate Output Fall Slew Rate VOUT = 0.71 -5 < VIN ≤ -1 0.4V to 2.4V load 2.4V to 0.4V load -25+(VIN + 1)/0.015 0.5 0.5 3.0 3.0 95 VOUT/0.023 Equation B 206 Min -44 -44+(VOUT - 1.4)/0.024 Equation A -142 Max Units mA mA mA µA mA mA mA mA mA V/ns V/ns 1. Equation A: IOH = 11.9 (VOUT - 5.25) * (VOUT + 2.45) for VCC > VOUT > 3.1V. 2. Equation B: IOL = 78.5 * VOUT * (4.4 - VOUT ) for 0V < VOUT < 0.71V. 15 2401D–PLD–09/02 Absolute Maximum Ratings* Ambient Temperature Under Bias.................. -65°C to +135°C Storage Temperature ..................................... -65°C to +150°C Junction Temperature ..............................................150°C(MAX) Voltage on Any Pin with Respect to Ground .........................................-2.0V to +7.0V(1) Voltage on Input Pins with Respect to Ground During Programming.....................................-2.0V to +14.0V(1) Programming Voltage with Respect to Ground .......................................-2.0V to +14.0V(1) DC Output Current per Pin ................................ -25 to +25 mA Note: *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 1. For currents less than 100 mA, minimum voltage is -0.6 VDC and maximum voltage is VCC + 0.75 VDC. Pulses of less than 20µs may undershoot to -2.0V or overshoot to 7.0V. DC and AC Operating Conditions Commercial Operating Temperature (Ambient), TA Junction Temperature, TJ (1) Industrial -40°C - 85°C – 5V ± 10% 5V ± 10% 3.0 - 3.6 -0.5 - V CCINT + .5 0 - VCCIO 40 ns Max 40 ns Max 0°C - 70°C – 5V ± 5% 5V ± 5% 3.0 - 3.6 -0.5 - VCCINT + .5 0 - VCCIO 40 ns Max 40 ns Max VCCINT (5.0V) Power Supply VCCIO (5.0V) Power Supply VCCIO (3.3V) Power Supply VI Input Voltage VO Output Voltage tR tF Note: 1. Junction temperature is package and device dependant and can be calculated as follows: TJ(MAX) = TA(MAX) + (θJA|Air Flow = 0*P(MAX)). For more information see “Thermal Characteristics of Atmel Packages.” 16 ATF15xxSE Family 2401D–PLD–09/02 ATF15xxSE Family DC Characteristics(1) ATFxxSE Family Symbol IIL IIH IOZ ICC1 Parameter Input or I/O Low Leakage Current Input or I/O High Leakage Current Tri-State Output Off-State Current Power Supply Current, Standby VO = VCC or GND VCC = Max VIN = 0, VCC Std Mode Com. Ind. “ITD” Mode ICC2 ICC3(2) VIL VIH VOL Power Supply Current, Power-down Mode Reduced-power Mode Supply Current, Standby Input Low Voltage Input High Voltage 5.0V Output Low Voltage (TTL) 3.3V Output Low Voltage (TTL) 3.3V Output Low Voltage (CMOS) VOH 5.0V Output High Voltage (TTL) 3.3V Output High Voltage (TTL) 3.3V Output High Voltage (CMOS) Notes: IOL = 12 mA, V CCIO = 4.75V IOL = 12 mA, V CCIO = 3.0V IOL = 0.1 mA, VCCIO = 3.0V IOH = -4 mA, V CCIO = 4.75V IOH = -4 mA, V CCIO = 3.0V IOH = -0.1 mA, VCCIO = 3.0V 2.4 2.4 VCCIO – 0.2 VCC = Max VIN = 0, VCC VCC = Max VIN = 0, VCC Com. Ind. -40 (3) (3) Condition VIN = VCC Min Typ -2 2 Min -10 10 40 Unit µA µA µA mA mA mA mA 1 1 0.1 (3) (3) PD Mode Std Mode Com. Ind. -0.3 2.0 1 mA mA mA 0.8 VCCINT +0.5 0.45 0.45 0.2 V V V V V V V V 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec. 2. ICC3 refers to the current in the reduced-power mode when macrocell reduced-power is turned ON. 3. See characteristic curves for each device. Power-down AC Characteristics(1) ATFxxSE Family -5 Symbol tIVDH tGVDH tCVDH tDHIX tDHGX tDHCX tDLIV tDLGV tDLCV tDLOV Notes: Parameter Valid 1, I/O before PD High Valid 1, OE (2) -6 Max Min 6.0 6.0 6.0 9.0 9.0 9.0 1.0 1.0 1.0 1.0 10.0 10.0 10.0 1.0 1.0 1.0 1.0 Max Min 7.0 7.0 7.0 -7 Max Min 10 10 10 12 12 12 1.0 1.0 1.0 1.0 -10 Max Min 15 15 15 15.0 15.0 15.0 1.0 1.0 1.0 1.0 -15 Max Unit ns ns ns 25 25 25 1.0 1.0 1.0 1.0 ns ns ns µs µs µs µs Min 5.0 5.0 5.0 before PD High (2) Valid 1, Clock (2) before PD High I, I/O Don’t Care after PD High OE Don’t Care after PD High (2) Clock Don’t Care after PD High PD Low to Valid I, I/O PD Low to Valid OE, (Pin or Term) PD Low to Valid Clock, (Pin or Term) PD Low to Valid Output 1. For slow slew outputs, add tSSO. 2. Pin or product term. 17 2401D–PLD–09/02 Timing Model U Pin Capacitance Typ(1) CIN CI/O Note: 8 8 Max 10 10 Units pF pF Condition VIN = 0V; f = 1.0 MHz VOUT = 0V; f = 1.0 MHz 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. The OGI pin (high-voltage pin during programming) has a maximum capacitance of 12 pF. Input Test Waveforms and Measurement Levels Output AC Test Loads 5.0V (3.3V) 464 (703 ) 250 (8060 ) C = CL 18 ATF15xxSE Family 2401D–PLD–09/02 ATF1502SE AC Characteristics(1) ATF1502SE(L) SE -5 Symbol tPD1 tPD2 tSU tH tFSU tFH tCO1 tCH tCL tASU tAH tACO1 tACH tACL tCNT fCNT(3) tACNT fACNT (4) SE -6 Min Max 6.0 6.0 4.0 0.0 2.5 0.0 3.2 3.5 2.5 2.5 0.9 2.1 5.4 5.4 2.5 2.5 5.7 7.0 143 7.0 143 200 0.2 0.2 2.2 3.1 0.9 2.6 2.5 0.7 0.2 0.2 0.2 2.1 3.8 1.1 3.3 3.3 0.8 0.3 SE -7 Min Max 7.5 7.5 5.0 0.0 2.5 0.0 4.3 3.0 3.0 1.1 2.7 6.6 3.0 3.0 8.6 117 8.6 117 167 0.3 0.3 2.5 4.6 1.4 4.0 4.0 1.0 0.4 SE -10 Min Max 10 10 7.0 0.0 3.0 0.0 5.0 4.0 4.0 2.0 3.0 8.2 4.0 4.0 10.0 100 10.0 100 125 0.5 0.5 1.0 5.0 0.8 5.0 5.0 2.0 1.5 SEL -15(6) Min Max 15 12 11 0.0 3.0 1.0 8.0 5.0 5.0 4.0 4.0 15 6.0 6.0 13 77 or 100(6) 13 77 or 100(6) 80 or 125(6) 1.0 1.0 1.5 8.0 1.0 6.0 6.0 3.0 2.5 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz ns MHz MHz ns ns ns ns ns ns ns ns ns Parameter Input or Feedback to Nonregistered Output I/O Input or Feedback to Nonregistered Feedback Global Clock Setup Time Global Clock Hold Time Global Clock Setup Time of Fast Input Global Clock Hold of Fast Input Global Clock to Output Delay Global Clock High Time Global Clock Low Time Array Clock Setup Time Array Clock Hold Time Array Clock Output Delay Array Clock High Time Array Clock Low Time Minimum Clock Global Period Maximum Internal Global Clock Frequency Minimum Array Clock Period Maximum Internal Array Clock Frequency Maximum Clock Frequency Input Pad and Buffer Delay I/O Input Pad and Buffer Delay Fast Input Delay Foldback Term Delay Cascade Logic Delay Logic Array Delay Logic Control Delay Internal Output Enable Delay Output Buffer and Pad Delay (slow slew rate = OFF; VCCIO = 5V; CL= 35 pF) Min Max 5.0 5.0 2.9 0.0 2.5 0.0 2.0 2.0 0.7 1.8 2.5 2.5 175.4 5.7 175.4 250 fMAX(5) tIN tIO tFIN tSEXP tPEXP tLAD tLAC tIOE tOD1 19 2401D–PLD–09/02 AC Characteristics(1) ATF1502SE(L) (Continued) SE -5 Symbol tOD2 Parameter Output Buffer and Pad Delay (slow slew rate = OFF; VCCIO = 3.3V; CL= 35 pF) Output Buffer and Pad Delay (slow slew rate = ON; VCCIO = 5V or 3.3V; CL= 35 pF) Output Buffer Enable Delay (slow slew rate = OFF; VCCIO = 5V; CL= 35 pF) Output Buffer Enable Delay (slow slew rate = OFF; VCCIO = 3.3V; CL= 35 pF) Output Buffer Enable Delay (slow slew rate = ON; VCCIO = 5V or 3.3V; CL= 35 pF) Output Buffer Disable Delay (CL= 5 pF) Register Setup Time Register Hold Time Register Setup Time of Fast Input Register Hold Time of Fast Input Register Delay Combinatorial Delay Array Clock Delay Register Enable Time Global Control Delay Register Preset Time Register Clear Time Switch Matrix Delay 0.8 1.7 1.9 0.6 1.2 0.9 2.7 2.6 1.6 2.0 2.0 1.1 Min Max 0.7 SE -6 Min Max 0.8 SE -7 Min Max 0.9 SE -10 Min Max 2.0 SEL -15(6) Min Max 3.0 Unit ns tOD3 5.2 5.3 5.4 5.5 6.0 ns tZX1 4.0 4.0 4.0 5.0 7.0 ns tZX2 4.5 4.5 4.5 5.5 7.0 ns tZX3 9.0 9.0 9.0 9.0 10 ns tXZ tSU tH tFSU tFH tRD tCOMB tIC tEN tGLOB tPRE tCLR tUIM tRPA(2) Notes: 4.0 1.0 2.0 1.7 0.7 4.0 1.3 2.5 1.7 0.8 1.6 1.1 3.4 3.3 1.4 2.4 2.4 1.1 4.0 2.0 3.0 3.0 0.5 1.2 1.0 2.0 1.0 1.3 1.9 3.0 1.4 5.0 4.0 4.0 5.0 2.0 2.0 2.0 5.0 5.0 1.0 3.0 3.0 1.0 6.0 ns ns ns ns ns 2.0 2.0 7.0 7.0 1.0 5.0 5.0 2.0 ns ns ns ns ns ns ns ns Reduced Power Adder 8 9 10 11 13 ns 1. See ordering Information for valid part numbers. 2. The tRPA parameter must be added to the tLAD, tLAC, tIC, tACL and tSEXP parameters for macrocells running in the reducedpower mode. 3. fCNT is the fastest 16-bit counter frequency available, using the local feedback when applicable, and a PIA fan-out of one logic block (16 macrocells). fCNT is also the Export Control Maximum flip-flop toggle rate, fTOG. 4. fACNT is the fastest 16-bit counter frequency available, using the internal array clock, local feedback when applicable and a PIA fan-out of one logic block (16 macrocells). 5. fMAX is the fastest available frequency for pipelined data. 6. For clocked applications and frequencies above fCRITICAL, OR, non-clocked applications with dormant times less than 1/fCRITICAL, the device will achieve the speeds of the –10 column. See “Input Transition Detection/ Automatic Power Down” on page 8. 20 ATF1502SE 2401D–PLD–09/02 ATF1502SE STAND-BY ICC VS. SUPPLY VOLTAGE (TA = 25°C) 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 4.5 4.8 NORMALIZED Icc 1.4 1.2 1.0 TBD 0.8 0.6 0.4 -40.0 NORMALIZED ICC VS. TEMP ICC (µA) TBD 5.0 SUPPLY VOLTAGE (V) 5.3 5.5 0.0 25.0 75.0 TEMPERATURE (C) SUPPLY CURRENT VS. INPUT FREQUENCY (VCC = 5.0V, T A = 25°C) 140.000 120.000 ICC (mA) SUPPLY CURRENT VS. INPUT FREQUENCY (V CC = 5.0V, TA = 25°C) 1.000 0.800 0.600 0.400 0.200 0.000 0.0 0.5 2.5 5.0 7.5 10.0 25.0 37.5 50.0 FREQUENCY (MHz) TBD 100.000 ICC (mA) 80.000 TBD 60.000 40.000 20.000 0.000 0.0 0.5 2.5 5.0 7.5 10.0 FREQUENCY (MHz) 25.0 37.5 50.0 0 -10 IOH (mA) -20 -30 -40 -50 4.0 OUTPUT SOURCE CURRENT VS. SUPPLY VOLTAGE (VOH = 2.4V) 0.0 -10.0 -20.0 -30.0 -40.0 -50.0 -60.0 -70.0 -80.0 -90.0 OUTPUT SOURCE CURRENT VS. OUTPUT VOLTAGE (VCC = 5.0V, TA = 25°C) IOH (mA) TBD TBD 4.5 5.0 SUPPLY VOLTAGE (V) 5.5 6.0 0.00 0.50 1.00 1.50 2.00 2.50 VOH (V) 3.00 3.50 4.00 4.50 5.00 48 46 Iol (mA) OUTPUT SINK CURRENT VS. SUPPLY VOLTAGE (VOL = 0.5V) 140.0 120.0 OUTPUT SINK CURRENT VS. OUTPUT VOLTAGE (V CC = 5.0V, TA = 25°C) 44 IOL (mA) 42 40 38 36 4.0 4.5 TBD 100.0 80.0 60.0 40.0 TBD 5.0 SUPPLY VOLTAGE (V) 5.5 6.0 20.0 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 SUPPLY VOLTAGE (V) 21 2401D–PLD–09/02 0 INPUT CURRENT (mA) -20 -40 -60 -80 -100 -120 0.0 INPUT CLAMP CURRENT VS. INPUT VOLTAGE (V CC = 5.0V, TA = 35°C) INPUT CURRENT (uA) 40 30 20 10 0 -10 -20 -30 0.0 INPUT CURRENT VS. INPUT VOLTAGE (VCC = 5.0V, T A = 25°C) TBD TBD -0.2 -0.4 -0.6 INPUT VOLTAGE (V) -0.8 -1.0 1.0 2.0 3.0 4.0 INPUT VOLTAGE (V) 5.0 6.0 NORMALIZED TPD VS. VCC 1.2 NORMALIZED TPD 1.1 1.0 0.9 0.8 4.5 4.8 5.0 SUPPLY VOLTAGE (V) 5.3 5.5 TBD NORMALIZED TPD 1.1 NORMALIZED T PD VS. TEMP 1.0 TBD 0.9 0.8 -40.0 0.0 25.0 TEMPERATURE (C) 75.0 1.3 NORMALIZED TCO NORMALIZED TCO VS. VCC 1.1 NORMALIZED TCO NORMALIZED T CO VS. TEMP 1.2 1.1 TBD 1.0 0.9 0.8 4.5 4.8 5.0 SUPPLY VOLTAGE (V) 5.3 5.5 1.0 TBD 0.9 0.8 -40.0 0.0 25.0 75.0 TEMPERATURE (V) NORMALIZED TSU VS. VCC 1.2 NORMALIZED TSU NORMALIZED TSU VS. TEMP 1.2 NORMALIZED TCO 1.1 1.0 0.9 0.8 -40.0 TBD 1.1 1.0 0.9 0.8 4.5 4.8 5.0 SUPPLY VOLTAGE (V) 5.3 5.5 TBD 0.0 25.0 75.0 TEMPERATURE (C) 22 ATF1502SE 2401D–PLD–09/02 ATF1502SE 8 DELTA TPD VS. OUTPUT LOADING 8.00 7.00 DELTA TCO VS. OUTPUT LOADING DELTA T PD (ns) 6 4 DELTA T CO (ns) 6.00 5.00 4.00 3.00 2.00 1.00 TBD 2 0 -2 TBD 0.00 0 50 100 150 200 250 300 50 100 150 200 250 300 OUTPUT LOADING (PF) NUMBER OF OUTPUTS LOADING DELTA TCO VS. # OF OUTPUT SWITCHING 0.0 DELTA TPD (ns) -0.1 -0.2 TBD -0.3 -0.4 -0.5 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 NUMBER OF OUTPUTS SWITCHING DELTA TPD VS. # OF OUTPUT SWITCHING DELTA TCO (ns) 0.0 -0.1 TBD -0.2 -0.3 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 NUMBER OF OUTPUTS SWITCHING 23 2401D–PLD–09/02 ATF1502SE(L) Pinouts 44-lead TQFP - Top View I/O I/O I/O VCC GCK2/OE2/I GCLR/I OE1/I GCK1/I GND I/O/GCLK3 I/O 44 43 42 41 40 39 38 37 36 35 34 I/O I/O I/O VCC I/OE2/GCK2 GCLR/I I/OE1 GCK1/I GND GCK3 I/O I/O I/O I/O I/O GND VCC I/O PD2/I/O I/O I/O I/O 18 19 20 21 22 23 24 25 26 27 28 TDI/I/O I/O I/O GND PD1/I/O I/O I/O/TMS I/O VCC I/O I/O 7 8 9 10 11 12 13 14 15 16 17 6 5 4 3 2 1 44 43 42 41 40 ATF1502SE(L) ATF1504SE(L) 39 38 37 36 35 34 33 32 31 30 29 I/O I/O/TDO I/O I/O VCC I/O I/O I/O/TCK I/O GND I/O 44-lead PLCC - Top View I/O/TDI I/O I/O GND PD1/I/O I/O TMS/I/O I/O VCC I/O I/O 1 2 3 4 5 6 7 8 9 10 11 ATF1502SE(L) ATF1504SE(L) 33 32 31 30 29 28 27 26 25 24 23 I/O I/O/TDO I/O I/O VCC I/O I/O I/O/TCK I/O GND I/O 24 ATF1502SE 2401D–PLD–09/02 I/O I/O I/O I/O GND VCC I/O PD2/I/O I/O I/O I/O 12 13 14 15 16 17 18 19 20 21 22 ATF1502SE ATF1502SE(L) Dedicated Pinouts Dedicated Pin INPUT/GCLK1 INPUT/GCLR INPUT/OE1 INPUT/OE2/GCLK2 I/O/GCLK3 I/O/PD (1,2) I/O/TDI (JTAG) I/O/TMS (JTAG) I/O/TCK (JTAG) I/O/TDO (JTAG) GNDINT GNDIO VCCINT VCCIO # of Signal Pins # User I/O Pins 44-PLCC J-lead 43 1 44 2 41 11, 25 7 13 32 38 22, 42 10, 30 3, 23 15, 35 36 32 44-lead TQFP 37 39 38 40 35 5, 19 1 7 26 32 16, 36 4, 24 17, 41 9, 29 36 32 OE (1, 2) Global OE pins GCLR Global Clear pin GCLK (1, 2, 3) Global Clock pins PD (1, 2) Power-down pins TDI, TMS, TCK, TDO JTAG pins used for boundary-scan testing or in-system programming GNDINT Ground pins for the internal device logic GNDIO Ground pins for the I/O drivers VCCINT VCC pins for the internal device logic (+3.3V) VCCIO VCC for the I/O drivers 25 2401D–PLD–09/02 ATF1502SE(L) I/O Pinouts MC 1 2 3 4/TDI 5 6 7/PD1 8 9/TMS 10 11 12 13 14 15 16 17 18 19 20/TDO 21 22 23 24 25/TCK 26 27 28 29 30 31/PD2 32 PLC A A A A A A A A A A A A A A A A B B B B B B B B B B B B B B B B 44-lead PLCC 4 5 6 7 8 9 11 12 13 14 16 17 18 19 20 21 41 40 39 38 37 36 34 33 32 31 29 28 27 26 25 24 44-lead TQFP 42 43 44 1 2 3 5 6 7 8 10 11 12 13 14 15 35 34 33 32 31 30 28 27 26 25 23 22 21 20 19 18 26 ATF1502SE 2401D–PLD–09/02 ATF1502SE ATF1502SE(L) Ordering Information tPD (ns) 5.0 6.0 7.5 tCO1 (ns) 3.2 3.5 4.3 FMAX (MHz) 250 200 167 Ordering Code ATF1502SE-5 AC44 ATF1502SE-5 JC44 ATF1502SE-6 AC44 ATF1502SE-6 JC44 ATF1502SE-7 AC44 ATF1502SE-7 JC44 ATF1502SE-7 AI44 ATF1502SE-7 JI44 10 5.0 125 ATF1502SE-10 AC44 ATF1502SE-10 JC44 ATF1502SE-10 AI44 ATF1502SE-10 JI44 15 8.0 77 ATF1502SEL-15 AC44 ATF1502SEL-15 JC44 Package 44A 44J 44A 44J 44A 44J 44A 44J 44A 44J 44A 44J 44A 44J Operation Range Commercial (0°C to 70°C) Commercial (0°C to 70°C) Commercial (0°C to 70°C) Industrial (-40°C to +85°C) Commercial (0°C to 70°C) Industrial (-40°C to +85°C) Commercial (0°C to 70°C) Using “C” Product for Industrial To use commercial product for industrial temperature ranges, downgrade one speed grade from the “I” to the “C” device, and de-rate power by 30%. Package Type 44A 44J 44-lead, Thin Plastic Gull Wing Quad Flatpack (TQFP) 44-lead, Plastic J-leaded Chip Carrier (PLCC) 27 2401D–PLD–09/02 AC Characteristics(1) ATF1504SE(L) SE -5 Symbol tPD1 tPD2 tSU tH tFSU tFH tCO1 tCH tCL tASU tAH tACO1 tACH tACL tCNT fCNT(3) tACNT fACNT(4) fMAX(5) tIN tIO tFIN tSEXP tPEXP tLAD tLAC tIOE tOD1 Parameter Input or Feedback to Nonregistered Output I/O Input or Feedback to Nonregistered Feedback Global Clock Setup Time Global Clock Hold Time Global Clock Setup Time of Fast Input Global Clock Hold of Fast Input Global Clock to Output Delay Global Clock High Time Global Clock Low Time Array Clock Setup Time Array Clock Hold Time Array Clock Output Delay Array Clock High Time Array Clock Low Time Minimum Clock Global Period Maximum Internal Global Clock Frequency Minimum Array Clock Period Maximum Internal Array Clock Frequency Maximum Clock Frequency Input Pad and Buffer Delay I/O Input Pad and Buffer Delay Fast Input Delay Foldback Term Delay Cascade Logic Delay Logic Array Delay Logic Control Delay Internal Output Enable Delay Output Buffer and Pad Delay (slow slew rate = OFF; VCCIO = 5V; C L= 35 pF) 176 250 0.2 0.2 2.2 3.1 0.9 2.6 2.5 0.7 0.2 176 5.7 141 200 0.2 0.2 2.6 3.8 1.1 3.2 3.2 0.8 0.3 2.5 2.5 5.7 141 7.1 125 167 0.5 0.5 1.0 4.0 0.8 3.0 3.0 2.0 2.0 2.0 2.0 0.7 1.8 5.4 2.5 2.5 7.1 125 8.0 100 125 0.5 0.5 1.0 5.0 0.8 5.0 5.0 2.0 1.5 2.9 0.0 2.5 0.0 3.2 2.5 2.5 0.9 2.9 6.7 3.0 3.0 8.0 100 10 77 77 1.0 1.0 2.0 8.0 1.0 6.0 6.0 3.0 2.5 Min Max 5.0 5.0 3.6 0.0 2.5 0.0 4.0 3.0 3.0 2.0 2.0 7.5 4.0 4.0 10 77 13 SE -6 Min Max 6.0 6.0 6.0 0.0 3.0 0.5 4.5 4.0 4.0 2.0 3.0 10.0 6.0 6.0 13 SE -7 Min Max 7.5 7.5 7.0 0.0 3.0 0.5 5.0 5.0 5.0 5.0 4.0 15 SE -10 Min Max 10 10 11 0.0 3.0 1.0 9.0 SEL -15(6) Min Max 15 12 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz ns MHz MHz ns ns ns ns ns ns ns ns ns 28 ATF1504SE(L) 2401D–PLD–09/02 ATF1504SE(L) AC Characteristics(1) ATF1504SE(L) (Continued) SE -5 Symbol tOD2 Parameter Output Buffer and Pad Delay (slow slew rate = OFF; VCCIO = 3.3V; CL= 35 pF) Output Buffer and Pad Delay (slow slew rate = ON; VCCIO = 5V or 3.3V; C L= 35 pF) Output Buffer Enable Delay (slow slew rate = OFF; VCCIO = 5V; C L= 35 pF) Output Buffer Enable Delay (slow slew rate = OFF; VCCIO = 3.3V; CL= 35 pF) Output Buffer Enable Delay (slow slew rate = ON; VCCIO = 5V or 3.3V; C L= 35 pF) Output Buffer Disable Delay (CL= 5 pF) Register Setup Time Register Hold Time Register Setup Time of Fast Input Register Hold Time of Fast Input Register Delay Combinatorial Delay Array Clock Delay Register Enable Time Global Control Delay Register Preset Time Register Clear Time Switch Matrix Delay 0.8 1.7 1.9 0.6 1.2 0.9 2.7 2.6 1.6 2.0 2.0 1.1 Min Max 0.7 SE -6 Min Max 0.8 SE -7 Min Max 2.5 SE -10 Min Max 2.0 SEL -15(6) Min Max 3.0 Unit ns tOD3 5.2 5.3 7.0 5.5 6.0 ns tZX1 4.0 4.0 4.0 5.0 7.0 ns tZX2 4.5 4.5 4.5 5.5 7.0 ns tZX3 9.0 9.0 9.0 9.0 10 ns tXZ tSU tH tFSU tFH tRD tCOMB tIC tEN tGLOB tPRE tCLR tUIM 4.0 1.0 2.0 1.8 0.7 4.0 3.0 2.0 3.0 0.5 1.6 1.0 3.3 3.2 1.9 2.4 2.4 1.3 4.0 2.0 3.0 3.0 0.5 1.0 1.0 3.0 3.0 1.0 2.0 2.0 1.0 5.0 5.0 4.0 5.0 2.0 2.0 2.0 5.0 5.0 1.0 3.0 3.0 1.0 6.0 ns ns ns ns ns 2.0 2.0 6.0 6.0 2.0 4.0 4.0 2.0 ns ns ns ns ns ns ns ns Reduced Power Adder 8.0 9.0 1.0 11 13 ns tRPA(2) Notes: 1. See ordering Information for valid part numbers. 2. The tRPA parameter must be added to the tLAD, tLAC, tIC, tACL and tSEXP parameters for macrocells running in the reducedpower mode. 3. fCNT is the fastest 16-bit counter frequency available, using the local feedback when applicable, and a PIA fan-out of one logic block (16 macrocells). fCNT is also the Export Control Maximum flip-flop toggle rate, fTOG. 4. fACNT is the fastest 16-bit counter frequency available, using the internal array clock, local feedback when applicable and a PIA fan-out of one logic block (16 macrocells). 5. fMAX is the fastest available frequency for pipelined data. 6. For clocked applications and frequencies above fCRITICAL, OR, non-clocked applications with dormant times less than 1/fCRITICAL, the device will achieve the speeds of the –10 column. See “Input Transition Detection/ Automatic Power Down” on page 8. 29 2401D–PLD–09/02 STAND-BY ICC VS. SUPPLY VOLTAGE (TA = 25°C) 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 4.5 4.8 NORMALIZED Icc 1.4 1.2 1.0 NORMALIZED ICC VS. TEMP ICC (µA) TBD TBD 0.8 0.6 0.4 -40.0 5.0 SUPPLY VOLTAGE (V) 5.3 5.5 0.0 25.0 75.0 TEMPERATURE (C) SUPPLY CURRENT VS. INPUT FREQUENCY (VCC = 5.0V, T A = 25°C) 140.000 120.000 ICC (mA) 100.000 ICC (mA) 80.000 TBD 60.000 40.000 20.000 0.000 0.0 0.5 2.5 5.0 7.5 10.0 FREQUENCY (MHz) 25.0 37.5 50.0 SUPPLY CURRENT VS. INPUT FREQUENCY (VCC = 5.0V, TA = 25°C) 1.000 0.800 0.600 0.400 0.200 0.000 0.0 0.5 2.5 5.0 7.5 10.0 25.0 37.5 50.0 FREQUENCY (MHz) TBD 0 -10 IOH (mA) -20 -30 -40 -50 4.0 OUTPUT SOURCE CURRENT VS. SUPPLY VOLTAGE (VOH = 2.4V) 0.0 -10.0 -20.0 -30.0 -40.0 -50.0 -60.0 -70.0 -80.0 -90.0 OUTPUT SOURCE CURRENT VS. OUTPUT VOLTAGE (VCC = 5.0V, T A = 25°C) IOH (mA) TBD TBD 4.5 5.0 SUPPLY VOLTAGE (V) 5.5 6.0 0.00 0.50 1.00 1.50 2.00 2.50 VOH (V) 3.00 3.50 4.00 4.50 5.00 48 46 Iol (mA) OUTPUT SINK CURRENT VS. SUPPLY VOLTAGE (VOL = 0.5V) 140.0 120.0 OUTPUT SINK CURRENT VS. OUTPUT VOLTAGE (VCC = 5.0V, TA = 25°C) 44 IOL (mA) 42 40 38 36 4.0 4.5 5.0 SUPPLY VOLTAGE (V) 5.5 6.0 TBD 100.0 80.0 60.0 40.0 20.0 0.0 TBD 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 SUPPLY VOLTAGE (V) 30 ATF1504SE(L) 2401D–PLD–09/02 ATF1504SE(L) INPUT CLAMP CURRENT VS. INPUT VOLTAGE (V CC = 5.0V, TA = 35°C) INPUT CURRENT (uA) 0 INPUT CURRENT (mA) -20 -40 -60 -80 -100 -120 0.0 40 30 20 10 0 -10 -20 -30 0.0 INPUT CURRENT VS. INPUT VOLTAGE (VCC = 5.0V, T A = 25°C) TBD TBD -0.2 -0.4 -0.6 INPUT VOLTAGE (V) -0.8 -1.0 1.0 2.0 3.0 4.0 INPUT VOLTAGE (V) 5.0 6.0 NORMALIZED TPD VS. VCC 1.2 NORMALIZED TPD NORMALIZED T PD VS. TEMP 1.1 NORMALIZED TPD 1.1 1.0 0.9 0.8 4.5 4.8 5.0 SUPPLY VOLTAGE (V) 5.3 5.5 TBD 1.0 TBD 0.9 0.8 -40.0 0.0 25.0 TEMPERATURE (C) 75.0 1.3 NORMALIZED TCO 1.2 1.1 NORMALIZED TCO VS. VCC 1.1 NORMALIZED TCO NORMALIZED T CO VS. TEMP 1.0 TBD 0.9 TBD 1.0 0.9 0.8 4.5 4.8 5.0 SUPPLY VOLTAGE (V) 5.3 5.5 0.8 -40.0 0.0 25.0 75.0 TEMPERATURE (V) NORMALIZED TSU VS. VCC 1.2 NORMALIZED TSU NORMALIZED TSU VS. TEMP 1.2 NORMALIZED TCO 1.1 1.0 0.9 0.8 -40.0 TBD 1.1 1.0 0.9 0.8 4.5 4.8 5.0 SUPPLY VOLTAGE (V) 5.3 5.5 TBD 0.0 25.0 75.0 TEMPERATURE (C) 31 2401D–PLD–09/02 8 DELTA TPD VS. OUTPUT LOADING 8.00 7.00 DELTA TCO VS. OUTPUT LOADING DELTA T PD (ns) 6 4 DELTA T CO (ns) 6.00 5.00 4.00 3.00 2.00 1.00 TBD 2 0 -2 TBD 0.00 0 50 100 150 200 250 300 50 100 150 200 250 300 OUTPUT LOADING (PF) NUMBER OF OUTPUTS LOADING 0.0 DELTA TPD (ns) -0.1 -0.2 DELTA TPD VS. # OF OUTPUT SWITCHING DELTA TCO (ns) DELTA TCO VS. # OF OUTPUT SWITCHING 0.0 -0.1 TBD -0.2 TBD -0.3 -0.4 -0.5 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 NUMBER OF OUTPUTS SWITCHING -0.3 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 NUMBER OF OUTPUTS SWITCHING 32 ATF1504SE(L) 2401D–PLD–09/02 ATF1504SE(L) ATF1504SE(L) Pinouts 44-lead TQFP – Top View I/O I/O I/O VCC I/OE2/GCK2 GCLR/I I/OE1 GCK1/I GND GCK3 I/O 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 I/O/TDI I/O I/O GND PD1/I/O I/O TMS/I/O I/O VCC I/O I/O 1 2 3 4 5 6 7 8 9 10 11 ATF1502SE(L) ATF1504SE(L) I/O I/O/TDO I/O I/O VCC I/O I/O I/O/TCK I/O GND I/O 44-lead PLCC – Top View I/O I/O I/O VCC GCK2/OE2/I GCLR/I OE1/I GCK1/I GND I/O/GCLK3 I/O I/O I/O I/O I/O GND VCC I/O PD2/I/O I/O I/O I/O 18 19 20 21 22 23 24 25 26 27 28 TDI/I/O I/O I/O GND PD1/I/O I/O I/O/TMS I/O VCC I/O I/O 7 8 9 10 11 12 13 14 15 16 17 6 5 4 3 2 1 44 43 42 41 40 I/O I/O I/O I/O GND VCC I/O PD2/I/O I/O I/O I/O 39 38 37 36 35 34 33 32 31 30 29 12 13 14 15 16 17 18 19 20 21 22 ATF1502SE(L) ATF1504SE(L) I/O I/O/TDO I/O I/O VCC I/O I/O I/O/TCK I/O GND I/O 33 2401D–PLD–09/02 84-lead PLCC – Top View I/O I/O I/O I/O GND I/O I/O I/O VCCINT INPUT/OE2/GCLK2 INPUT/GCLR INPUT/OE1 INPUT/GCLK1 GND I/O/GCLK3 I/O I/O VCCIO I/O I/O I/O 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 I/O I/O I/O I/O I/O GND I/O I/O I/O VCCINT INPUT/OE2/GCLK2 INPUT/GCLR INPUT/OE1 INPUT/GCLK1 GND I/O/GCLK3 I/O I/O VCCIO I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCIO I/O I/O I/O GND VCCINT I/O I/O/PD2 I/O GND I/O I/O I/O I/O I/O VCCIO 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 I/O/PD1 VCCIO I/O/TDI I/O I/O I/O I/O GND I/O I/O I/O I/O/TMS I/O I/O VCCIO I/O I/O I/O I/O I/O GND 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 ATF1504SE(L) ATF1508SE(L) 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 I/O I/O GND I/O/TDO I/O I/O I/O I/O VCCIO I/O I/O I/O I/O/TCK I/O I/O GND I/O I/O I/O I/O I/O 100-lead TQFP – Top View I/O/PD1 I/O VCCIO I/O/TDI I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O/TMS I/O I/O VCCIO I/O I/O I/O I/O I/O I/O I/O 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 ATF1508SE(L) 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 I/O GND I/O/TDO I/O I/O I/O I/O I/O I/O VCCIO I/O I/O I/O I/O/TCK I/O I/O GND I/O I/O I/O I/O I/O I/O I/O VCCIO 34 ATF1504SE(L) 2401D–PLD–09/02 GND I/O I/O I/O I/O I/O I/O I/O VCCIO I/O I/O I/O GND VCCINT I/O I/O/PD2 I/O GND I/O I/O I/O I/O I/O I/O I/O 26 27 28 29 30 31 33 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 ATF1504SE(L) ATF1504SE(L) Dedicated Pinouts Dedicated Pin INPUT/GCLK1 INPUT/GCLR INPUT/OE1 INPUT/OE2/GCLK2 I/O /GCLK3 I/O/PD (1,2) I/O/TDI (JTAG) I/O/TMS (JTAG) I/O/TCK (JTAG) I/O/TDO (JTAG) GNDINT GNDIO VCCINT VCCIO N/C 44-lead TQFP 37 39 38 40 35 5, 19 1 7 26 32 16, 36 4, 24 17, 41 9, 29 44-lead PLCC 43 1 44 2 41 11, 25 7 13 32 38 22, 44 10, 30 3, 23 15, 35 84-lead PLCC 83 1 84 2 81 20, 46 14 23 62 71 42, 82 7, 18, 32,47, 69, 72 3, 43 13, 26, 33, 53, 66, 78 100-lead TQFP 87 89 88 90 85 12, 42 4 15 62 73 38, 86 11, 26, 43, 59, 74, 95 39, 91 3, 18, 34, 51, 66, 82 1, 2, 5, 7, 22, 24, 27, 28, 49, 50, 53, 55, 70, 72, 77, 78 68 64 # of Signal Pins # User I/O Pins 36 32 36 32 68 64 OE (1, 2) Global OE pins GCLR Global Clear pin GCLK (1, 2, 3) Global Clock pins PD (1, 2) Power-down pins TDI, TMS, TCK, TDO JTAG pins used for boundary-scan testing or in-system programming GNDINT Ground pins for the internal device logic GNDIO Ground pins for the I/O pins VCCINT VCC pins for the internal device logic VCCIO VCC for the I/O drivers 35 2401D–PLD–09/02 ATF1504SE(L) I/O Pinouts MC 1 2 3 4 5 6 7 8/ TDI 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32/ TMS PLC A A A/ PD1 A A A A A A A A A A A A A B B B B B B B B B B B B B B B B 44-lead PLCC 12 11 9 8 7 6 5 4 21 20 19 18 17 16 14 13 44-lead TQFP 6 5 3 2 1 44 43 42 15 14 13 12 11 10 8 7 84-lead PLCC 22 21 20 18 17 16 15 14 12 11 10 9 8 6 5 4 41 40 39 37 36 35 34 33 31 30 29 28 27 25 24 23 100-lead TQFP 14 13 12 10 9 8 6 4 100 99 98 97 96 94 93 92 37 36 35 33 32 31 30 29 25 23 21 20 19 17 16 15 MC 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48/ TCK 49 50 51 52 53 54 55 56/ TDO 57 58 59 60 61 62 63 64 PLC C C C/ PD2 C C C C C C C C C C C C C D D D D D D D D D D D D D D D D/ GCLK3 44-lead PLCC 24 25 26 27 28 29 31 32 33 34 36 37 38 39 40 41 44-lead TQFP 18 19 20 21 22 23 25 26 27 28 30 31 32 33 34 35 84-lead PLCC 44 45 46 48 49 50 51 52 54 55 56 57 58 60 61 62 63 64 65 67 68 69 70 71 73 74 75 76 77 79 80 81 100-lead TQFP 40 41 42 44 45 46 47 48 52 54 56 57 58 60 61 62 63 64 65 67 68 69 71 73 75 76 79 80 81 83 84 85 36 ATF1504SE(L) 2401D–PLD–09/02 ATF1504SE(L) ATF1504SE(L) Ordering Information tPD (ns) 5.0 tCO1 (ns) 3.2 fMAX (MHz) 250 Ordering Code ATF1504SE-5 ATF1504SE-5 ATF1504SE-5 ATF1504SE-5 ATF1504SE-6 ATF1504SE-6 ATF1504SE-6 ATF1504SE-6 ATF1504SE-7 ATF1504SE-7 ATF1504SE-7 ATF1504SE-7 ATF1504SE-7 ATF1504SE-7 ATF1504SE-7 ATF1504SE-7 10 5.0 125 AC44 JC44 JC84 AC100 AC44 JC44 JC84 AC100 AC44 JC44 JC84 AC100 AI44 JI44 J84 AI100 Package 44A 44J 84J 100A 44A 44J 84J 100A 44A 44J 84J 100A 44A 44J 84J 100A 44A 44J 84J 100A 44A 44J 84J 100A 44A 44J 84J 100A Operation Range Commercial (0°C to 70°C) 6.0 4.0 200 Commercial (0°C to 70°C) 7.5 4.5 167 Commercial (0°C to 70°C) Industrial (-40°C to +85°C) ATF1504SE-10 AC44 ATF1504SE-10 JC44 ATF1504SE-10 JC84 ATF1504SE-10 AC100 ATF1504SE-10 AI44 ATF1504SE-10 JI44 ATF1504SE-10 JI84 ATF1504SE-10 AI100 Commercial (0°C to 70°C) Industrial (-40°C to +85°C) 15 9.0 77 ATF1504SEL-15 AC44 ATF1504SEL-15 JC44 ATF1504SEL-15 JC84 ATF1504SEL-15 AC100 Commercial (0°C to 70°C) Using “C” Product for Industrial To use commercial product for industrial temperature ranges, down grade one speed grade from the “I” to the “C” device, and de-rate power by 30%. Package Type 44A 44J 84J 100A 44-lead, Thin Plastic Gull Wing Quad Flatpack (TQFP) 44-lead, Plastic J-leaded Chip Carrier (PLCC) 84-lead, Plastic J-leaded Chip Carrier (PLCC) 100-lead, Very Thin Plastic Gull Wing Quad Flatpack (TQFP) 37 2401D–PLD–09/02 AC Characteristics(1) ATF1508SE(L) SE -6 Symbol tPD1 tPD2 tSU tH tFSU tFH tCO1 tCH tCL tASU tAH tACO1 tACH tACL tCNT fCNT(3) tACNT fACNT(4) fMAX(5) tIN tIO tFIN tSEXP tPEXP tLAD tLAC tIOE tOD1 tOD2 tOD3 Parameter Input or Feedback to Non-registered Output I/O Input or Feedback to Non-registered Feedback Global Clock Setup Time Global Clock Hold Time Global Clock Setup Time of Fast Input Global Clock Hold of Fast Input Global Clock to Output Delay Global Clock High Time Global Clock Low Time Array Clock Setup Time Array Clock Hold Time Array Clock Output Delay Array Clock High Time Array Clock Low Time Minimum Clock Global Period Maximum Internal Global Clock Frequency Minimum Array Clock Period Maximum Internal Array Clock Frequency Maximum Clock Frequency Input Pad and Buffer Delay I/O Input Pad and Buffer Delay Fast Input Delay Foldback Term Delay Cascade Logic Delay Logic Array Delay Logic Control Delay Internal Output Enable Delay Output Buffer and Pad Delay (slow slew rate = OFF; VCCIO = 5V; CL= 35 pF) Output Buffer and Pad Delay (slow slew rate = OFF; VCCIO = 3.3V; CL= 35 pF) Output Buffer and Pad Delay (slow slew rate = ON; VCCIO = 5V or 3.3V; C L= 35 pF) Output Buffer Enable Delay (slow slew rate = OFF; VCCIO = 5V; CL= 35 pF) 150 167 0.2 0.2 2.6 3.7 1.1 3.0 3.0 0.7 0.4 0.9 5.4 150 6.8 125 167 0.5 0.5 1.0 4.0 0.8 3.0 3.0 2.0 2.0 2.5 7.0 3.0 3.0 6.8 125 8.0 100 125 0.5 0.5 1.0 5.0 0.0 5.0 5.0 2.0 1.5 2.0 5.5 3 3 0.9 1.8 6.5 3 3 8.0 100 10 77 100 2.0 2.0 2.0 8.0 1.0 6.0 6.0 3.0 4.0 5.0 8.0 3.4 0.0 2.5 0 4.0 3.0 3.0 3.0 2.0 7.5 4.0 4.0 10 77 13 Min Max 6 6 6.0 0.0 3.0 0.5 4.5 4.0 4.0 2.0 5.0 10 6.0 6.0 13 SE -7 Min Max 7.5 7.5 7.0 0.0 3.0 0.5 5.0 5.0 5.0 4.0 4.0 15 SE -10 Min Max 10 10 SEL -15(6) Min 15 15 11 0.0 3.0 1 8.0 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz ns MHz MHz ns ns ns ns ns ns ns ns ns ns ns tZX1 4.0 4.0 5 6.0 ns 38 ATF1508SE(L) 2401D–PLD–09/02 ATF1508SE(L) AC Characteristics(1) ATF1508SE(L) (Continued) SE -6 Symbol tZX2 tZX3 Parameter Output Buffer Enable Delay (slow slew rate = OFF; VCCIO = 3.3V; CL= 35 pF) Output Buffer Enable Delay (slow slew rate = ON; VCCIO = 5V or 3.3V; C L= 35 pF) Output Buffer Disable Delay (C L= 5 pF) Register Setup Time Register Hold Time Register Setup Time of Fast Input Register Hold Time of Fast Input Register Delay Combinatorial Delay Array Clock Delay Register Enable Time Global Control Delay Register Preset Time Register Clear Time Switch Matrix Delay 1.0 1.7 1.9 0.6 1.4 1.0 3.1 3.0 2.0 2.4 2.4 1.4 Min Max 4.5 9 SE -7 Min Max 4.5 9 SE -10 Min Max 5.5 9 SEL -15(6) Min Max 7.0 10.0 Unit ns ns tXZ tSU tH tFSU tFH tRD tCOMB tIC tEN tGLOB tPRE tCLR tUIM 4 3.0 2.0 3.0 0.5 4 2.0 5.0 3.0 0.5 1.0 1.0 3.0 3.0 1.0 2.0 2.0 1.0 5 4.0 4.0 2.0 1.0 2.0 2.0 5.0 5.0 1.0 3.0 3.0 1.0 6.0 ns ns ns ns ns 1.0 1.0 6.0 6.0 1.0 4.0 4.0 2.0 ns ns ns ns ns ns ns ns tRPA(2) Reduced Power Adder 10 10 11 13 ns Notes: 1. See ordering Information for valid part numbers. 2. The tRPA parameter must be added to the tLAD, tLAC, tIC, tACL and tSEXP parameters for macrocells running in the reducedpower mode. 3. fCNT is the fastest 16-bit counter frequency available, using the local feedback when applicable, and a PIA fan-out of one logic block (16 macrocells). fCNT is also the Export Control Maximum flip-flop toggle rate, fTOG. 4. fACNT is the fastest 16-bit counter frequency available, using the internal array clock, local feedback when applicable and a PIA fan-out of one logic block (16 macrocells). 5. fMAX is the fastest available frequency for pipelined data. 6. For clocked applications and frequencies above fCRITICAL, OR, non-clocked applications with dormant times less than 1/fCRITICAL, the device will achieve the speeds of the –10 column. See “Input Transition Detection/ Automatic Power Down” on page 8. 39 2401D–PLD–09/02 STAND-BY ICC VS. SUPPLY VOLTAGE (TA = 25°C) 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 4.5 4.8 NORMALIZED Icc 1.4 1.2 1.0 NORMALIZED ICC VS. TEMP ICC (µA) TBD TBD 0.8 0.6 0.4 -40.0 5.0 SUPPLY VOLTAGE (V) 5.3 5.5 0.0 25.0 75.0 TEMPERATURE (C) SUPPLY CURRENT VS. INPUT FREQUENCY (VCC = 5.0V, TA = 25°C) 140.000 120.000 SUPPLY CURRENT VS. INPUT FREQUENCY (VCC = 5.0V, TA = 25°C) 1.000 0.800 ICC (mA) 100.000 ICC (mA) 80.000 TBD 60.000 40.000 20.000 0.000 0.0 0.5 2.5 5.0 7.5 10.0 FREQUENCY (MHz) 25.0 37.5 50.0 0.600 0.400 0.200 0.000 0.0 0.5 2.5 5.0 7.5 10.0 25.0 37.5 50.0 FREQUENCY (MHz) TBD 0 -10 IOH (mA) OUTPUT SOURCE CURRENT VS. SUPPLY VOLTAGE (V OH = 2.4V) 0.0 -10.0 -20.0 OUTPUT SOURCE CURRENT VS. OUTPUT VOLTAGE (VCC = 5.0V, T A = 25°C) -30 -40 -50 4.0 4.5 TBD IOH (mA) -20 -30.0 -40.0 -50.0 -60.0 -70.0 -80.0 -90.0 TBD 5.0 SUPPLY VOLTAGE (V) 5.5 6.0 0.00 0.50 1.00 1.50 2.00 2.50 VOH (V) 3.00 3.50 4.00 4.50 5.00 48 46 Iol (mA) OUTPUT SINK CURRENT VS. SUPPLY VOLTAGE (V OL = 0.5V) OUTPUT SINK CURRENT VS. OUTPUT VOLTAGE (VCC = 5.0V, TA = 25°C) 140.0 120.0 100.0 44 42 40 38 36 4.0 4.5 5.0 SUPPLY VOLTAGE (V) 5.5 6.0 TBD IOL (mA) 80.0 60.0 40.0 20.0 0.0 TBD 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 SUPPLY VOLTAGE (V) 40 ATF1508SE(L) 2401D–PLD–09/02 ATF1508SE(L) INPUT CLAMP CURRENT VS. INPUT VOLTAGE (V CC = 5.0V, TA = 35°C) INPUT CURRENT (uA) 0 INPUT CURRENT (mA) -20 -40 -60 -80 -100 -120 0.0 40 30 20 10 0 -10 -20 -30 0.0 INPUT CURRENT VS. INPUT VOLTAGE (V CC = 5.0V, TA = 25°C) TBD TBD -0.2 -0.4 -0.6 INPUT VOLTAGE (V) -0.8 -1.0 1.0 2.0 3.0 4.0 INPUT VOLTAGE (V) 5.0 6.0 NORMALIZED TPD VS. VCC 1.2 NORMALIZED TPD NORMALIZED TPD VS. TEMP 1.1 NORMALIZED TPD 1.1 1.0 0.9 0.8 4.5 4.8 5.0 SUPPLY VOLTAGE (V) 5.3 5.5 TBD 1.0 TBD 0.9 0.8 -40.0 0.0 25.0 TEMPERATURE (C) 75.0 1.3 NORMALIZED TCO 1.2 1.1 NORMALIZED TCO VS. VCC 1.1 NORMALIZED TCO NORMALIZED TCO VS. TEMP 1.0 TBD 0.9 TBD 1.0 0.9 0.8 4.5 4.8 5.0 SUPPLY VOLTAGE (V) 5.3 5.5 0.8 -40.0 0.0 25.0 75.0 TEMPERATURE (V) NORMALIZED TSU VS. VCC 1.2 NORMALIZED TSU NORMALIZED TSU VS. TEMP 1.2 NORMALIZED TCO 1.1 1.0 0.9 0.8 -40.0 TBD 1.1 1.0 0.9 0.8 4.5 4.8 5.0 SUPPLY VOLTAGE (V) 5.3 5.5 TBD 0.0 25.0 75.0 TEMPERATURE (C) 41 2401D–PLD–09/02 8 DELTA TPD VS. OUTPUT LOADING 8.00 7.00 DELTA TCO VS. OUTPUT LOADING DELTA T PD (ns) 6 4 DELTA T CO (ns) 6.00 5.00 4.00 3.00 2.00 1.00 TBD 2 0 -2 TBD 0.00 0 50 100 150 200 250 300 50 100 150 200 250 300 OUTPUT LOADING (PF) NUMBER OF OUTPUTS LOADING DELTA TCO VS. # OF OUTPUT SWITCHING 0.0 DELTA TPD (ns) -0.1 -0.2 TBD -0.3 -0.4 -0.5 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 NUMBER OF OUTPUTS SWITCHING DELTA TPD VS. # OF OUTPUT SWITCHING DELTA TCO (ns) 0.0 -0.1 TBD -0.2 -0.3 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 NUMBER OF OUTPUTS SWITCHING 42 ATF1508SE(L) 2401D–PLD–09/02 ATF1508SE(L) ATF1508SE(L) Pinouts 84-lead PLCC – Top View I/O I/O I/O I/O GND I/O I/O I/O VCCINT INPUT/OE2/GCLK2 INPUT/GCLR INPUT/OE1 INPUT/GCLK1 GND I/O/GCLK3 I/O I/O VCCIO I/O I/O I/O 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 I/O I/O I/O I/O I/O GND I/O I/O I/O VCCINT INPUT/OE2/GCLK2 INPUT/GCLR INPUT/OE1 INPUT/GCLK1 GND I/O/GCLK3 I/O I/O VCCIO I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCIO I/O I/O I/O GND VCCINT I/O I/O/PD2 I/O GND I/O I/O I/O I/O I/O VCCIO 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 I/O/PD1 VCCIO I/O/TDI I/O I/O I/O I/O GND I/O I/O I/O I/O/TMS I/O I/O VCCIO I/O I/O I/O I/O I/O GND 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 ATF1504SE(L) ATF1508SE(L) 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 I/O I/O GND I/O/TDO I/O I/O I/O I/O VCCIO I/O I/O I/O I/O/TCK I/O I/O GND I/O I/O I/O I/O I/O 100-lead TQFP – Top View I/O/PD1 I/O VCCIO I/O/TDI I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O/TMS I/O I/O VCCIO I/O I/O I/O I/O I/O I/O I/O 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 ATF1508SE(L) 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 I/O GND I/O/TDO I/O I/O I/O I/O I/O I/O VCCIO I/O I/O I/O I/O/TCK I/O I/O GND I/O I/O I/O I/O I/O I/O I/O VCCIO GND I/O I/O I/O I/O I/O I/O I/O VCCIO I/O I/O I/O GND VCCINT I/O I/O/PD2 I/O GND I/O I/O I/O I/O I/O I/O I/O 26 27 28 29 30 31 33 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 43 2401D–PLD–09/02 100-lead PQFP – Top View I/O I/O I/O GND I/O I/O I/O VCCINT INPUT/OE2/GCLK2 INPUT/GCLR INPUT/OE1 INPUT/GCLK1 GND I/O/GCLK3 I/O I/O VCCIO I/O I/O I/O 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC NC I/O I/O VCCIO I/O/TDI NC I/O NC I/O I/O I/O GND I/O/PD1 I/O I/O I/O/TMS I/O I/O VCCIO I/O I/O I/O NC I/O NC I/O GND NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 NC NC I/O I/O GND I/O/TDO NC I/O NC I/O I/O I/O VCCIO I/O I/O I/O I/O/TCK I/O I/O GND I/O I/O I/O NC I/O NC I/O VCCIO NC NC 160 141 I/O I/O I/O I/O I/O VCCIO I/O I/O I/O GND VCCINT I/O I/O I/O/PD2 GND I/O I/O I/O I/O I/O 160-lead TQFP – Top View 1 120 20 ATF1508SE(L) 101 41 60 44 ATF1508SE(L) 2401D–PLD–09/02 80 ATF1508SE(L) ATF1508SE(L) Dedicated Pinouts Dedicated Pin INPUT/GCLK1 INPUT/GCLR INPUT/OE1 INPUT/OE2/GCK2 I/O/GCLK3 I/O PD (1,2) TDI (JTAG) TMS (JTAG) TCK (JTAG) TDO (JTAG) GNDINT GNDIO VCCINT VCCIO No Connect 84-PLCC JLead 83 1 84 2 81 12, 45 14 23 62 71 42, 82 7, 19, 32, 47, 59, 72 3, 43 13, 26, 38, 53, 66, 78 100-pin TQFP 87 89 88 90 85 1,41 4 15 62 73 38,86 11, 26, 43, 59, 74, 95 39, 91 3, 18, 34, 51, 66, 82 100-pin PQFP 89 91 90 92 87 3, 43 6 17 64 75 40,88 13, 28, 61, 76, 45, 97 41,93 5,20,36,53,68,84 160-lead PQFP 139 141 140 142 137 63,159 9 22 99 112 60,138 17, 42,113, 66, 95,148 61,143 8,26,55,79,104,133 1,2,3,4,5,6,7,34,35,36, 37,38,39,40,44,45,46, 47,74,75,76,77,81,82, 83,84,85,86,87,114, 115,116,117,118,119, 120,124,125,126,127, 154,155,156,157 100 96 – # of Signal pins # of User I/O pins 68 64 84 80 84 80 OE (1,2) Global OE pins. GCLR Global Clear pin. GCLK (1,2,3) Global Clock pins. TDI, TMS, TCK, TDO JTAG pins used for In System Programming or Boundary-scan Testing. GNDINT Ground pins for the internal device logic. GNDIO Ground pins for the I/O drivers. VCCINT VCC pins for the internal device logic. VCCIO VCC pins for the I/O drivers. 45 2401D–PLD–09/02 ATF1508SE(L) I/O Pinouts MC 1 2 3/PD1 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32/ TDI PLB A A A A A A A A A A A A A A A A B B B B B B B B B B B B B B B B/ 84-PLCC J-lead – – 12 – 11 10 – 9 – – 8 – 6 5 – 4 22 – 21 – 20 – – 18 17 – 16 – 15 – – 14 100-lead PQFP 4 – 3 – 2 1 – 100 99 – 98 – 96 95 – 94 16 – 15 – 14 12 – 11 10 – 9 – 8 7 – 6 100-lead TQFP 2 – 1 – 100 99 – 98 97 – 96 – 94 93 – 92 14 – 13 – 12 10 – 9 8 – 7 – 6 5 – 4 160-lead PQFP 160 – 159 158 153 152 – 151 150 – 149 147 146 145 – 144 21 – 20 19 18 16 – 15 14 – 13 12 11 10 – 9 MC 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48/TMS 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 PLB C C C C C C C C C C C C C C C C D D D D D D D D D D D D D D D D 84-PLCC J-lead – – 31 – 30 29 – 28 – – 27 – 25 24 – 23 41 – 40 – 39 – – 37 36 – 35 – 34 – – 33 100-lead PQFP 27 – 26 – 25 24 – 23 22 – 21 – 19 18 – 17 39 – 38 – 37 35 – 34 33 – 32 – 31 30 – 29 100-lead TQFP 25 – 24 – 23 22 – 21 20 – 19 – 17 16 – 15 37 – 36 – 35 33 – 32 31 – 30 – 29 28 – 27 160-lead PQFP 41 – 33 32 31 30 – 29 28 – 27 25 24 23 – 22 59 – 58 57 56 54 – 53 52 – 51 50 49 48 – 43 46 ATF1508SE(L) 2401D–PLD–09/02 ATF1508SE(L) ATF1508SE(L) I/O Pinouts (Continued) MC 65 66 67/PD2 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 PLB E E E E E E E E E E E E E E E E F F F F F F F F F F F F F F F F/ TCK 84-PLCC J-lead 44 – 45 – 46 – – 48 49 – 50 – 51 – – 52 – – 54 – 55 56 – 57 – – 58 – 60 61 – 62 100-lead PQFP 42 – 43 – 44 46 – 47 48 – 49 – 50 51 – 52 54 – 55 – 56 57 – 58 59 – 60 – 62 63 – 64 100-lead TQFP 40 – 41 – 42 44 – 45 46 – 47 – 48 49 – 50 52 – 53 – 54 55 – 56 57 – 58 – 60 61 – 62 160-lead PQFP 62 – 63 64 65 67 – 68 69 – 70 71 72 73 – 78 80 – 88 89 90 91 – 92 93 – 94 96 97 98 – 99 MC 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112/ TDO 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128/GCLK3 PLB G G G G G G G G G G G G G G G G H H H H H H H H H H H H H H H H 84-PLCC J-lead 63 – 64 – 65 – – 67 68 – 69 – 70 – – 71 – – 73 – 74 75 – 76 – – 77 – 79 80 – 81 100-lead PQFP 65 – 66 – 67 69 – 70 71 – 72 – 73 74 – 75 77 – 78 – 79 80 – 81 82 – 83 – 85 86 – 87 100-lead TQFP 63 – 64 – 65 67 – 68 69 – 70 – 71 72 – 73 75 – 76 – 77 78 – 79 80 – 81 – 83 84 – 85 160-lead PQFP 100 – 101 102 103 105 – 106 107 – 108 109 110 111 – 112 121 – 122 123 128 129 – 130 131 – 132 134 135 136 – 137 47 2401D–PLD–09/02 ATF1508SE(L) Ordering Information tPD (ns) 6.0 tCO1 (ns) 4.0 fMAX (MHz) 167 Ordering Code ATF1508SE-5 ATF1508SE-5 ATF1508SE-5 ATF1508SE-5 ATF1508SE-7 ATF1508SE-7 ATF1508SE-7 ATF1508SE-7 ATF1508SE-7 ATF1508SE-7 ATF1508SE-7 ATF1508SE-7 10 5.0 125 JC84 AC100 QC100 QC160 JC84 AC100 QC100 QC160 JI84 AI100 QI100 QI160 Package 84J 100A 100Q4 160Q1 84J 100A 100Q4 160Q1 84J 100A 100Q4 160Q1 84J 100A 100Q4 160Q1 84J 100A 100Q4 160Q1 84J 100A 100Q4 160Q1 Operation Range Commercial (0°C to 70°C) 7.5 4.5 167 Commercial (0°C to 70°C) Industrial (-40°C to +85°C) ATF1508SE-10 JC84 ATF1508SE-10 AC100 ATF1508SE-10 QC100 ATF1508SE-10 QC160 ATF1508SE-10 JI84 ATF1508SE-10 AI100 ATF1508SE-10 QI100 ATF1508SE-10 QI160 Commercial (0°C to 70°C) Industrial (-40°C to +85°C) 15 8.0 100 ATF1508SEL-15 JC84 ATF1508SEL-15 AC100 ATF1508SEL-15 QC100 ATF1508SEL-15 QC160 Commercial (0°C to 70°C) Using “C” Product for Industrial To use commercial product for industrial temperature ranges, down-grade one speed grade from the “I” to the “C” device and de-rate power by 30%. Package Type 84J 100A 100Q4 160Q1 84-lead, Plastic J-leaded Chip Carrier (PLCC) 100-lead, Very Thin Plastic Gull Wing Quad Flatpack (TQFP) 100-lead, Plastic Quad Pin Flat Package (PQFP) 160-lead, Plastic Quad Pin Flat Package (PQFP) 48 ATF1508SE(L) 2401D–PLD–09/02 ATF1516SE(L) AC Characteristics(1) ATF1516SE(L) SE -7 Symbol tPD1 tPD2 tSU tH tFSU tFH tCO1 tCH tCL tASU tAH tACO1 tACH tACL tCNT fCNT(3) tACNT fACNT(4) fMAX(5) tIN tIO tFIN tSEXP tPEXP tLAD tLAC tIOE tOD1 tOD2 tOD3 Parameter Input or Feedback to Non-registered Output I/O Input or Feedback to Non-registered Feedback Global Clock Setup Time Global Clock Hold Time Global Clock Setup Time of Fast Input Global Clock Hold of Fast Input Global Clock to Output Delay Global Clock High Time Global Clock Low Time Array Clock Setup Time Array Clock Hold Time Array Clock Output Delay Array Clock High Time Array Clock Low Time Minimum Clock Global Period Maximum Internal Global Clock Frequency Minimum Array Clock Period Maximum Internal Array Clock Frequency Maximum Clock Frequency Input Pad and Buffer Delay I/O Input Pad and Buffer Delay Fast Input Delay Foldback Term Delay Cascade Logic Delay Logic Array Delay Logic Control Delay Internal Output Enable Delay Output Buffer and Pad Delay (slow slew rate = OFF; VCCIO = 5V; CL= 35 pF) Output Buffer and Pad Delay (slow slew rate = OFF; VCCIO = 3.3V; CL= 35 pF) Output Buffer and Pad Delay (slow slew rate = ON; VCCIO = 5V or 3.3V; C L= 35 pF) Output Buffer Enable Delay (slow slew rate = OFF; VCCIO = 5V; CL= 35 pF) 130 167 0.3 0.3 3.4 3.9 1.1 2.6 2.6 0.8 0.5 1.0 5.5 130 7.8 100 125 0.5 0.5 1.0 5.0 0.8 5.0 5.0 2.0 1.5 2.0 5.5 3.0 3.0 7.8 100 10 77 100 2.0 2.0 2.0 8.0 1.0 6.0 6.0 3.0 4.0 5.0 8.0 3.0 3.0 0.8 1.9 7.3 3.9 0.0 3.9 0.0 4.7 4.0 4.0 2.0 3.0 1 4 4 10 77 13 10 6 6 13 Min Max 7.5 7.5 7.0 0.0 3.0 0.5 5.0 5.0 5 4.0 4.0 15 SE -10 Min Max 10 10 11 0.0 3.0 1 8.0 SEL -15(6) Min Max 15 12 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz ns MHz MHz ns ns ns ns ns ns ns ns ns ns ns tZX1 4.0 5.0 6.0 ns 49 2401D–PLD–09/02 AC Characteristics(1) ATF1516SE(L) (Continued) SE -7 Symbol tZX2 tZX3 Parameter Output Buffer Enable Delay (slow slew rate = OFF; VCCIO = 3.3V; CL= 35 pF) Output Buffer Enable Delay (slow slew rate = ON; VCCIO = 5V or 3.3V; CL= 35 pF) Output Buffer Disable Delay (C L= 5 pF) Register Setup Time Register Hold Time Register Setup Time of Fast Input Register Hold Time of Fast Input Register Delay Combinatorial Delay Array Clock Delay Register Enable Time Global Control Delay Register Preset Time Register Clear Time Switch Matrix Delay (2) SE -10 Min Max 5.5 9.0 SEL -15(6) Min Max 7.0 10.0 Unit ns ns Min Max 4.5 9.0 tXZ tSU tH tFSU tFH tRD tCOMB tIC tEN tGLOB tPRE tCLR tUIM 4.0 1.1 1.6 2.4 0.6 1.1 1.1 2.9 2.6 2.8 2.7 2.7 3.0 2.0 3.0 3.0 0.5 5.0 4.0 4.0 2.0 1.0 2.0 2.0 5.0 5.0 1.0 3.0 3.0 1.0 6.0 ns ns ns ns ns 1.0 1.0 6.0 6.0 1.0 4.0 4.0 2.0 ns ns ns ns ns ns ns ns tRPA Reduced Power Adder 10 11 13 ns Notes: 1. See ordering Information for valid part numbers. 2. The tRPA parameter must be added to the tLAD, tLAC, tIC, tACL and tSEXP parameters for macrocells running in the reducedpower mode. 3. fCNT is the fastest 16-bit counter frequency available, using the local feedback when applicable, and a PIA fan-out of one logic block (16 macrocells). fCNT is also the Export Control Maximum flip-flop toggle rate, fTOG. 4. fACNT is the fastest 16-bit counter frequency available, using the internal array clock, local feedback when applicable and a PIA fan-out of one logic block (16 macrocells). 5. fMAX is the fastest available frequency for pipelined data. 6. For clocked applications and frequencies above fCRITICAL, OR, non-clocked applications with dormant times less than 1/fCRITICAL, the device will achieve the speeds of the –10 column. See “Input Transition Detection/ Automatic Power Down” on page 8. 50 ATF1516SE(L) 2401D–PLD–09/02 ATF1516SE(L) STAND-BY ICC VS. SUPPLY VOLTAGE (TA = 25°C) 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 4.5 4.8 NORMALIZED Icc 1.4 1.2 1.0 TBD 0.8 0.6 0.4 -40.0 NORMALIZED ICC VS. TEMP ICC (µA) TBD 5.0 SUPPLY VOLTAGE (V) 5.3 5.5 0.0 25.0 75.0 TEMPERATURE (C) SUPPLY CURRENT VS. INPUT FREQUENCY (VCC = 5.0V, TA = 25°C) 140.000 120.000 ICC (mA) 100.000 ICC (mA) 80.000 TBD 60.000 40.000 20.000 0.000 0.0 0.5 2.5 5.0 7.5 10.0 FREQUENCY (MHz) 25.0 37.5 50.0 SUPPLY CURRENT VS. INPUT FREQUENCY (V CC = 5.0V, TA = 25°C) 1.000 0.800 0.600 0.400 0.200 0.000 0.0 0.5 2.5 5.0 7.5 10.0 25.0 37.5 50.0 FREQUENCY (MHz) TBD 0 -10 IOH (mA) -20 -30 -40 -50 4.0 OUTPUT SOURCE CURRENT VS. SUPPLY VOLTAGE (V OH = 2.4V) 0.0 -10.0 -20.0 -30.0 -40.0 -50.0 -60.0 -70.0 -80.0 -90.0 OUTPUT SOURCE CURRENT VS. OUTPUT VOLTAGE (VCC = 5.0V, T A = 25°C) IOH (mA) TBD TBD 4.5 5.0 SUPPLY VOLTAGE (V) 5.5 6.0 0.00 0.50 1.00 1.50 2.00 2.50 VOH (V) 3.00 3.50 4.00 4.50 5.00 48 46 Iol (mA) OUTPUT SINK CURRENT VS. SUPPLY VOLTAGE (V OL = 0.5V) 140.0 120.0 OUTPUT SINK CURRENT VS. OUTPUT VOLTAGE (V CC = 5.0V, TA = 25°C) 44 IOL (mA) 42 40 38 36 4.0 4.5 5.0 SUPPLY VOLTAGE (V) 5.5 6.0 TBD 100.0 80.0 60.0 40.0 20.0 0.0 TBD 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 SUPPLY VOLTAGE (V) 51 2401D–PLD–09/02 0 INPUT CURRENT (mA) -20 -40 -60 -80 -100 -120 0.0 INPUT CLAMP CURRENT VS. INPUT VOLTAGE (VCC = 5.0V, T A = 35°C) INPUT CURRENT (uA) 40 30 20 10 0 -10 -20 -30 0.0 INPUT CURRENT VS. INPUT VOLTAGE (VCC = 5.0V, T A = 25°C) TBD TBD -0.2 -0.4 -0.6 INPUT VOLTAGE (V) -0.8 -1.0 1.0 2.0 3.0 4.0 INPUT VOLTAGE (V) 5.0 6.0 NORMALIZED TPD VS. VCC 1.2 NORMALIZED TPD NORMALIZED T PD VS. TEMP 1.1 NORMALIZED TPD 1.1 1.0 0.9 0.8 4.5 4.8 5.0 SUPPLY VOLTAGE (V) 5.3 5.5 TBD 1.0 TBD 0.9 0.8 -40.0 0.0 25.0 TEMPERATURE (C) 75.0 1.3 NORMALIZED TCO 1.2 1.1 NORMALIZED TCO VS. VCC 1.1 NORMALIZED TCO NORMALIZED T CO VS. TEMP 1.0 TBD 0.9 TBD 1.0 0.9 0.8 4.5 4.8 5.0 SUPPLY VOLTAGE (V) 5.3 5.5 0.8 -40.0 0.0 25.0 75.0 TEMPERATURE (V) NORMALIZED TSU VS. VCC 1.2 NORMALIZED TSU NORMALIZED TSU VS. TEMP 1.2 NORMALIZED TCO 1.1 1.0 0.9 0.8 -40.0 TBD 1.1 1.0 0.9 0.8 4.5 4.8 5.0 SUPPLY VOLTAGE (V) 5.3 5.5 TBD 0.0 25.0 75.0 TEMPERATURE (C) 52 ATF1516SE(L) 2401D–PLD–09/02 ATF1516SE(L) 8 DELTA TPD VS. OUTPUT LOADING 8.00 7.00 DELTA TCO VS. OUTPUT LOADING DELTA T PD (ns) 6 4 DELTA T CO (ns) 6.00 5.00 4.00 3.00 2.00 1.00 TBD 2 0 -2 TBD 0.00 0 50 100 150 200 250 300 50 100 150 200 250 300 OUTPUT LOADING (PF) NUMBER OF OUTPUTS LOADING DELTA TCO VS. # OF OUTPUT SWITCHING 0.0 DELTA TPD (ns) -0.1 -0.2 TBD -0.3 -0.4 -0.5 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 NUMBER OF OUTPUTS SWITCHING DELTA TPD VS. # OF OUTPUT SWITCHING DELTA TCO (ns) 0.0 -0.1 TBD -0.2 -0.3 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 NUMBER OF OUTPUTS SWITCHING 53 2401D–PLD–09/02 ATF1516SE(L) Dedicated Pinouts 208-lead PQFP and RQFP – Top View 208 183 1 156 26 ATF1516SE(L) 131 54 ATF1516SE(L) 2401D–PLD–09/02 104 53 78 ATF1516SE(L) ATF1516SE(L) Dedicated Pinouts Dedicated Pin INPUT/GCLK1 INPUT/GCLR INPUT/OE1 INPUT/OE2/GCK2 I/O/GCLK3 I/O PD (1,2) TDI (JTAG) TMS (JTAG) TCK (JTAG) TDO (JTAG) GNDINT GNDIO VCCINT VCCIO No Connect # of Signal pins # of User I/O pins 208-pin PQFP 184 182 183 181 TBD TBD 176 127 30 189 75, 82, 180, 185 14, 32, 50, 72, 94, 116, 134, 152, 174, 200 74, 83, 179, 186 5, 23, 41, 63, 85, 107, 125, 143, 165, 191 1,2, 51, 52, 53, 54, 103, 104, 105, 106, 155, 156, 157, 158, 207, 208 164 160 208-pin RQFP 184 182 183 181 TBD TBD 176 127 30 189 75, 82, 180, 185 14, 32, 50, 72, 94, 116, 134, 152, 174, 200 74, 83, 179, 186 5, 23, 41, 63, 85, 107, 125, 143, 165, 191 1,2, 51, 52, 53, 54, 103, 104, 105, 106, 155, 156, 157, 158, 207, 208 164 160 OE (1,2) Global OE pins. GCLR Global Clear pin. GCLK (1,2,3) Global Clock pins. TDI, TMS, TCK, TDO JTAG pins used for In System Programming or Boundary-scan Testing. GNDINT Ground pins for the internal device logic. GNDIO Ground pins for the I/O drivers. VCCINT VCC pins for the internal device logic. VCCIO VCC pins for the I/O drivers. 55 2401D–PLD–09/02 ATF1516SE(L) I/O Pinouts MC PLB 208-pin PQFP 208-pin RQRP MC PLB 208-pin PQFP 208-pin RQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 A A A A A A A A A A A A A A A A B B B B B B B B B B B B B B B B 153 154 159 160 161 162 163 164 166 167 141 142 144 145 146 147 148 149 150 151 153 154 159 160 161 162 163 164 166 167 141 142 144 145 146 147 148 149 150 151 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 C C C C C C C C C C C C C C C C D D D D D D D D D D D D D D D D 108 109 110 111 112 113 114 115 117 118 92 93 95 96 97 98 99 100 101 102 108 109 110 111 112 113 114 115 117 118 92 93 95 96 97 98 99 100 101 102 56 ATF1516SE(L) 2401D–PLD–09/02 ATF1516SE(L) ATF1516SE(L) I/O Pinouts (Continued) MC PLB 208-pin PQFP 208-pin RQRP MC PLB 208-pin PQFP 208-pin RQFP 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 E E E E E E E E E E E E E E E E F F F F F F F F F F F F F F F F 168 169 170 171 172 173 175 176 177 178 130 131 132 133 135 136 137 138 139 140 168 169 170 171 172 173 175 176 177 178 130 131 132 133 135 136 137 138 139 140 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 G G G G G G G G G G G G G G G G H H H H H H H H H H H H H H H H 119 120 121 122 123 124 126 127 128 129 79 80 81 84 86 87 88 89 90 91 119 120 121 122 123 124 126 127 128 129 79 80 81 84 86 87 88 89 90 91 57 2401D–PLD–09/02 ATF1516SE(L) I/O Pinouts (Continued) MC PLB 208-pin PQFP 208-pin RQRP MC PLB 208-pin PQFP 208-pin RQFP 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 I I I I I I I I I I I I I I I I J J J J J J J J J J J J J J J J 197 196 195 194 193 192 190 189 188 187 27 26 25 24 22 21 20 19 18 17 197 196 195 194 193 192 190 189 188 187 27 26 25 24 22 21 20 19 18 17 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 K K K K K K K K K K K K K K K K L L L L L L L L L L L L L L L L 38 37 36 35 34 33 31 30 29 28 78 77 76 73 71 70 69 68 67 66 38 37 36 35 34 33 31 30 29 28 78 77 76 73 71 70 69 68 67 66 58 ATF1516SE(L) 2401D–PLD–09/02 ATF1516SE(L) ATF1516SE(L) I/O Pinouts (Continued) MC PLB 208-pin PQFP 208-pin RQRP MC PLB 208-pin PQFP 208-pin RQFP 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 M M M M M M M M M M M M M M M M N N N N N N N N N N N N N N N N 4 3 206 205 204 203 202 201 199 198 16 15 13 12 11 10 9 8 7 6 4 3 206 205 204 203 202 201 199 198 16 15 13 12 11 10 9 8 7 6 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 O O O O O O O O O O O O O O O O P P P P P P P P P P P P P P P P 49 48 47 46 45 44 43 42 40 39 65 64 62 61 60 59 58 57 56 55 49 48 47 46 45 44 43 42 40 39 65 64 62 61 60 59 58 57 56 55 59 2401D–PLD–09/02 ATF1516SE(L) Ordering Information tPD (ns) 7.5 tCO1 (ns) 4.7 fMAX (MHz) 167 Ordering Code ATF1516SE-7 QC208 ATF1516SE-7 RC208 ATF1516SE-7 QI208 ATF1516SE-7 RI208 10 5.0 125 ATF1516SE-10 QC208 ATF1516SE-10 RC208 ATF1516SE-10 QI208 ATF1516SE-10 RI208 15 8.0 100 ATF1516SEL-15 QC208 ATF1516SEL-15 RC208 Package 208Q1 208Q2 208Q1 208Q2 208Q1 208Q2 208Q1 208Q2 208Q1 208Q2 Operation Range Commercial (0°C to 70°C) Industrial (-40°C to +85°C) Commercial (0°C to 70°C) Industrial (-40°C to +85°C) Commercial (0°C to 70°C) Using “C” Product for Industrial To use commercial product for industrial temperature ranges, down-grade one speed grade from the “I” to the “C” device, and de-rate power by 30%. Package Type 208Q1 208Q2 208-lead, 28 x 28 mm Body, 2.6 Form Opt., Plastic Quad Flatpack (PQFP) 208-lead, 28 x 28 mm Body, 2.6 Form Opt., Plastic Quad Flatpack with Heat Spreader (PQFP) 60 ATF1516SE(L) 2401D–PLD–09/02 ATF1516SE(L) Package Information 44A – TQFP PIN 1 B PIN 1 IDENTIFIER e E1 E D1 D C 0˚~7˚ A1 L COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E MIN – 0.05 0.95 11.75 9.90 11.75 9.90 0.30 0.09 0.45 NOM – – 1.00 12.00 10.00 12.00 10.00 – – – 0.80 TYP MAX 1.20 0.15 1.05 12.25 10.10 12.25 10.10 0.45 0.20 0.75 Note 2 Note 2 NOTE A2 A Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. E1 B C L e 10/5/2001 2325 Orchard Parkway San Jose, CA 95131 TITLE 44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) DRAWING NO. 44A REV. B R 61 2401D–PLD–09/02 44J – PLCC 1.14(0.045) X 45° PIN NO. 1 IDENTIFIER 1.14(0.045) X 45° 0.318(0.0125) 0.191(0.0075) E1 B E B1 D2/E2 e D1 D A A2 A1 0.51(0.020)MAX 45° MAX (3X) COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E Notes: 1. This package conforms to JEDEC reference MS-018, Variation AC. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. E1 D2/E2 B B1 e MIN 4.191 2.286 0.508 17.399 16.510 17.399 16.510 14.986 0.660 0.330 NOM – – – – – – – – – – 1.270 TYP MAX 4.572 3.048 – 17.653 16.662 17.653 16.662 16.002 0.813 0.533 Note 2 Note 2 NOTE 10/04/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC) DRAWING NO. 44J REV. B R 62 ATF1516SE(L) 2401D–PLD–09/02 ATF1516SE(L) 84J – PLCC 1.14(0.045) X 45° PIN NO. 1 IDENTIFIER 1.14(0.045) X 45° 0.318(0.0125) 0.191(0.0075) E1 B E B1 D2/E2 e D1 D A A2 A1 0.51(0.020)MAX 45° MAX (3X) COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E Notes: 1. This package conforms to JEDEC reference MS-018, Variation AF. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. E1 D2/E2 B B1 e MIN 4.191 2.286 0.508 30.099 29.210 30.099 29.210 27.686 0.660 0.330 NOM – – – – – – – – – – 1.270 TYP MAX 4.572 3.048 – 30.353 29.413 30.353 29.413 28.702 0.813 0.533 Note 2 Note 2 NOTE 10/04/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 84J, 84-lead, Plastic J-leaded Chip Carrier (PLCC) DRAWING NO. 84J REV. B R 63 2401D–PLD–09/02 100A – TQFP PIN 1 B PIN 1 IDENTIFIER e E1 E D1 D C 0˚~7˚ A1 L COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E MIN – 0.05 0.95 15.75 13.90 15.75 13.90 0.17 0.09 0.45 NOM – – 1.00 16.00 14.00 16.00 14.00 – – – 0.50 TYP MAX 1.20 0.15 1.05 16.25 14.10 16.25 14.10 0.27 0.20 0.75 Note 2 Note 2 NOTE A2 A Notes: 1. This package conforms to JEDEC reference MS-026, Variation AED. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.08 mm maximum. E1 B C L e 10/5/2001 2325 Orchard Parkway San Jose, CA 95131 TITLE 100A, 100-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness, 0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) DRAWING NO. 100A REV. C R 64 ATF1516SE(L) 2401D–PLD–09/02 ATF1516SE(L) 100Q4 – PQFP D1 D E1 E Top View Bottom View A2 A1 e b L1 COMMON DIMENSIONS (Unit of Measure = mm) Side View Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MS-022, Variation GC-1, for additional information. 2. To be determined at seating plane. 3. Regardless of the relative size of the upper and lower body sections, dimensions D1 and E1 are determined at the largest feature of the body exclusive of mold Flash and gate burrs, but including any mismatch between the upper and lower sections of the molded body. 4. Dimension b does not include Dambar protrusion. The Dambar protrusion(s) shall not cause the lead width to exceed b maximum by more than 0.08 mm. Dambar cannot be located on the lower radius or the lead foot. 5. A1 is defined as the distance from the seating plane to the lowest point of the package body. SYMBOL A1 A2 D D1 E E1 e b L1 MIN 0.25 2.50 NOM – 2.70 23.20 BSC 20.00 BSC 17.20 BSC 14.00 BSC 0.65 BSC MAX 0.50 2.90 NOTE 5 2 3 2 3 0.22 1.60 REF 0.40 4 3/29/02 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 100Q4, 100-lead, 14 x 20 mm Body, 3.2 Form Opt., Plastic Quad Flat Pack (PQFP) DRAWING NO. 100Q4 REV. A 65 2401D–PLD–09/02 160Q1 – PQFP D1 D E1 E Top View A2 Bottom View A1 e b L1 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN 0.25 3.20 NOM – 3.40 31.20 BSC 28.00 BSC 31.20 BSC 28.00 BSC 0.65 BSC 0.22 – 1.60 REF 0.40 4 MAX 0.50 3.60 2 3 2 3 NOTE 5 Side View Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MS-022, Variation DD-1, for additional information. 2. To be determined at seating plane. 3. Regardless of the relative size of the upper and lower body sections, dimensions D1 and E1 are determined at the largest feature of the body exclusive of mold Flash and gate burrs, but including any mismatch between the upper and lower sections of the molded body. 4. Dimension b does not include Dambar protrusion. The Dambar protrusion(s) shall not cause the lead width to exceed b maximum by more than 0.08 mm. Dambar cannot be located on the lower radius or the lead foot. 5. A1 is defined as the distance from the seating plane to the lowest point of the package body. A1 A2 D D1 E E1 e b L1 3/28/02 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 160Q1, 160-lead, 28 x 28 mm Body, 3.2 Form Opt., Plastic Quad Flat Pack (PQFP) DRAWING NO. 160Q1 REV. A 66 ATF1516SE(L) 2401D–PLD–09/02 ATF1516SE(L) 208Q1 – PQFP D1 A2 L1 E1 A1 Side View e b Top View D COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A1 A2 MIN 0.25 3.20 NOM MAX 0.50 3.60 NOTE – 3.40 30.60 BSC 28.00 BSC 30.60 BSC 28.00 BSC 0.50 BSC E D D1 E E1 e b L1 0.17 2, 3 2, 3 – 1.30 REF 0.27 4 Bottom View Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-129, Variation FA-1, for proper dimensions, tolerances, datums, etc. 2. The top package body size may be smaller than the bottom package size by as much as 0.15 mm. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable protrusion is 0.25 mm per side. D1 and E1 are maximum plastic body size dimensions including mold mismatch. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08 mm. Dambar cannot be located on the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07 mm. 07/23/02 2325 Orchard Parkway San Jose, CA 95131 TITLE 208Q1, 208-lead (28 x 28 mm Body, 2.6 Form Opt.), Plastic Quad Flat Pack (PQFP) DRAWING NO. 208Q1 REV. B R 67 2401D–PLD–09/02 208Q2 – PQFP D1 A2 L1 E1 A1 Side View e b Top View D COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A1 A2 MIN 0.05 3.20 NOM MAX 0.25 3.60 NOTE – 3.40 30.60 BSC 28.00 BSC 30.60 BSC 28.00 BSC 0.50 BSC E D D1 E E1 e b L1 0.17 2, 3 2, 3 – 1.30 REF 0.27 4 Bottom View Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-129, Variation FA-2, for proper dimensions, tolerances, datums, etc. 2. The top package body size may be smaller than the bottom package size by as much as 0.15 mm. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable protrusion is 0.25 mm per side. D1 and E1 are maximum plastic body size dimensions including mold mismatch. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08 mm. Dambar cannot be located on the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07 mm. 07/23/02 2325 Orchard Parkway San Jose, CA 95131 TITLE 208Q2, 208-lead (28 x 28 mm Body, 2.6 Form Opt.), Plastic Quad Flat Pack (PQFP) DRAWING NO. 208Q2 REV. A R 68 ATF1516SE(L) 2401D–PLD–09/02 Atmel Headquarters Corporate Headquarters 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 487-2600 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany TEL (49) 71-31-67-0 FAX (49) 71-31-67-2340 1150 East Cheyenne Mtn. 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Blvd. Colorado Springs, CO 80906 TEL 1(719) 576-3300 FAX 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland TEL (44) 1355-803-000 FAX (44) 1355-242-743 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 e-mail literature@atmel.com Web Site http://www.atmel.com © Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. ATMEL ® is the registered trademark of Atmel; Logic Doubling ™ is the trademark of Atmel. Other terms and product names may be the trademarks of others. Printed on recycled paper. 2401D–PLD–09/02 xM