ATF1508AS

Features • High-density, High-performance, Electrically-erasable Complex Programmable Logic Device – 128 Macrocells – 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell – 84, 100, 160 Pins – 7.5 ns Maximum Pin-to-pin Delay – Registered Operation up to 125 MHz – Enhanced Routing Resources Flexible Logic Macrocell – D/T/Latch Configured Flip-flops – Global and Individual Register Control Signals – Global and Individual Output Enable – Programmable Output Slew Rate – Programmable Output Open Collector Option – Maximum Logic Utilization by Burying a Register within a COM Output Advanced Power Management Features – Automatic 10 µA Standby for “L” Version – Pin-controlled 1 mA Standby Mode – Programmable Pin-keeper Inputs and I/Os – Reduced-power Feature per Macrocell Available in Commercial and Industrial Temperature Ranges Available in 84-lead PLCC, 100-lead PQFP, 100-lead TQFP and 160-lead PQFP Packages Advanced EE Technology – 100% Tested – Completely Reprogrammable – 10,000 Program/Erase Cycles – 20-year Data Retention – 2000V ESD Protection – 200 mA Latch-up Immunity JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported Fast In-System Programmability (ISP) via JTAG PCI-compliant 3.3 or 5.0V I/O Pins Security Fuse Feature Green (Pb/Halide-free/RoHS Compliant) Package Options • Highperformance EE PLD ATF1508AS ATF1508ASL • • • • • • • • • • Enhanced Features • • • • • • • • • • • Improved Connectivity (Additional Feedback Routing, Alternate Input Routing) Output Enable Product Terms Transparent-latch Mode Combinatorial Output with Registered Feedback within Any Macrocell Three Global Clock Pins ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O Fast Registered Input from Product Term Programmable “Pin-keeper” Option VCC Power-up Reset Option Pull-up Option on JTAG Pins TMS and TDI Advanced Power Management Features – Edge-controlled Power-down “L” – Individual Macrocell Power Option – Disable ITD on Global Clocks, Inputs and I/O for “Z” Parts Rev. 0784P–PLD–7/05 1 84-lead PLCC Top View I/O I/O I/O I/O GND I/O I/O I/O VCCINT INPUT/OE2/GCLK2 INPUT/GCLR INPUT/OE1 INPUT/GCLK1 GND I/O/GCLK3 I/O I/O VCCIO I/O I/O I/O 100-lead PQFP Top View I/O I/O I/O GND I/O I/O I/O VCCINT INPUT/OE2/GCLK2 INPUT/GCLR INPUT/OE1 INPUT/GCLK1 GND I/O/GCLK3 I/O I/O VCCIO I/O I/O I/O 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 I/O I/O I/O I/O I/O VCCIO I/O I/O I/O GND VCCINT I/O I/O/PD2 I/O GND I/O I/O I/O I/O I/O VCCIO 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 I/O/PD1 VCCIO I/O/TDI I/O I/O I/O I/O GND I/O I/O I/O I/O/TMS I/O I/O VCCIO I/O I/O I/O I/O I/O GND 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 I/O I/O GND I/O/TDO I/O I/O I/O I/O VCCIO I/O I/O I/O I/O/TCK I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O/PD1 I/O VCCIO I/O/TDI I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O/TMS I/O I/O VCCIO I/O I/O I/O I/O I/O I/O I/O GND I/O I/O 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 I/O I/O I/O I/O GND I/O/TDO I/O I/O I/O I/O I/O I/O VCCIO I/O I/O I/O I/O/TCK I/O I/O GND I/O I/O I/O I/O I/O I/O I/O VCCIO I/O I/O 100-lead TQFP Top View I/O I/O I/O I/O I/O GND I/O I/O I/O VCCINT INPUT/OE2/GCLK2 INPUT/GCLR INPUT/OE1 INPUT/GCLK1 GND I/O/GCLK3 I/O I/O VCCIO I/O I/O I/O I/O I/O I/O 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 I/O I/O/PD2 I/O N/C N/C N/C N/C I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCCINT INPUT/OE2/GCLK2 INPUT/GCLR INPUT/OE1 INPUT/GCLK1 GND I/O/GCLK3 I/O I/O I/O VCCIO I/O I/O I/O I/O I/O N/C N/C N/C N/C I/O I/O I/O I/O I/O I/O I/O I/O VCCIO I/O I/O I/O GND VCCINT I/O I/O/PD2 I/O GND I/O I/O I/O I/O I/O 160-lead PQFP Top View I/O/PD1 I/O VCCIO I/O/TDI I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O/TMS I/O I/O VCCIO I/O I/O I/O I/O I/O I/O I/O 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 I/O GND I/O/TDO I/O I/O I/O I/O I/O I/O VCCIO I/O I/O I/O I/O/TCK I/O I/O GND I/O I/O I/O I/O I/O I/O I/O VCCIO N/C N/C N/C N/C N/C N/C N/C VCCIO I/O/TDI I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O/TMS I/O I/O I/O VCCIO I/O I/O I/O I/O I/O I/O I/O N/C N/C N/C N/C N/C N/C N/C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 N/C N/C N/C N/C N/C N/C N/C GND I/O/TDO I/O I/O I/O I/O I/O I/O I/O VCCIO I/O I/O I/O I/O I/O/TCK I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O N/C N/C N/C N/C N/C N/C N/C GND I/O I/O I/O I/O I/O I/O I/O VCCIO I/O I/O I/O GND VCCINT I/O I/O/PD2 I/O GND I/O I/O I/O I/O I/O I/O I/O 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 2 ATF1508AS(L) 0784P–PLD–7/05 I/O GND I/O N/C N/C N/C N/C I/O I/O I/O I/O I/O I/O I/O VCCIO I/O I/O I/O I/O GND VCCINT I/O I/O/PD1 I/O I/O GND I/O I/O I/O I/O I/O I/O I/O N/C N/C N/C N/C I/O VCCIO I/O ATF1508AS(L) Block Diagram 8 to 12 16 3 0784P–PLD–7/05 Description The ATF1508AS is a high-performance, high-density complex programmable logic device (CPLD) that utilizes Atmel’s proven electrically-erasable technology. With 128 logic macrocells and up to 100 inputs, it easily integrates logic from several TTL, SSI, MSI, LSI and classic PLDs. The ATF1508AS’s enhanced routing switch matrices increase usable gate count and increase odds of successful pin-locked design modifications. The ATF1508AS has up to 96 bi-directional I/O pins and four dedicated input pins, depending on the type of device package selected. Each dedicated pin can also serve as a global control signal, register clock, register reset or output enable. Each of these control signals can be selected for use individually within each macrocell. Each of the 128 macrocells generates a buried feedback that goes to the global bus. Each input and I/O pin also feeds into the global bus. The switch matrix in each logic block then selects 40 individual signals from the global bus. Each macrocell also generates a foldback logic term that goes to a regional bus. Cascade logic between macrocells in the ATF1508AS allows fast, efficient generation of complex logic functions. The ATF1508AS contains eight such logic chains, each capable of creating sum term logic with a fan-in of up to 40 product terms. The ATF1508AS macrocell, shown in Figure 1, is flexible enough to support highly-complex logic functions operating at high speed. The macrocell consists of five sections: product terms and product term select multiplexer; OR/XOR/CASCADE logic, a flip-flop, output select and enable, and logic array inputs. Unused macrocells are automatically disabled by the compiler to decrease power consumption. A security fuse, when programmed, protects the contents of the ATF1508AS. Two bytes (16 bits) of User Signature are accessible to the user for purposes such as storing project name, part number, revision or date. The User Signature is accessible regardless of the state of the security fuse. The ATF1508AS device is an in-system programmable (ISP) device. It uses the industry-standard 4-pin JTAG interface (IEEE Std. 1149.1), and is fully compliant with JTAG’s Boundaryscan Description Language (BSDL). ISP allows the device to be programmed without removing it from the printed circuit board. In addition to simplifying the manufacturing flow, ISP also allows design modifications to be made in the field via software. Product Terms and Select Mux Each ATF1508AS macrocell has five product terms. Each product term receives as its inputs all signals from both the global bus and regional bus. The product term select multiplexer (PTMUX) allocates the five product terms as needed to the macrocell logic gates and control signals. The PTMUX programming is determined by the design compiler, which selects the optimum macrocell configuration. OR/XOR/ CASCADE Logic The ATF1508AS’s logic structure is designed to efficiently support all types of logic. Within a single macrocell, all the product terms can be routed to the OR gate, creating a 5-input AND/OR sum term. With the addition of the CASIN from neighboring macrocells, this can be expanded to as many as 40 product terms with a little small additional delay. The macrocell’s XOR gate allows efficient implementation of compare and arithmetic functions. One input to the XOR comes from the OR sum term. The other XOR input can be a product term or a fixed high- or low-level. For combinatorial outputs, the fixed level input allows polarity selection. For registered functions, the fixed levels allow DeMorgan minimization of product terms. The XOR gate is also used to emulate T- and JK-type flip-flops. 4 ATF1508AS(L) 0784P–PLD–7/05 ATF1508AS(L) Flip-flop The ATF1508AS’s flip-flop has very flexible data and control functions. The data input can come from either the XOR gate, from a separate product term or directly from the I/O pin. Selecting the separate product term allows creation of a buried registered feedback within a combinatorial output macrocell. (This feature is automatically implemented by the fitter software). In addition to D, T, JK and SR operation, the flip-flop can also be configured as a flowthrough latch. In this mode, data passes through when the clock is high and is latched when the clock is low. The clock itself can be either the Global CLK Signal (GCK) or an individual product term. The flip-flop changes state on the clock’s rising edge. When the GCK signal is used as the clock, one of the macrocell product terms can be selected as a clock enable. When the clock enable function is active and the enable signal (product term) is low, all clock edges are ignored. The flip-flop’s asynchronous reset signal (AR) can be either the Global Clear (GCLEAR), a product term, or always off. AR can also be a logic OR of GCLEAR with a product term. The asynchronous preset (AP) can be a product term or always off. Extra Feedback The ATF15xxSE Family macrocell output can be selected as registered or combinatorial. The extra buried feedback signal can be either combinatorial or a registered signal regardless of whether the output is combinatorial or registered. (This enhancement function is automatically implemented by the fitter software.) Feedback of a buried combinatorial output allows the creation of a second latch within a macrocell. The output enable multiplexer (MOE) controls the output enable signal. Each I/O can be individually configured as an input, output or for bi-directional operation. The output enable for each macrocell can be selected from the true or compliment of the two output enable pins, a subset of the I/O pins, or a subset of the I/O macrocells. This selection is automatically done by the fitter software when the I/O is configured as an input, all macrocell resources are still available, including the buried feedback, expander and cascade logic. The global bus contains all input and I/O pin signals as well as the buried feedback signal from all 128 macrocells. The switch matrix in each logic block receives as its inputs all signals from the global bus. Under software control, up to 40 of these signals can be selected as inputs to the logic block. Each macrocell also generates a foldback product term. This signal goes to the regional bus and is available to 16 macrocells. The foldback is an inverse polarity of one of the macrocell’s product terms. The 16 foldback terms in each region allows generation of high fan-in sum terms (up to 21 product terms) with a little additional delay. The ATF1508AS device has two sets of VCC pins viz, VCCINT and VCCIO. VCCINT pins must always be connected to a 5.0V power supply. VCCINT pins are for input buffers and are “compatible” with both 3.3V and 5.0V inputs. V CCIO p ins are for I/O output drives and can be connected for 3.3/5.0V power supply. This option enables the device output to provide control signals such as an interrupt that can be asserted by any of the several devices. I/O Control Global Bus/Switch Matrix Foldback Bus 3.3V or 5.0V I/O Operation Open-collector Output Option 5 0784P–PLD–7/05 Figure 1. ATF1508AS Macrocell Programmable Pin-keeper Option for Inputs and I/Os Input Diagram The ATF1508AS offers the option of programming all input and I/O pins so that “pin-keeper” circuits can be utilized. When any pin is driven high or low and then subsequently left floating, it will stay at that previous high- or low-level. This circuitry prevents unused input and I/O lines from floating to intermediate voltage levels, which causes unnecessary power consumption and system noise. The keeper circuits eliminate the need for external pull-up resistors and eliminate their DC power consumption. 6 ATF1508AS(L) 0784P–PLD–7/05 ATF1508AS(L) Speed/Power Management The ATF1508AS has several built-in speed and power management features. The ATF1508AS contains circuitry that automatically puts the device into a low-power stand-by mode when no logic transitions are occurring. This not only reduces power consumption during inactive periods, but also provides proportional power-savings for most applications running at system speeds below 5 MHz. To further reduce power, each ATF1508AS macrocell has a Reduced-power bit feature. This feature allows individual macrocells to be configured for maximum power savings. This feature may be selected as a design option. I/O Diagram All ATF1508 also have an optional power-down mode. In this mode, current drops to below 10 mA. When the power-down option is selected, either PD1 or PD2 pins (or both) can be used to power down the part. The power-down option is selected in the design source file. When enabled, the device goes into power-down when either PD1 or PD2 is high. In the power-down mode, all internal logic signals are latched and held, as are any enabled outputs. All pin transitions are ignored until the PD pin is brought low. When the power-down feature is enabled, the PD1 or PD2 pin cannot be used as a logic input or output. However, the pin’s macrocell may still be used to generate buried foldback and cascade logic signals. All power-down AC characteristic parameters are computed from external input or I/O pins, with Reduced-power Bit turned on. For macrocells in reduced-power mode (Reduced-power bit turned on), the reduced-power adder, tRPA, must be added to the AC parameters, which include the data paths tLAD, tLAC, tIC, tACL, tACH and tSEXP. Each output also has individual slew rate control. This may be used to reduce system noise by slowing down outputs that do not need to operate at maximum speed. Outputs default to slow switching, and may be specified as fast switching in the design file. 7 0784P–PLD–7/05 Design Software Support Power-up Reset ATF1508AS designs are supported by several third-party tools. Automated fitters allow logic synthesis using a variety of high level description languages and formats. The ATF1508AS is designed with a power-up reset, a feature critical for state machine initialization. At a point delayed slightly from VCC crossing VRST, all registers will be initialized, and the state of each output will depend on the polarity of its buffer. However, due to the asynchronous nature of reset and uncertainty of how VCC actually rises in the system, the following conditions are required: 1. The VCC rise must be monotonic, 2. After reset occurs, all input and feedback setup times must be met before driving the clock pin high, and, 3. The clock must remain stable during TD. The ATF1508AS has two options for the hysteresis about the reset level, VRST, Small and Large. During the fitting process users may configure the device with the Power-up Reset hysteresis set to Large or Small. Atmel POF2JED users may select the Large option by including the flag “-power_reset” on the command line after “filename.POF”. To allow the registers to be properly reinitialized with the Large hysteresis option selected, the following condition is added: 4. If VCC falls below 2.0V, it must shut off completely before the device is turned on again. When the Large hysteresis option is active, ICC is reduced by several hundred microamps as well. Security Fuse Usage Programming A single fuse is provided to prevent unauthorized copying of the ATF1508AS fuse patterns. Once programmed, fuse verify is inhibited. However, User Signature and device ID remains accessible. ATF1508AS devices are in-system programmable (ISP) devices utilizing the 4-pin JTAG protocol. This capability eliminates package handling normally required for programming and facilitates rapid design iterations and field changes. Atmel provides ISP hardware and software to allow programming of the ATF1508AS via the PC. ISP is performed by using either a download cable or a comparable board tester or a simple microprocessor interface. To allow ISP programming support by the Automated Test Equipment (ATE) vendors, Serial Vector Format (SVF) files can be created by the Atmel ISP Software. Conversion to other ATE tester format beside SVF is also possible ATF1508AS devices can also be programmed using standard third-party programmers. With third-party programmer, the JTAG ISP port can be disabled thereby allowing four additional I/O pins to be used for logic. Contact your local Atmel representatives or Atmel PLD applications for details. 8 ATF1508AS(L) 0784P–PLD–7/05 ATF1508AS(L) ISP Programming Protection The ATF1508AS has a special feature that locks the device and prevents the inputs and I/O from driving if the programming process is interrupted for any reason. The inputs and I/O default to high-Z state during such a condition. In addition the pin-keeper option preserves the former state during device programming. All ATF1508AS devices are initially shipped in the erased state thereby making them ready to use for ISP. Note: For more information refer to the “Designing for In-System Programmability with Atmel CPLDs” application note. JTAG-BST Overview The JTAG boundary-scan testing is controlled by the Test Access Port (TAP) controller in the ATF1508AS. The boundary-scan technique involves the inclusion of a shift-register stage (contained in a boundary-scan cell) adjacent to each component so that signals at component boundaries can be controlled and observed using scan testing principles. Each input pin and I/O pin has its own boundary-scan cell (BSC) in order to support boundary-scan testing. The ATF1508AS does not currently include a Test Reset (TRST) input pin because the TAP controller is automatically reset at power-up. The six JTAG BST modes supported include: SAMPLE/PRELOAD, EXTEST, BYPASS and IDCODE. BST on the ATF1508AS is implemented using the Boundary-scan Definition Language (BSDL) described in the JTAG specification (IEEE Standard 1149.1). Any third-party tool that supports the BSDL format can be used to perform BST on the ATF1508AS. The ATF1508AS also has the option of using four JTAG-standard I/O pins for In-System programming (ISP). The ATF1508AS is programmable through the four JTAG pins using programming compatible with the IEEE JTAG Standard 1149.1. Programming is performed by using 5V TTL-level programming signals from the JTAG ISP interface. The JTAG feature is a programmable option. If JTAG (BST or ISP) is not needed, then the four JTAG control pins are available as I/O pins. JTAG Boundary-scan Cell (BSC) Testing The ATF1508AS contains up to 96 I/O pins and four input pins, depending on the device type and package type selected. Each input pin and I/O pin has its own boundary-scan cell (BSC) in order to support boundary-scan testing as described in detail by IEEE Standard 1149.1. A typical BSC consists of three capture registers or scan registers and up to two update registers. There are two types of BSCs, one for input or I/O pin, and one for the macrocells. The BSCs in the device are chained together through the (BST) capture registers. Input to the capture register chain is fed in from the TDI pin while the output is directed to the TDO pin. Capture registers are used to capture active device data signals, to shift data in and out of the device and to load data into the update registers. Control signals are generated internally by the JTAG TAP controller. The BSC configuration for the input and I/O pins and macrocells are shown below. 9 0784P–PLD–7/05 BSC Configuration Pins and Macrocells (Except JTAG TAP Pins) Note: The ATF1508AS has a pull-up option on TMS and TDI pins. This feature is selected as a design option. BSC Configuration for Macrocell TDO OEJ 0 0 1 1 DQ DQ OUTJ 0 0 1 1 DQ DQ Pin Capture DR TDI Shift Update DR Mode Clock Macrocell BSC Boundary Scan Definition Language (BSDL) Models for the ATF1508 These are now available in all package types via the Atmel Web Site. These models can be used for Boundary-scan Test Operation in the ATF1508AS and have been scheduled to conform to the IEEE 1149.1 standard. 10 ATF1508AS(L) 0784P–PLD–7/05 ATF1508AS(L) PCI Compliance The ATF1508AS also supports the growing need in the industry to support the new Peripheral Component Interconnect (PCI) interface standard in PCI-based designs and specifications. The PCI interface calls for high current drivers, which are much larger than the traditional TTL drivers. PCI Voltage-tocurrent Curves for +5V Signaling in Pull-up Mode Pull Up VCC Voltage Test Point 2.4 1.4 DC drive point AC drive point -2 -44 Current (mA) -178 PCI Voltage-tocurrent Curves for +5V Signaling in Pull-down Mode Pull Down VCC Voltage AC drive point 2.2 DC drive point 0.55 Test Point Current (mA) 3,6 95 380 11 0784P–PLD–7/05 PCI DC Characteristics Symbol VCC VIH VIL IIH IIL VOH VOL CIN CCLK CIDSEL LPIN Note: Supply Voltage Input High Voltage Input Low Voltage Input High Leakage Current Input Low Leakage Current Output High Voltage Output Low Voltage Input Pin Capacitance CLK Pin Capacitance IDSEL Pin Capacitance Pin Inductance 1. Leakage current is without pin-keeper off. (1) Parameter Conditions Min 4.75 2.0 -0.5 Max 5.25 VCC + 0.5 0.8 70 -70 Units V V V µA µA V VIN = 2.7V VIN = 0.5V IOUT = -2 mA IOUT = 3 mA, 6 mA 2.4 (1) 0.55 10 12 8 20 V pF pF pF nH PCI AC Characteristics Symbol IOH(AC) Parameter Switching Current High Conditions 0 < VOUT ≤ 1.4 1.4 < VOUT < 2.4 3.1 < VOUT < VCC (Test High) IOL(AC) Switching Current Low VOUT = 3.1V VOUT > 2.2V 2.2 > VOUT > 0 0.1 > VOUT > 0 (Test Point) ICL SLEWR SLEWF Notes: Low Clamp Current Output Rise Slew Rate Output Fall Slew Rate VOUT = 0.71 -5 < VIN ≤ -1 0.4V to 2.4V load 2.4V to 0.4V load -25+(VIN + 1)/0.015 0.5 0.5 3.0 3.0 95 VOUT/0.023 Equation B 206 (2) Min -44 -44+(VOUT - 1.4)/0.024 Max Units mA mA Equation A(1) -142 mA µA mA mA mA mA mA V/ns V/ns 1. Equation A: IOH = 11.9 (VOUT - 5.25) * (VOUT + 2.45) for VCC > VOUT > 3.1V. 2. Equation B: IOL = 78.5 * VOUT * (4.4 - VOUT) for 0V < VOUT < 0.71V. 12 ATF1508AS(L) 0784P–PLD–7/05 ATF1508AS(L) Power-down Mode The ATF1508AS includes two pins for optional pin-controlled power-down feature. When this mode is enabled, the PD pin acts as the power-down pin. When the PD1 and PD2 pin is high, the device supply current is reduced to less than 10 mA. During power-down, all output data and internal logic states are latched and held. Therefore, all registered and combinatorial output data remain valid. Any outputs that were in a high-Z state at the onset will remain at highZ. During power-down, all input signals except the power-down pin are blocked. Input and I/O hold latches remain active to ensure that pins do not float to indeterminate levels, further reducing system power. The power-down pin feature is enabled in the logic design file. Designs using either power-down pin may not use the PD pin logic array input. However, buried logic resources in this macrocell may still be used. Power-down AC Characteristics(1)(2) -7 Symbol tIVDH tGVDH tCVDH tDHIX tDHGX tDHCX tDLIV tDLGV tDLCV tDLOV Notes: Parameter Valid I, I/O before PD High Valid OE (2) -10 Max Min 10 10 10 12 12 12 1 1 1 1 15 15 15 1 1 1 1 Max Min 15 15 15 -15 Max Min 20 20 20 25 25 25 1 1 1 1 -20 Max Min 25 25 25 30 30 30 1 1 1 1 -25 Max Units ns ns ns 35 35 35 1 1 1 1 ns ns ns µs µs µs µs Min 7 7 7 before PD High Valid Clock(2) before PD High I, I/O Don’t Care after PD High OE (2) Don’t Care after PD High (2) Clock Don’t Care after PD High PD Low to Valid I, I/O PD Low to Valid OE (Pin or Term) PD Low to Valid Clock (Pin or Term) PD Low to Valid Output 1. For slow slew outputs, add tSSO. 2. Pin or product term. Absolute Maximum Ratings* Temperature Under Bias.................................. -40°C to +85°C Storage Temperature ..................................... -65°C to +150°C Voltage on Any Pin with Respect to Ground .........................................-2.0V to +7.0V(1) Voltage on Input Pins with Respect to Ground During Programming.....................................-2.0V to +14.0V(1) Programming Voltage with Respect to Ground .......................................-2.0V to +14.0V(1) *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: 1. Minimum voltage is -0.6V DC, which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is VCC + 0.75V DC, which may overshoot to 7.0V for pulses of less than 20 ns. 13 0784P–PLD–7/05 DC and AC Operating Conditions Commercial Operating Temperature (Ambient) VCCINT or VCCIO (5V) Power Supply VCCIO (3.3V) Power Supply 0°C - 70°C 5V ± 5% 2.7V - 3.6V Industrial -40°C - 85°C 5V ± 10% 2.7V - 3.6V DC Characteristics(1) Symbol IIL IIH IOZ ICC1 Parameter Input or I/O Low Leakage Current Input or I/O High Leakage Current Tri-state Output Off-state Current Power Supply Current, Standby VO = VCC or GND VCC = Max VIN = 0, VCC Std Mode “L” Mode ICC2 ICC3(2) VCCIO VCCIO VIL VIH VOL Power Supply Current, Power-down Mode Reduced-power Mode Supply Current Supply Voltage Supply Voltage Input Low Voltage Input High Voltage Output Low Voltage (TTL) Output Low Voltage (CMOS) VOH Notes: Output High Voltage (TTL) VIN = VIH or VIL VCCIO = MIN, IOL = 12 mA VIN = VIH or VIL VCC = MIN, IOL = 0.1 mA VIN = VIH or VIL VCCIO = MIN, IOH = -4.0 mA Com. Ind. Com. Ind. 2.4 VCC = Max VIN = 0, VCC VCC = Max VIN = 0, VCC “PD” Mode Std Mode Com. Ind. Com. Ind. 3.3V Device Output 4.75 4.5 3.0 -0.3 2.0 Com. Ind. Com. Ind. -40 160 180 10 10 1 65 85 5.25 5.5 3.6 0.8 VCCIO + 0.3 0.45 0.45 0.2 0.2 10 VIN = VCC Condition Min Typ -2 2 Max -10 10 40 Units µA µA µA mA mA µA µA mA mA mA V V V V V V V V V V 5.0V Device Output 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec. 2. ICC3 refers to the current in the reduced-power mode when macrocell reduced-power is turned ON. 14 ATF1508AS(L) 0784P–PLD–7/05 ATF1508AS(L) Pin Capacitance(1) Typ CIN CI/O Note: 8 8 Max 10 10 Units pF pF Conditions VIN = 0V; f = 1.0 MHz VOUT = 0V; f = 1.0 MHz 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. The OGI pin (high-voltage pin during programming) has a maximum capacitance of 12 pF. Timing Model U Input Test Waveforms and Measurement Levels rR, tF = 1.5 ns typical Output AC Test Loads (3.0V)* (703 )* (8060 )* Note: *Numbers in parenthesis refer to 3.0V operating conditions (preliminary). 15 0784P–PLD–7/05 SUPPLY CURRENT VS. SUPPLY VOLTAGE (TA = 25°C, F = 0) 250.0 SUPPLY CURRENT VS. FREQUENCY LOW-POWER ("L") VERSION (TA = 25°C) 200.0 STANDARD POWER 200.0 ICC (mA) 150.0 STANDARD POWER ICC (mA) 150.0 REDUCED POWER MODE 100.0 100.0 REDUCED POWER MODE 50.0 50.0 4.50 4.75 5.00 VCC (V) 5.25 5.50 0.0 0.00 5.00 10.00 FREQUENCY (MHz) 15.00 20.00 SUPPLY CURRENT VS. SUPPLY VOLTAGE LOW-POWER ("L") VERSION (TA = 25°C, F = 0) 30.0 OUTPUT SOURCE CURRENT VS. SUPPLY VOLTAGE (VOH = 2.4V, TA = 25°C) 0 -10 -20 20.0 ICC ( A) IOH (mA) -30 -40 10.0 -50 -60 4.50 0.0 4.50 4.75 5.00 VCC (V) 5.25 5.50 4.75 5.00 SUPPLY VOLTAGE (V) 5.25 5.50 SUPPLY CURRENT VS. FREQUENCY STANDARD POWER (TA = 25°C, F = 0) 300.0 INPUT CURRENT (mA) INPUT CLAMP CURRENT VS. INPUT VOLTAGE (VCC = 5V, TA = 25°C) 0 -20 -40 -60 -80 -100 -120 -140 -160 250.0 200.0 ICC ( A) STANDARD POWER 150.0 100.0 50.0 0.0 0.00 REDUCED POWER MODE 20.00 40.00 60.00 FREQUENCY (MHz) 80.00 100.00 -1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 INPUT VOLTAGE (V) SUPPLY CURRENT VS. SUPPLY VOLTAGE PIN-CONTROLLED POWER-DOWN MODE (TA = 25°C, F = 0) 1100.0 OUTPUT SINK CURRENT VS. SUPPLY VOLTAGE (VOL = 0.5V, TA = 25°C) 43 42 41 STANDARD POWER ICC ( A) IOL (mA) 1000.0 40 39 38 900.0 800.0 REDUCED POWER MODE 700.0 4.50 37 36 4.50 4.75 5.00 VCC (V) 5.25 5.50 4.75 5.00 SUPPLY VOLTAGE (V) 5.25 5.50 16 ATF1508AS(L) 0784P–PLD–7/05 ATF1508AS(L) OUTPUT SOURCE CURRENT VS. SUPPLY VOLTAGE (VCC = 5V, TA = 25°C) 1.20 NORMALIZED TCO VS. SUPPLY VOLTAGE (TA = 25°C) -10 1.10 -50 NORMALIZED TPD -30 IOH (mA) 1.00 -70 -90 0.90 -110 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 OUTPUT VOLTAGE (V) 0.80 4.50 4.75 5.00 SUPPLY VOLTAGE (V) 5.25 5.50 INPUT CURRENT VS. INPUT VOLTAGE (VCC = 5V, TA = 25°C) 40 30 INPUT CURRENT ( A) NORMALIZED TSU 1.20 NORMALIZED TSU VS. SUPPLY VOLTAGE (TA = 25°C) 20 10 0 -10 -20 -30 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 INPUT VOLTAGE (V) 1.10 1.00 0.90 0.80 4.50 4.75 5.00 SUPPLY VOLTAGE (V) 5.25 5.50 OUTPUT SINK CURRENT VS. OUTPUT VOLTAGE (VCC = 5V, TA = 25°C) 140 120 NORMALIZED TPD 1.20 NORMALIZED TPD VS. TEMPERATURE (VCC = 5.0V) 100 IOL (mA) 80 60 40 20 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 OUTPUT VOLTAGE (V) 1.10 1.00 0.90 0.80 -40 0 TEMPERATURE (C) 25 75 NORMALIZED TPD VS. SUPPLY VOLTAGE (TA = 25°C) 1.20 NORMALIZED TCO VS. TEMPERATURE (VCC = 5.0V) 1.20 NORMALIZED TPD NORMALIZED TCO 1.10 1.10 1.00 1.00 0.90 0.90 0.80 4.50 0.80 4.75 5.00 SUPPLY VOLTAGE (V) 5.25 5.50 -40 0 TEMPERATURE (C) 25 75 17 0784P–PLD–7/05 NORMALIZED TSU VS. TEMPERATURE (VCC = 5.0V) 1.20 NORMALIZED TSU 1.10 1.00 0.90 0.80 -40 0 TEMPERATURE (C) 25 75 18 ATF1508AS(L) 0784P–PLD–7/05 ATF1508AS(L) AC Characteristics (1) -7 Symbol tPD1 tPD2 tSU tH tFSU tFH tCOP tCH tCL tASU tAH tACOP tACH tACL tCNT fCNT tACNT fACNT fMAX tIN tIO tFIN tSEXP tPEXP tLAD tLAC tIOE tOD1 Parameter Input or Feedback to Non-registered Output I/O Input or Feedback to Non-registered Feedback Global Clock Setup Time Global Clock Hold Time Global Clock Setup Time of Fast Input Global Clock Hold Time of Fast Input Global Clock to Output Delay Global Clock High Time Global Clock Low Time Array Clock Setup Time Array Clock Hold Time Array Clock Output Delay Array Clock High Time Array Clock Low Time Minimum Clock Global Period Maximum Internal Global Clock Frequency Minimum Array Clock Period Maximum Internal Array Clock Frequency Maximum Clock Frequency Input Pad and Buffer Delay I/O Input Pad and Buffer Delay Fast Input Delay Foldback Term Delay Cascade Logic Delay Logic Array Delay Logic Control Delay Internal Output Enable Delay Output Buffer and Pad Delay (Slow slew rate = OFF; VCCIO = 5V; CL = 35 pF) 125 166.7 0.5 0.5 1 4 0.8 3 3 2 2 125 8 100 125 0.5 0.5 1 5 0.8 5 5 2 1.5 3 3 8 100 10 76.9 100 2 2 2 8 1 6 6 3 4 3 3 3 2 7.5 4 4 10 76.9 13 66 41.7 2 2 2 10 1 7 7 3 5 6 0 3 0.5 4.5 4 4 3 3 10 6 6 13 66 17 50 33.3 2 2 2 12 1.2 8 8 4 6 Min Max 7.5 7 7 0 3 0.5 5 5 5 4 4 15 8 8 17 50 22 Min -10 Max 10 9 Min 3 3 11 0 3 1.0 8 6 6 4 5 20 10 10 22 -15 Max 15 12 16 0 3 1.5 10 7 7 5 6 25 Min -20 Max 20 16 20 0 3 2 13 Min -25 Max 25 20 Units ns ns ns ns ns MHz ns ns ns ns ns ns ns ns ns MHz ns MHz MHz ns ns ns ns ns ns ns ns ns 19 0784P–PLD–7/05 AC Characteristics (Continued)(1) -7 Symbol tOD2 Parameter Output Buffer and Pad Delay (Slow slew rate = OFF; VCCIO = 3.3V; CL = 35 pF) Output Buffer and Pad Delay (Slow slew rate = ON; VCCIO = 5V or 3.3V; CL = 35 pF) Output Buffer Enable Delay (Slow slew rate = OFF; VCCIO = 5.0V; CL = 35 pF) Output Buffer Enable Delay (Slow slew rate = OFF; VCCIO = 3.3V; CL = 35 pF) Output Buffer Enable Delay (Slow slew rate = ON; VCCIO = 5.0V/3.3V; CL = 35 pF) Output Buffer Disable Delay (CL = 5 pF) Register Setup Time Register Hold Time Register Setup Time of Fast Input Register Hold Time of Fast Input Register Delay Combinatorial Delay Array Clock Delay Register Enable Time Global Control Delay Register Preset Time Register Clear Time Switch Matrix Delay Reduced-power Adder (2) -10 Max 2.5 Min Max 2.0 Min -15 Max 5 Min -20 Max 6 Min -25 Max 7 Units ns Min tOD3 5 5.5 8 10 12 ns tZX1 4.0 5.0 7 9 10 ns tZX2 4.5 5.5 7 9 10 ns tZX3 9 9 10 11 12 ns tXZ tSU tH tFSU tFH tRD tCOMB tIC tEN tGLOB tPRE tCLR tUIM tRPA Notes: 4 3 2 3 0.5 1 1 3 3 1 2 2 1 10 2 3 3 0.5 5 4 4 2 2 2 2 5 5 1 3 3 1 11 6 5 5 2 2 1 1 6 6 1 4 4 2 13 7 6 6 3 2.5 2 2 7 7 1 5 5 2 14 8 ns ns ns ns ns 2 2 8 8 1 6 6 2 15 ns ns ns ns ns ns ns ns ns 1. See ordering information for valid part numbers. 2. The tRPA parameter must be added to the tLAD, tLAC,tTIC, tACL, and tSEXP parameters for macrocells running in the reducedpower mode. 20 ATF1508AS(L) 0784P–PLD–7/05 ATF1508AS(L) ATF1508AS Dedicated Pinouts Dedicated Pin INPUT/OE2/GCLK2 INPUT/GCLR INPUT/OE1 INPUT/GCLK1 I/O /GCLK3 I/O / PD (1, 2) I/O / TDI(JTAG) I/O / TMS(JTAG) I/O / TCK(JTAG) I/O / TDO(JTAG) GND VCCINT VCCIO N/C 84-lead J-lead 2 1 84 83 81 12,45 14 23 62 71 7,19,32,42, 47,59,72,82 3,43 13,26,38, 53,66,78 – 100-lead PQFP 92 91 90 89 87 3,43 6 17 64 75 13,28,40,45, 61,76,88,97 41,93 5,20,36,53,68,84 – 100-lead TQFP 90 89 88 87 85 1,41 4 15 62 73 11,26,38,43, 59,74,86,95 39,91 3,18,34,51,66,82 – 160-lead PQFP 142 141 140 139 137 63,159 9 22 99 112 17,42,60,66,95, 113,138,148 61,143 8,26,55,79,104,133 1,2,3,4,5,6,7,34,35,36, 37,38,39,40,44,45,46, 47,74,75,76,77,81,82, 83,84,85,86,87,114, 115,116,117,118,119, 120,124,125,126,127, 154,155,156,157 100 96 # of SIGNAL PINS # USER I/O PINS 68 64 84 80 84 80 OE (1, 2) GCLR GCLK (1, 2, 3) PD (1, 2) TDI, TMS, TCK, TDO GND VCCINT VCCIO Global OE Pins Global Clear Pin Global Clock Pins Power-down pins JTAG pins used for boundary scan testing or in-system programming Ground Pins VCC pins for the device (+5V - Internal) VCC pins for output drivers (for I/O pins) (+5V or 3.3V - I/Os) 21 0784P–PLD–7/05 ATF1508AS I/O Pinouts MC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 65 PLB A A A/ PD1 A A A A A A A A A A A A A B B B B B B B B B B B B B B B B/ TDI E 84-lead J-lead – – 12 – 11 10 – 9 – – 8 – 6 5 – 4 22 – 21 – 20 – – 18 17 – 16 – 15 – – 14 44 100-lead PQFP 4 – 3 – 2 1 – 100 99 – 98 – 96 95 – 94 16 – 15 – 14 12 – 11 10 – 9 – 8 7 – 6 42 100-lead TQFP 2 – 1 – 100 99 – 98 97 – 96 – 94 93 – 92 14 – 13 – 12 10 – 9 8 – 7 – 6 5 – 4 40 160-lead PQFP 160 – 159 158 153 152 – 151 150 – 149 147 146 145 – 144 21 – 20 19 18 16 – 15 14 – 13 12 11 10 – 9 62 MC 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 97 PLB C C C C C C C C C C C C C C C C/ TMS D D D D D D D D D D D D D D D D G 84-lead J-lead – – 31 – 30 29 – 28 – – 27 – 25 24 – 23 41 – 40 – 39 – – 37 36 – 35 – 34 – – 33 63 100-lead PQFP 27 – 26 – 25 24 – 23 22 – 21 – 19 18 – 17 39 – 38 – 37 35 – 34 33 – 32 – 31 30 – 29 65 100-lead TQFP 25 – 24 – 23 22 – 21 20 – 19 – 17 16 – 15 37 – 36 – 35 33 – 32 31 – 30 – 29 28 – 27 63 160-lead PQFP 41 – 33 32 31 30 – 29 28 – 27 25 24 23 – 22 59 – 58 57 56 54 – 53 52 – 51 50 49 48 – 43 100 22 ATF1508AS(L) 0784P–PLD–7/05 ATF1508AS(L) ATF1508AS I/O Pinouts (Continued) MC 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 PLB E E/ PD2 E E E E E E E E E E E E E F F F F F F F F F F F F F F F F/ TCK 84-lead J-lead – 45 – 46 – – 48 49 – 50 – 51 – – 52 – – 54 – 55 56 – 57 – – 58 – 60 61 – 62 100-lead PQFP – 43 – 44 46 – 47 48 – 49 – 50 51 – 52 54 – 55 – 56 57 – 58 59 – 60 – 62 63 – 64 100-lead TQFP – 41 – 42 44 – 45 46 – 47 – 48 49 – 50 52 – 53 – 54 55 – 56 57 – 58 – 60 61 – 62 160-lead PQFP – 63 64 65 67 – 68 69 – 70 71 72 73 – 78 80 – 88 89 90 91 – 92 93 – 94 96 97 98 – 99 MC 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 PLB G G G G G G G G G G G G G G G/ TDO H H H H H H H H H H H H H H H H/ GCLK3 84-lead J-lead – 64 – 65 – – 67 68 – 69 – 70 – – 71 – – 73 – 74 75 – 76 – – 77 – 79 80 – 81 100-lead PQFP – 66 – 67 69 – 70 71 – 72 – 73 74 – 75 77 – 78 – 79 80 – 81 82 – 83 – 85 86 – 87 100-lead TQFP – 64 – 65 67 – 68 69 – 70 – 71 72 – 73 75 – 76 – 77 78 – 79 80 – 81 – 83 84 – 85 160-lead PQFP – 101 102 103 105 – 106 107 – 108 109 110 111 – 112 121 – 122 123 128 129 – 130 131 – 132 134 135 136 – 137 23 0784P–PLD–7/05 Ordering Information ATF1508AS Standard Package Options tPD (ns) tCO1 (ns) fMAX (MHz) Ordering Code ATF1508AS-7 JC84 7.5 4.5 166.7 ATF1508AS-7 QC100 ATF1508AS-7 AC100 ATF1508AS-7 QC160 ATF1508AS-10 JC84 10 5 125 ATF1508AS-10 QC100 ATF1508AS-10 AC100 ATF1508AS-10 QC160 ATF1508AS-10 Jl84 ATF1508AS-10 Ql100 ATF1508AS-10 Al100 ATF1508AS-10 Ql160 ATF1508AS-15 JC84 15 5 100 ATF1508AS-15 QC100 ATF1508AS-15 AC100 ATF1508AS-15 QC160 ATF1508AS-15 JI84 ATF1508AS-15 QI100 15 8 100 ATF1508AS-15 AI100 ATF1508AS-15 QI160 Notes: 1. The last time buy is Sept. 30, 2005 for shaded parts. 2. The recommended replacement package for QC160 is the AU100. Package 84J 100Q1 100A 160Q1 84J 100Q1 100A 160Q1 84J 100Q1 100A 160Q1 84J 100Q1 100A 160Q1 84J 100Q1 100A 160Q1 Industrial (-40°C to +85°C) Commercial (0°C to 70°C) Industrial (-40°C to +85°C) Commercial (0°C to 70°C) Commercial (0°C to 70°C) Operation Range 10 5 125 Using “C” Product for Industrial To use commercial product for Industrial temperature ranges, down-grade one speed grade from the “I” to the “C” device (7 ns “C” = 10 ns “I”) and de-rate power by 30%. ATF1508AS Green Package Options (Pb/Halide-free/RoHS Compliant) tPD (ns) 7.5 tCO1 (ns) 4.5 fMAX (MHz) 166.7 Ordering Code ATF1508AS-7 JX84 ATF1508AS-7 AX100 ATF1508AS-10 JU84 ATF1508AS-10 QU100 ATF1508AS-10 AU100 Package Type 84J 100Q1 100A 160Q1 84-lead, Plastic J-leaded Chip Carrier (PLCC) 100-lead, Plastic Quad Pin Flat Package (PQFP) 100-lead, Very Thin Plastic Gull Wing Quad Flat Package (TQFP) 160-lead, Plastic Quad Pin Flat Package (PQFP) Package 84J 100A 84J 100Q1 100A Operation Range Commercial (0°C to 70°C) Industrial (-40°C to +85°C) 10 5 125 24 ATF1508AS(L) 0784P–PLD–7/05 ATF1508AS(L) ATF1508ASL Standard Package Options tPD (ns) tCO1 (ns) fMAX (MHz) Ordering Code ATF1508ASL-20 JC84 20 12 83.3 ATF1508ASL-20 QC100 ATF1508ASL-20 AC100 ATF1508ASL-20 QC160 ATF1508ASL-25 JI84 25 15 70 ATF1508ASL-25 QI100 ATF1508ASL-25 AI100 ATF1508ASL-25 QI160 Note: 1. The last time buy is Sept. 30, 2005 for shaded parts. Package 84J 100Q1 100A 160Q1 84J 100Q1 100A 160Q1 Industrial (-40°C to +85°C) Commercial (0°C to 70°C) Operation Range Using “C” Product for Industrial To use commercial product for Industrial temperature ranges, down-grade one speed grade from the “I” to the “C” device (7 ns “C” = 10 ns “I”) and de-rate power by 30%. ATF1508ASL Green Package Options (Pb/Halide-free/RoHS Compliant) tPD (ns) 25 tCO1 (ns) 15 fMAX (MHz) 70 Ordering Code ATF1508ASL-25 JU84 ATF1508ASL-25 AU100 Package 84J 100A Operation Range Industrial (-40°C to +85°C) Package Type 84J 100Q1 100A 160Q1 84-lead, Plastic J-leaded Chip Carrier (PLCC) 100-lead, Plastic Quad Pin Flat Package (PQFP) 100-lead, Very Thin Plastic Gull Wing Quad Flat Package (TQFP) 160-lead, Plastic Quad Pin Flat Package (PQFP) 25 0784P–PLD–7/05 Package Information 84J – PLCC 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER 1.14(0.045) X 45˚ 0.318(0.0125) 0.191(0.0075) E1 B E B1 D2/E2 e D1 D A A2 A1 0.51(0.020)MAX 45˚ MAX (3X) COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E Notes: 1. This package conforms to JEDEC reference MS-018, Variation AF. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. E1 D2/E2 B B1 e MIN 4.191 2.286 0.508 30.099 29.210 30.099 29.210 27.686 0.660 0.330 NOM – – – – – – – – – – 1.270 TYP MAX 4.572 3.048 – 30.353 29.413 30.353 29.413 28.702 0.813 0.533 Note 2 Note 2 NOTE 10/04/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 84J, 84-lead, Plastic J-leaded Chip Carrier (PLCC) DRAWING NO. 84J REV. B R 26 ATF1508AS(L) 0784P–PLD–7/05 ATF1508AS(L) 100Q1 – PQFP PIN 1 ID E PIN 1 e D1 B D E1 A C 0º~7º L A1 A A1 D E E1 B C D1 L e COMMON DIMENSIONS (Unit of Measure = mm) JEDEC STANDARD MS-022, GC-1 SYMBOL MIN – 0.25 NOM 3.04 0.33 23.20 BSC 17.20 BSC 14.00 BSC 0.22 0.11 – – 20 BSC 0.73 – 0.65 BSC 1.03 0.40 0.23 MAX 3.4 0.5 NOTE 07/6/2005 DRAWING NO. TITLE 2325 Orchard Parkway 100Q1, 100-lead, 14 x 20 mm Body, 3.2 mm Footprint, 0.65 mm Pitch, 100Q1 San Jose, CA 95131 Plastic Quad Flat Package (PQFP) REV. C R 27 0784P–PLD–7/05 100A – TQFP PIN 1 B PIN 1 IDENTIFIER e E1 E D1 D C 0˚~7˚ A1 L COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E MIN – 0.05 0.95 15.75 13.90 15.75 13.90 0.17 0.09 0.45 NOM – – 1.00 16.00 14.00 16.00 14.00 – – – 0.50 TYP MAX 1.20 0.15 1.05 16.25 14.10 16.25 14.10 0.27 0.20 0.75 Note 2 Note 2 NOTE A2 A Notes: 1. This package conforms to JEDEC reference MS-026, Variation AED. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.08 mm maximum. E1 B C L e 10/5/2001 2325 Orchard Parkway San Jose, CA 95131 TITLE 100A, 100-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness, 0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) DRAWING NO. 100A REV. C R 28 ATF1508AS(L) 0784P–PLD–7/05 ATF1508AS(L) 160Q1 – PQFP D1 D E1 E Top View A2 Bottom View A1 e b L1 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN 0.25 3.20 NOM – 3.40 31.20 BSC 28.00 BSC 31.20 BSC 28.00 BSC 0.65 BSC 0.22 – 1.60 REF 0.40 4 MAX 0.50 3.60 2 3 2 3 NOTE 5 Side View Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MS-022, Variation DD-1, for additional information. 2. To be determined at seating plane. 3. Regardless of the relative size of the upper and lower body sections, dimensions D1 and E1 are determined at the largest feature of the body exclusive of mold Flash and gate burrs, but including any mismatch between the upper and lower sections of the molded body. 4. Dimension b does not include Dambar protrusion. The Dambar protrusion(s) shall not cause the lead width to exceed b maximum by more than 0.08 mm. Dambar cannot be located on the lower radius or the lead foot. 5. A1 is defined as the distance from the seating plane to the lowest point of the package body. A1 A2 D D1 E E1 e b L1 3/28/02 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 160Q1, 160-lead, 28 x 28 mm Body, 3.2 Form Opt., Plastic Quad Flat Pack (PQFP) DRAWING NO. 160Q1 REV. A 29 0784P–PLD–7/05 Revision History Revision 0784P 0784O Comments Green package options added. The ATF1508ASL-25 commercial speed offering was obsoleted in 2002 and replaced by the ATF1508ASL-20 commercial speed grade. 30 ATF1508AS(L) 0784P–PLD–7/05 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. 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