ATF22LV10C-15SI

Features • • • • • • • • • 3.0V to 5.5V Operating Range Advanced Low-voltage Electrically-erasable Programmable Logic Device User-controlled Power-down Pin Option Pin-controlled Standby Power (10µA Typical) Well-suited for Battery Powered Systems 10ns Maximum Propagation Delay CMOS and TTL Compatible Inputs and Outputs Latch Feature Hold Inputs to Previous Logic States Advanced Electrically-erasable Technology – Reprogrammable – 100% Tested High-reliability CMOS Process – 20 year Data Retention – 100 Erase/Write Cycles – 2,000V ESD Protection – 200mA Latchup Immunity Industrial Temperature Ranges Dual-in-line and Surface Mount Packages in Standard Pinouts Inputs are 5V Tolerant Green Package Options (Pb/Halide-free/RoHS Compliant) Available Applcations include Glue logic for 3.3V systems, DMA Control, State Machine Control, Graphics processing • High-performance Electrically Erasable Programmable Logic Device Atmel ATF22LV10C See separate datasheet for Atmel ATF22LV10C(Q)Z option • • • • • 1. Description The Atmel® ATF22LV10C is a high-performance CMOS (electrically erasable) programmable logic device (PLD) that utilizes the Atmel proven electrically erasable Flash memory technology. Speeds down to 10ns and power dissipation as low as 10mA are offered. All speed ranges are specified over the 3.0V to 5.5V range for industrial and commercial temperature ranges. The ATF22LV10C provides a low-voltage and user controlled “zero” power CMOS PLD solution. A user-controlled power-down feature offers “zero” (10 µA typical) standby power. This feature allows the user to manage total system power to meet specific application requirements and enhance reliability, all without sacrificing speed. (The Atmel ATF22LV10CQZ provides edge-sensing “zero” standby power (3µA typical), as well as low voltage operation. See the ATF22LV10CQZ datasheet.) The ATF22LV10C is capable of operating at supply voltages down to 3.0V. When the power-down pin is active, the device is placed into a zero standby power-down mode. When the power-down pin is not used or active, the device operates in a full power low voltage mode. Pin “keeper” circuits on input and output pins hold pins to their previous logic levels when idle, which eliminate static power consumed by pull-up resistors. The ATF22LV10C macrocell incorporates a variable product term architecture. Each output is allocated from 8 to 16 product terms which allows highly-complex logic functions to be realized. Two additional product terms are included to provide synchronous reset and asynchronous reset. These additional product terms are common to all ten registers and are automatically cleared upon power-up. Register preload simplifies testing. A security fuse prevents unauthorized copying of programmed fuse patterns. 0780M–PLD–7/10 Figure 1-1. Block Diagram Figure 1-2. Pin Configurations Pin Configurations (All Pinouts Top View) Pin Name CLK IN I/O VCC PD Function Clock Logic Inputs Bi-directional Buffers (3V to 5.5V) Supply Programmable Power-down Figure 1-3. CLK/IN IN IN IN/PD IN IN IN IN IN IN IN GND TSSOP 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O IN Figure 1-4. DIP/SOIC CLK/IN IN IN IN/PD IN IN IN IN IN IN IN GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O IN Figure 1-5. PLCC IN IN CLK/IN VCC* VCC I/O I/O 4 3 2 1 28 27 26 Note: For PLCC, pins 1, 8, 15, and 22 can be left unconnected. For superior performance, connect VCC to pin 1 and GND to 8, 15, and 22 2 Atmel ATF22LV10C 0780M–PLD–7/10 IN IN GND GND* IN I/O I/O 12 13 14 15 16 17 18 IN/PD IN IN GND* IN IN IN 5 6 7 8 9 10 11 25 24 23 22 21 20 19 I/O I/O I/O GND* I/O I/O I/O Atmel ATF22LV10C 2. Absolute Maximum Ratings* *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Temperature Under Bias .................. -40°C to +85°C Storage Temperature...................... -65°C to +150°C Voltage on Any Pin with Respect to Ground...........................-2.0V to +7.0V(1) Voltage on Input Pins with Respect to Ground During Programming......................-2.0V to +14.0V(1) Programming Voltage with Respect to Ground.........................-2.0V to +14.0V(1) Note: 1. Minimum voltage is -0.6V DC, which may undershoot to 2.0V for pulses of less than 20ns. Maximum output pin voltage is VCC + 0.75V DC, which may overshoot to 7.0V for pulses of less than 20ns. 3. DC and AC Operating Conditions Commercial Industrial -40°C - 85°C 3.0V - 5.5V 0°C - 70°C 3.0V - 5.5V Operating Temperature (Ambient) VCC Power Supply 3.1 IIL IIH ICC ICC2 IPD IOS(1) VIL VIH VOL DC Characteristics Parameter Input or I/O Low Leakage Current Input or I/O High Leakage Current Power Supply Current Clocked Power Supply Current Power Supply Current, Power-down Mode Output Short Circuit Current Input Low Voltage Input High Voltage Output Low Voltage VIN = VIH or VIL VCC = Min IOL = 16mA VIN = VIH or VIL VCC = Min IOH = -2.0mA IOH = -100µA 2.4 VCC - 0.2V Condition(2) 0 VIN VIL(Max) (VCC - 0.2)V VIN VCC VCC = Max, VIN = Max Outputs Open VCC = Max Outputs Open, f = 15MHz VCC = 3.6V, Max VIN = 0, Outputs Open VOUT = 0.5V -0.5 2.0 Com. Ind. Com. Ind. Com. Ind. 10 10 55 60 Min Typ Max -10 10 85 90 100 105 100 120 -130 0.8 VCC + 0.75 0.5 Units µA µA mA mA mA mA µA µA mA V V V Symbol VOH VOH Notes: Output High Voltage Output High Voltage V V 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec 2. For DC characteristics, the test condition of VCC = Max corresponds to 3.6V 3 0780M–PLD–7/10 3.2 AC Waveforms 3.3 AC Characteristics(1) -10 -15 Max 10 5 2 7.5 0 12 6 71.4 80 83.3 3 2 3 10 8 6 10 12 12 13 3 2 3 10 8 6 10 6.5 2 12 0 16 8 45.5 50 62.5 15 15 15 Min 3 Max 15 8 10 Units ns ns ns ns ns ns ns MHz MHz MHz ns ns ns ns ns ns ns Parameter Input or Feedback to Non-Registered Output Clock to Feedback Clock to Output Input or Feedback Setup Time Input Hold Time Clock Period Clock Width External Feedback 1/(tS+ tCO) Min 3 Symbol tPD tCF tCO tS tH tP tW fMAX Internal Feedback 1/(tS + tCF) No Feedback 1/(tP) tEA tER tAP tSP tAW tAR tSPR Note: Input to Output Enable Input to Output Disable Input or I/O to Asynchronous Reset of Register Setup Time, Synchronous Preset Asychronous Reset Width Asychronous Reset Recovery Time Synchronous Preset to Clock Recovery Time 1. See ordering information for valid part numbers 4 Atmel ATF22LV10C 0780M–PLD–7/10 Atmel ATF22LV10C 3.4 Power-down AC Characteristics -10 Symbol tIVDH tGVDH tCVDH tDHIX tDHGX tDHCX tDLIV tDLGV tDLCV tDLOV Parameter Valid Input before PD High Valid OE before PD High Valid Clock before PD High Input Don't Care after PD High OE Don't Care after PD High Clock Don't Care after PD High PD Low to Valid Input PD Low to Valid OE PD Low to Valid Clock PD Low to Valid Output Min 10 0 0 10 10 10 10 25 25 30 Max Min 15 0 0 15 15 15 15 30 30 35 -15 Max Units ns ns ns ns ns ns ns ns ns ns 3.5 Input Test Waveforms and Measurement Levels tR, tF < 1.5ns 3.6 Output Test Loads 3.3V R1 = 316 OUTPUT PIN R2 = 348 CL = 35 pF Note: Similar competitors devices are specified with slightly different loads. These load differences may affect output signals’ delay and slew rate. Atmel® devices are tested with sufficient margins to meet compatible device specification conditions. Table 3-1. Pin Capacitance (f = 1MHz, T = 25°C(1) Typ Max 8 8 Units pF pF Conditions VIN = 0V VOUT = 0V CIN COUT Note: 5 6 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested 5 0780M–PLD–7/10 3.7 Power-up Reset The registers in the Atmel® ATF22LV10C are designed to reset during power-up. At a point delayed slightly from VCC crossing VRST, all registers will be reset to the low state. The output state will depend on the polarity of the buffer. This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the uncertainty of how VCC actually rises in the system, the following conditions are required: 1. The VCC rise must be monotonic and start below 0.7V 2. The clock must remain stable during TPR 3. After TPR, all input and feedback setup times must be met before driving the clock pin high 3.8 Preload of Register Outputs The ATF22LV10C registers are provided with circuitry to allow loading of each register with either a high or a low. This feature will simplify testing since any state can be forced into the registers to control test sequencing. A JEDEC file with preload is generated when a source file with vectors is compiled. Once downloaded, the JEDEC file preload sequence will be done automatically by most of the approved programmers after the programming. 4. Electronic Signature Word There are 64-bits of programmable memory that are always available to the user, even if the device is secured. These bits can be used for user-specific data. 5. Security Fuse Usage A single fuse is provided to prevent unauthorized copying of the ATF22LV10C fuse patterns. Once programmed, fuse verify and preload are inhibited. However, the 64-bit User Signature remains accessible. The security fuse should be programmed last, as its effect is immediate. 6. Programming/Erasing Programming/erasing is performed using standard PLD programmers. See CMOS PLD Programming Hardware & Software Support for information on software/programming. Table 6-1. Parameter TPR VRST Programming/Erasing Description Power-up Reset Time Power-up Reset Voltage Typ 600 2.5 Max 1,000 3.0 Units ns V 7. Input and I/O Pin-keeper All ATF22V10C family members have internal input and I/O pin-keeper circuits. Therefore, whenever inputs or I/Os are not being driven externally, they will maintain their last driven state. This ensures that all logic array inputs and device outputs are at known states. These are relatively weak active circuits that can be easily overridden by TTL-compatible drivers (see Input and I/O diagrams on page 7). 6 Atmel ATF22LV10C 0780M–PLD–7/10 Atmel ATF22LV10C 8. Power-down Mode The Atmel® ATF22LV10C includes an optional pin controlled power-down feature. When this mode is enabled, the PD pin acts as the power-down pin (Pin 4 on the DIP/SOIC packages and Pin 5 on the PLCC package). When the PD pin is high, the device supply current is reduced to less than 100mA. During power-down, all output data and internal logic states are latched and held. Therefore, all registered and combinatorial output data remain valid. Any outputs which were in an undetermined state at the onset of power-down will remain at the same state. During power-down, all input signals except the power-down pin are blocked. Input and I/O hold latches remain active to insure that pins do not float to indeterminate levels, further reducing system power. The power-down pin feature is enabled in the logic design file. Designs using the power-down pin may not use the PD pin logic array input. However, all other PD pin macrocell resources may still be used, including the buried feedback and foldback product term array inputs. PD pin configuration is controlled by the design file, and appears as a separate fuse bit in the JEDEC file. When the power-down feature is not specified in the design file, the IN/PD pin will be configured as a regular logic input. Note: Some programmers list the 22V10 JEDEC-compatible 22V10C (no PD used) separately from the non-22V10 JEDECcompatible 22V10CEX (with PD used). Figure 8-1. Input Diagram VCC 100K INPUT ESD PROTECTION CIRCUIT Figure 8-2. OE I/O Diagram VCC DATA I/O VCC INPUT 100K 7 0780M–PLD–7/10 9. Compiler Mode Selection Table 9-1. Compiler Mode Selection PAL Mode (5828 Fuses) Synario WINCUPL Note: Atmel ATF22C10C (DIP) Atmel ATF22V10C (PLCC) P22V10 P22V10LCC GAL Mode (5892 Fuses) Atmel ATF22C10C DIO (UES) Atmel ATF22V10C PLCC (UES) G22V10 G22V10LCC Power-down Mode(1) (5893 Fuses) Atmel ATF22C10C DIP (PWD) Atmel ATF22C10V PLCC (PWD) G22V10CP G22V10CPLCC 1. These device types will create a JEDEC file which when programmed in an Atmel ATF22V10C device will enable the power-down mode feature. All other devices have this feature disabled. 10. Functional Logic Diagram Description The functional logic diagram describes the Atmel® ATF22LV10C architecture. The ATF22LV10C has twelve inputs and ten I/O macrocells. Each macrocell can be configured into one of four output configurations: active high/low, registered/combinatorial output.The universal architecture of the ATF22LV10C can be programmed to emulate most 24-pin PAL devices. Unused product terms are automatically disabled by the compiler to decrease power consumption. A security fuse, when programmed, protects the contents of the ATF22LV10C. Eight bytes (64-fuses) of User Signature are accessible to the user for purposes such as storing project name, part number, revision or date. The User Signature is accessible regardless of the state of the security fuse. 8 Atmel ATF22LV10C 0780M–PLD–7/10 Atmel ATF22LV10C Figure 10-1. Functional Logic Diagram Atmel ATF22LV10C Note: 1. *Input not available if the power-down (PD) option is utilized 9 0780M–PLD–7/10 ATMEL ATF22LV10C SUPPLY CURRENT VS. SUPPLY VOLTAGE (TA = 25°C) 70.00 60.00 1.10 ATMEL ATF22LV10C NORMALIZED ICC VS. TEMP. ICC (mA) 50.00 40.00 30.00 20.00 10.00 0.00 NORMALIZED ICC 3.30 SUPPLY VOLTAGE (V) 3.60 1.00 0.90 0.80 3.00 -40.00 0.00 25.00 75.00 TEMPERATURE (DEG. C) ATMEL ATF22LV10C SUPPLY CURRENT VS. INPUT FREQUENCY (VCC = 3.3V, TA = 25°C) 75.00 ICC (mA) 50.00 25.00 0.00 0.00 10.00 20.00 50.00 FREQUENCY (MHz) ATMEL ATF22LV10C OUTPUT SOURCE CURRENT VS. SUPPLY VOLTAGE (VOH = 2.4V) 0.00 -2.00 0.00 -2.00 ATMEL ATF22LV10C OUTPUT SOURCE CURRENT VS. OUTPUT VOLTAGE (VCC = 3.3V, TA = 25°C) IOH (mA) -4.00 -6.00 -8.00 -10.00 IOH (mA) 3.15 3.30 SUPPLY VOLTAGE (V) 3.45 3.60 -4.00 -6.00 -8.00 -10.00 -12.00 3.00 2.00 2.20 2.40 2.60 2.70 VOH (V) 2.80 3.00 3.20 3.30 ATMEL ATF22LV10C OUTPUT SINK CURRENT VS. SUPPLY VOLTAGE (VOL = 0.5V) 40.00 39.00 38.00 90.00 80.00 70.00 60.00 ATMEL ATF22LV10C OUTPUT SINK CURRENT VS. OUTPUT VOLTAGE (VCC = 3.3V, TA = 25°C) IOL (mA) IOL (mA) 37.00 36.00 35.00 34.00 33.00 32.00 50.00 40.00 30.00 20.00 10.00 0.00 3.00 3.15 3.30 SUPPLY VOLTAGE (V) 3.45 3.60 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.30 OUTPUT VOLTAGE (V) 10 Atmel ATF22LV10C 0780M–PLD–7/10 Atmel ATF22LV10C ATMEL ATF22LV10C INPUT CLAMP CURRENT VS. INPUT VOLTAGE (VCC = 3.3V, TA = 25°C) 20.00 15.00 ATMEL ATF22LV10C INPUT CURRENT VS. INPUT VOLTAGE (VCC = 3.3V, TA = 25°C) INPUT CURRENT (mA) INPUT CURRENT (µA) -0.20 -0.40 -0.60 -0.80 -1.00 0.00 -20.00 -40.00 -60.00 -80.00 -100.00 10.00 5.00 0.00 -5.00 0.00 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 INPUT VOLTAGE (V) INPUT VOLTAGE (V) NORMALIZED TPD VS. VCC 1.15 1.20 NORMALIZED TPD VS. TEMP NORMALIZED TPD NORMALIZED TPD 1.10 1.05 1.00 0.95 0.90 0.85 0.80 1.15 1.10 1.05 1.00 0.95 0.90 0.85 0.80 3.00 3.15 3.30 SUPPLY VOLTAGE (V) 3.45 3.60 -0.40 0.00 25.00 75.00 TEMPERATURE (C) NORMALIZED TCO VS. VCC 1.15 1.10 1.20 1.15 NORMALIZED TCO VS. TEMP NORMALIZED TCO NORMALIZED TCO 1.05 1.00 0.95 0.90 0.85 0.80 1.10 1.05 1.00 0.95 0.90 0.85 0.80 3.00 3.15 3.30 SUPPLY VOLTAGE (V) 3.45 3.60 -0.40 0.00 25.00 75.00 TEMPERATURE (C) NORMALIZED TSU VS. VCC 1.10 1.10 NORMALIZED TSU VS. TEMP NORMALIZED TSU NORMALIZED TSU 1.05 1.00 0.95 0.90 0.85 0.80 1.05 1.00 0.95 0.90 0.85 0.80 3.00 3.15 3.30 SUPPLY VOLTAGE (V) 3.45 3.60 -0.40 0.00 25.00 75.00 TEMPERATURE (C) 11 0780M–PLD–7/10 ATMEL ATF22LV10C DELTA TPD VS. OUTPUT LOADING 14.00 12.00 14.00 12.00 10.00 8.00 6.00 4.00 2.00 0.00 -2.00 -4.00 ATMEL ATF22LV10C DELTA TCO VS. OUTPUT LOADING DELTA TPD (ns) 8.00 6.00 4.00 2.00 0.00 -2.00 -4.00 0.00 50.00 100.00 150.00 200.00 250.00 300.00 DELTA TCO (ns) 10.00 0.00 50.00 100.00 150.00 200.00 250.00 300.00 OUTPUT LOADING (PF) OUTPUT LOADING (PF) ATMEL ATF22LV10C DELTA TPD VS. NUMBER OF OUTPUT SWITCHING 0.00 -0.10 -0.20 -0.30 -0.40 -0.50 0.00 -0.10 -0.20 -0.30 -0.40 -0.50 ATMEL ATF22LV10C DELTA TCO VS. NUMBER OF OUTPUT SWITCHING DELTA TPD (ns) 1.00 2.00 3.00 4.00 5.00 6.00 7.00 8.00 9.00 10.00 DELTA TCO (ns) 1.00 2.00 3.00 4.00 5.00 6.00 7.00 8.00 9.00 10.00 NUMBER OF OUTPUTS SWITCHING NUMBER OF OUTPUTS SWITCHING 12 Atmel ATF22LV10C 0780M–PLD–7/10 Atmel ATF22LV10C 11. 11.1 Ordering Information Ordering Code Detail tPD (ns) tS (ns) tCO (ns) Ordering Code ATF22LV10C-10JC ATF22LV10C-10PC ATF22LV10C-10SC ATF22LV10C-10XC ATF22LV10C-10JI ATF22LV10C-10PI ATF22LV10C-10SI ATF22LV10C-10XI ATF22LV10C-15JC ATF22LV10C-15PC ATF22LV10C-15SC ATF22LV10C-15XC ATF22LV10C-15JI ATF22LV10C-15PI ATF22LV10C-15SI ATF22LV10C-15XI Package 28J 24P3 24S 24X 28J 24P3 24S 24X 28J 24P3 24S 24X 28J 24P3 24S 24X Operation Range Commercial (0C to 70C) 10 7.5 7.5 10 7.5 7.5 Industrial (0C to 85C) 12 15 12 10 Commercial (0C to 70C) 10 Industrial (-40C to +85C) Note: Lead based packages will become obsolete, and are not recommended for new designs 11.2 Green Package Options (Pb/Halide-free/RoHS Compliant) tPD (ns) tS (ns) tCO (ns) Ordering Code ATF22LV10C-10JU ATF22LV10C-10PU ATF22LV10C-10SU ATF22LV10C-10XU Package 28J 24P3 24S 24X Operation Range Industrial (0C to +85C) 10 7.5 7.5 11.3 Using “C” Product for Industrial To use commercial product for industrial temperature ranges, simply de-rate ICC by 15% on the “C” device. No speed de-rating is necessary. Package Type 28J 24P3 24S 24X 28-lead, Plastic J-leaded Chip Carrier (PLCC) 24-lead, 0.300" Wide, Plastic Dual In-line Package (PDIP) 24-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC) 24-lead, 4.4mm Wide, Plastic Thin Shrink Small Outline (TSSOP) 13 0780M–PLD–7/10 12. 12.1 Package Information 28J – PLCC 1.14(0.045) X 45° PIN NO. 1 IDENTIFIER 1.14(0.045) X 45° 0.318(0.0125) 0.191(0.0075) E1 B E B1 D2/E2 e D1 D A A2 A1 0.51(0.020)MAX 45° MAX (3X) COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E Notes: 1. This package conforms to JEDEC reference MS-018, Variation AB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102mm) maximum. E1 D2/E2 B B1 e MIN 4.191 2.286 0.508 12.319 11.430 12.319 11.430 9.906 0.660 0.330 NOM – – – – – – – – – – 1.270 TYP MAX 4.572 3.048 – 12.573 11.582 12.573 11.582 10.922 0.813 0.533 Note 2 Note 2 NOTE 10/04/01 Package Drawing Contact: packagedrawings@atmel.com TITLE 28J, 28-lead, Plastic J-leaded Chip Carrier (PLCC) DRAWING NO. 28J REV. B 14 Atmel ATF22LV10C 0780M–PLD–7/10 Atmel ATF22LV10C 12.2 24P3 – PDIP D PIN 1 E1 A SEATING PLANE L B1 e E B A1 C eC eB SYMBOL A A1 D E E1 B Notes: 1. 2. This package conforms to JEDEC reference MS-001, Variation AF. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25mm (0.010"). B1 L C eB eC e COMMON DIMENSIONS (Unit of Measure = mm) MIN – 0.381 31.623 7.620 6.096 0.356 1.270 2.921 0.203 – 0.000 NOM – – – – – – – – – – – MAX 5.334 – 32.131 8.255 7.112 0.559 1.651 3.810 0.356 10.922 1.524 Note 2 Note 2 NOTE 2.540 TYP 6/1/04 Package Drawing Contact: packagedrawings@atmel.com TITLE 24P3, 24-lead (0.300"/7.62mm Wide) Plastic Dual Inline Package (PDIP) DRAWING NO. 24P3 REV. D 15 0780M–PLD–7/10 12.3 24S – SOIC B D1 PIN 1 ID PIN 1 D e E A COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN – 0.10 10.00 7.40 15.20 0.33 0.40 0.23 NOM – – – – – – – – 1.27 BSC MAX 2.65 0.30 10.65 7.60 15.60 0.51 1.27 0.32 NOTE A1 A A1 D D1 0 8 L1 E B L L L1 e 06/17/2002 Package Drawing Contact: packagedrawings@atmel.com TITLE 24S, 24-lead (0.300" body) Plastic Gull Wing Small Outline (SOIC) DRAWING NO. 24S REV. B 16 Atmel ATF22LV10C 0780M–PLD–7/10 Atmel ATF22LV10C 12.4 24X – TSSOP Dimensions in Millimeter and (Inches)* JEDEC STANDARD MO-153 AD Controlling dimension: millimeters 0.30(0.012) 0.19(0.007) 4.48(0.176) 4.30(0.169) 6.50(0.256) 6.25(0.246) PIN 1 0.65(0.0256)BSC 7.90(0.311) 7.70(0.303) 1.20(0.047)MAX 0.15(0.006) 0.05(0.002) 0 8 0.20(0.008) 0.09(0.004) 0.75(0.030) 0.45(0.018) 04/11/2001 Package Drawing Contact: packagedrawings@atmel.com TITLE 24X, 24-lead (4.4mm body width) Plastic Thin Shrink Small Outline Package (TSSOP) DRAWING NO. 24X REV. A 17 0780M–PLD–7/10 13. Revision History Doc. Rev. 0780M 0780L Date 07/2010 12/2005 Comments Update the standby current parameters for Powerdown mode from 100µA to 120µA. Shade Ordering Package Option table and add note, “Lead based packages will become obsolete and are not recommended for new designs.” Add Green Package options 18 Atmel ATF22LV10C 0780M–PLD–7/10 Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: (+1)(408) 441-0311 Fax: (+1)(408) 487-2600 www.atmel.com International Atmel Asia Limited Unit 01-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon HONG KONG Tel: (+852) 2245-6100 Fax: (+852) 2722-1369 Atmel Munich GmbH Business Campus Parkring 4 D-85748 Garching b. Munich GERMANY Tel: (+49) 89-31970-0 Fax: (+49) 89-3194621 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 JAPAN Tel: (+81) 3-3523-3551 Fax: (+81) 3-3523-7581 Product Contact Technical Support pld@atmel.com Sales Contact www.atmel.com/contacts Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. 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