ATF22V10CZ

Features • • • • • • • • • Industry Standard Architecture 12 ns Maximum Pin-to-Pin Delay Zero Power - 25 µA Maximum Standby Power CMOS and TTL Compatible Inputs and Outputs Advanced Electrically Erasable Technology Reprogrammable 100% Tested Latch Feature Holds Inputs to Previous Logic State High Reliability CMOS Process 20 Year Data Retention 100 Erase/Write Cycles 2,000V ESD Protection 200 mA Latchup Immunity Commercial and Industrial Temperature Ranges Dual-in-Line and Surface Mount Packages in Standard Pinouts High Performance E2 PLD ATF22V10CZ Preliminary Block Diagram Description The ATF22V10CZ is a high performance CMOS (Electrically Erasable) Programmable Logic Device (PLD) which utilizes Atmel’s proven electrically erasable Flash memory technology. Speeds down to 12 ns with zero standby power dissipation are offered. All speed ranges are specified over the full 5V ±10% range for industrial temperature ranges; 5V ± 5% for commercial range 5-volt devices. ATF22V10CZ Pin Configurations Pin Name CLK IN I/O VCC Function Clock Logic Inputs Bidirectional Buffers +5V Supply CLK/IN IN IN IN IN IN IN IN IN IN IN GND TSSOP Top View DIP/SOIC PLCC Top View (1) 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O IN Note: 1. For PLCC, P1, P8, P15 and P22 can be left unconnected. Connect VCC to pin 1 and GND to 8, 15, and 22. Rev. 0778B/V10CZ-B–04/98 The ATF22V10CZ provides a “zero” power CMOS PLD solution with 5V operating voltages. The ATF22V10CZ powers down automatically to the zero power mode through Atmel’s patented Input Transition Detection (ITD) circuitry when the device is idle. The ATF22V10CZ has an edge-sensing power down feature, offering “zero” (25 µA worst case) standby power. This feature allows the user to manage total system power to meet specific application requirements and enhance reliability. Pin “keeper” circuits on input and output pins eliminate static power consumed by pull-up resistors. The ATF22V10CZ incorporates a superset of the generic architectures, which allows direct replacement of the 22V10 family and most 24-pin combinatorial PLDs. Ten outputs are each allocated 8 to 16 product terms. Three different modes of operation, configured automatically with software, allow highly complex logic functions to be realized. Absolute Maximum Ratings* Temperature Under Bias................... -40°C to +85°C Storage Temperature...................... -65°C to +150°C Voltage on Any Pin with Respect to Ground......................... -2.0V to +7.0V (1) Voltage on Input Pins with Respect to Ground During Programming.................... -2.0V to +14.0V (1) Programming Voltage with Respect to Ground....................... -2.0V to +14.0V (1) *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: 1. Minimum voltage is -0.6V dc, which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is Vcc + 0.75V dc, which may overshoot to 7.0V for pulses of less than 20 ns. DC and AC Operating Conditions Commercial Operating Temperature (Case) VCC Power Supply 0°C - 70°C 5V ± 5% Industrial -40°C - 85°C 5V ± 10% 2 ATF22V10CZ ATF22V10CZ Functional Logic Diagram Description The Functional Logic Diagram describes the ATF22V10CZ architecture. The ATF22V10CZ has 12 inputs and 10 I/O macrocells. Each macrocell can be configured into one of four output configurations: active high/low, registered/combinatorial output. The universal architecture of the ATF22V10CZ can be programmed to emulate most 24-pin PAL devices. Unused product terms are automatically disabled by the compiler to decrease power consumption. A Security Fuse, when programmed, protects the contents of the ATF22V10CZ. Eight bytes (64 fuses) of User Signature are accessible to the user for purposes such as storing project name, part number, revision or date. The User Signature is accessible regardless of the state of the Security Fuse. DC Characteristics Symbol Parameter IIL IIH ICC Input or I/O Low Leakage Current Input or I/O High Leakage Current Clocked Power Supply Current Condition 0 ≤ VIN ≤ VIL(max) 3.5 ≤ VIN ≤ VCC VCC = MAX, Outputs Open, f = 15 MHz Com. Ind. Com. Ind. 90 90 5 5 Min Typ Max -10 10 150 180 25 50 -150 -0.5 2.0 VIN = VIH or VIL VCC = MIN, IOL = 16 mA VIN = VIH or VIL, VCC = MIN, IOH = -4.0 mA Com. Ind. 2.4 0.8 VCC + 0.75 0.5 Units µA µA mA mA µA µA mA V V V V ISB IOS (1) VIL VIH VOL V = MAX, Power Supply Current, CC VIN = MAX, Standby Outputs Open Output Short Circuit Current Input Low Voltage Input High Voltage Output Low Voltage VOUT = 0.5V VOH Note: Output High Voltage 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec. 3 AC Waveforms AC Characteristics (1) -12 Symbol tPD tCF tCO tS tH tP tW FMAX tEA tER tPZX tPXZ tAP tSP tAW tAR tSPR Note: -15 Max Min Max Parameter Input to Feedback to Non-Registered Output Clock to Feedback Clock to Output Input or Feedback Setup Time Input Hold Time Clock Period Clock Width External Feedback 1/(tS + tCO) Internal Feedback 1/(tS + tCF) No Feedback 1/(tP) Input to Output Enable - Product Term Input to Output Disable - Product Term OE Pin to Output Enable OE Pin to Output Disable Input or I/O to Asynchronous Reset of Register Setup Time, Synchronous Preset Asynchronous Reset Width Asynchronous Reset Recovery Time Synchronous Preset to Clock Recovery Time Min Units ns ns ns ns ns ns ns MHz MHz MHz 3 2 10 0 12 6 12 6 8 3 2 10 0 12 6 15 4.5 8 55.5 62 83.3 3 2 2 2 3 10 7 5 10 12 15 12 15 10 55.5 69 83.3 3 3 2 2 3 10 8 6 10 15 15 15 15 15 ns ns ns ns ns ns ns ns ns 1. See ordering information for valid part numbers. 4 ATF22V10CZ ATF22V10CZ Input Test Waveforms and Measurement Levels Output Test Loads Note: Similar competitors’ devices are specified with slightly different loads. These load differences may affect output signals’ delay and slew rate. Atmel devices are tested with sufficient margins to meet compatible device specification conditions. Pin Capacitance (f = 1 MHz, T = 25°C) (1) Typ CIN COUT Note: Max 8 8 Units pF pF Conditions VIN = 0V VOUT = 0V 5 6 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. 5 Power Up Reset The registers in the ATF22V10CZ are designed to reset during power up. At a point delayed slightly from VCC crossing VRST, all registers will be reset to the low state. The output state will depend on the polarity of the buffer. This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the uncertainty of how VCC actually rises in the system, the following conditions are required: 1. The VCC rise must be monotonic and start below 0.7V. 2. The clock must remain stable during TPR. 3. After TPR occurs, all input and feedback setup times must be met before driving the clock pin high. file preload sequence will be done automatically by most of the approved programmers after the programming. Electronic Signature Word There are 64 bits of programmable memory that are always available to the user, even if the device is secured. These bits can be used for user-specific data. Security Fuse Usage A single fuse is provided to prevent unauthorized copying of the ATF22V10CZ fuse patterns. Once programmed, fuse verify and preload are inhibited. However, the 64-bit User Signature remains accessible. The security fuse should be programmed last, as its effect is immediate. Preload of Register Outputs The ATF22V10CZ’s registers are provided with circuitry to allow loading of each register with either a high or a low. This feature will simplify testing since any state can be forced into the registers to control test sequencing. A JEDEC file with preload is generated when a source file with vectors is compiled. Once downloaded, the JEDEC Programming/Erasing Programming/erasing is performed using standard PLD programmers. See CMOS PLD Programming Hardware & Software Support for information on software/programming. V R ST POWER t PR REGISTERED OUTPUTS tW CLOCK tS Parameter TPR VRST Description Power-Up Reset Time Power-Up Reset Voltage Typ 600 3.8 Max 1,000 4.5 Units ns V 6 ATF22V10CZ ATF22V10CZ Input and I/O Pull-Ups All ATF22V10CZ family members have internal input and I/O pin-keeper circuits. Therefore, whenever inputs or I/Os are not being driven externally, they will maintain their last driven state. This ensures that all logic array inputs and device outputs are at known states. These are relatively weak active circuits that can be easily overridden by TTL-compatible drivers (see input and I/O diagrams below). Input Diagram I/O Diagram 7 Functional Logic Diagram ATF22V10CZ 8 ATF22V10CZ ATF22V10CZ tPD (ns) 12 tS (ns) 10 tCO (ns) 8 Ordering Code ATF22V10CZ-12JC ATF22V10CZ-12PC ATF22V10CZ-12SC ATF22V10CZ-12XC ATF22V10CZ-15JC ATF22V10CZ-15PC ATF22V10CZ-15SC ATF22V10CZ-15XC ATF22V10CZ-15JI ATF22V10CZ-15PI ATF22V10CZ-15SI ATF22V10CZ-15XI Package 28J 24P3 24S 24X 28J 24P3 24S 24X 28J 24P3 24S 24X Operation Range Commercial (0°C to 70°C) 15 4.5 8 Commercial (0°C to 70°C) 4.5 8 Industrial (-40°C to +85°C) Package Type 28J 24P3 24S 24X 28-Lead, Plastic J-Leaded Chip Carrier (PLCC) 24-Lead, 0.300" Wide, Plastic Dual Inline Package (DIP) 24-Lead, 0.300" Wide, Plastic Gull WIng Small Outline (SOIC) 24-Lead, 4.4 mm Wide, Plastic Thin Shrink Small Outline (TSSOP) 9