ATF2500C-20PC

Features • • • • High-performance, High-density, Electrically-erasable Programmable Logic Device Fully Connected Logic Array with 416 Product Terms 15 ns Maximum Pin-to-pin Delay for 5V Operation 24 Flexible Output Macrocells – 48 Flip-flops – Two per Macrocell – 72 Sum Terms – All Flip-flops, I/O Pins Feed in Independently D- or T-type Flip-flops Product Term or Direct Input Pin Clocking Registered or Combinatorial Internal Feedback Backward Compatible with ATV2500B/BQ and ATV2500H Software Advanced Electrically-erasable Technology – Reprogrammable – 100% Tested 44-lead Surface Mount Package and 40-pin DIP Package Flexible Design: Up to 48 Buried Flip-flops and 24 Combinatorial Outputs Simultaneously 8 Synchronous Product Terms Individual Asynchronous Reset per Macrocell OE Control per Macrocell Functionality Equivalent to ATV2500B/BQ and ATV2500H 2000V ESD Protection Security Fuse Feature to Protect the Code Commercial, Industrial and Military Temperature Range Offered 10 Year Data Retention Pin Keeper Option 200 mA Latch-up Immunity Green Package Options (Pb/Halide-free/RoHS Compliant) Available • • • • • ATF2500C CPLD Family Datasheet ATF2500C • • • • • • • • • • • • • 1. Description The ATF2500C is the highest-density PLD available in a 44-pin surface mount package. With its fully connected logic array and flexible macrocell structure, high gate utilization is easily obtainable. The ATF2500C is a high-performance CMOS (electrically-erasable) programmable logic device (PLD) that utilizes Atmel’s proven electrically-erasable technology. This PLD is now available in a fully Green or LHF (lead and halide-free) packages. Figure 1-1. Block Diagram 0777K–PLD–1/24/08 The ATF2500C is organized around a single universal array. All pins and feedback terms are always available to every macrocell. Each of the 38 logic pins are array inputs, as are the outputs of each flip-flop. In the ATF2500C, four product terms are input to each sum term. Furthermore, each macrocell’s three sum terms can be combined to provide up to 12 product terms per sum term with no performance penalty. Each flip-flop is individually selectable to be either D- or T-type, providing further logic compaction. Also, 24 of the flip-flops may be bypassed to provide internal combinatorial feedback to the logic array. Product terms provide individual clocks and asynchronous resets for each flip-flop. The flip-flops may also be individually configured to have direct input pin clocking. Each output has its own enable product term. Eight synchronous preset product terms serve local groups of either four or eight flip-flops. Register preload functions are provided to simplify testing. All registers automatically reset upon power-up. 2. Pin Configurations Table 2-1. Pin Name IN CLK/IN I/O I/O 0,2,4... I/O 1,3,5... GND VCC Pin Configurations Function Logic Inputs Pin Clock and Input Bi-directional Buffers Even I/O Buffers Odd I/O Buffers Ground +5V Supply Figure 2-1. CLK/IN IN IN I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 VCC I/O17 I/O16 I/O15 I/O14 I/O13 I/O12 IN IN IN IN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 DIP 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 IN IN IN IN I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 GND I/O23 I/O22 I/O21 I/O20 I/O19 I/O18 IN IN IN Figure 2-2. PLCC I/O1 I/O0 GND IN IN CLK/IN IN IN IN IN I/O6 Note: (PLCC package) pin 4 and pin 26 GND connections are not required, but are recommended for improved noise immunity. 2 ATF2500C 0777K–PLD–1/24/08 I/O12 IN IN IN IN IN IN IN GND I/O18 I/O19 18 19 20 21 22 23 24 25 26 27 28 I/O2 I/O3 I/O4 I/O5 VCC VCC I/O17 I/O16 I/O15 I/O14 I/O13 7 8 9 10 11 12 13 14 15 16 17 6 5 4 3 2 1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 I/O7 I/O8 I/O9 I/O10 I/O11 GND GND I/O23 I/O22 I/O21 I/O20 ATF2500C 3. Using the ATF2500C Family’s Many Advanced Features The ATF2500Cs advanced flexibility packs more usable gates into 44 leads than other PLDs. Some of the ATF2500Cs key features are: • Fully Connected Logic Array – Each array input is always available to every product term. This makes logic placement a breeze. • Selectable D- and T-Type Registers – Each ATF2500C flip-flop can be individually configured as either D- or T-type. Using the T-type configuration, JK and SR flip-flops are also easily created. These options allow more efficient product term usage. • Buried Combinatorial Feedback – Each macrocell’s Q2 register may be bypassed to feed its input (D/T2) directly back to the logic array. This provides further logic expansion capability without using precious pin resources. • Selectable Synchronous/Asynchronous Clocking – Each of the ATF2500Cs flip-flops has a dedicated clock product term. This removes the constraint that all registers use the same clock. Buried state machines, counters and registers can all coexist in one device while running on separate clocks. Individual flip-flop clock source selection further allows mixing higher performance pin clocking and flexible product term clocking within one design. • A Total of 48 Registers – The ATF2500C provides two flip-flops per macrocell – a total of 48. Each register has its own clock and reset terms, as well as its own sum term. • Independent I/O Pin and Feedback Paths – Each I/O pin on the ATF2500C has a dedicated input path. Each of the 48 registers has its own feedback term into the array as well. These features, combined with individual product terms for each I/O’s output enable, facilitate true bi-directional I/O design. • Combinable Sum Terms – Each output macrocell’s three sum terms may be combined into a single term. This provides a fan in of up to 12 product terms per sum term with no speed penalty. • Programmable Pin-keeper Circuits – These weak feedback latches are useful for bus interfacing applications. Floating pins can be set to a known state if the Pin-keepers are enabled. • User Row (64 bits) – Use to store information such as unit history. 3 0777K–PLD–1/24/08 4. Power-up Reset The registers in the ATF2500Cs are designed to reset during power-up. At a point delayed slightly from VCC crossing VRST, all registers will be reset to the low state. The output state will depend on the polarity of the output buffer. This feature is critical for state as nature of reset and the uncertainty of how VCC actually rises in the system, the following conditions are required: 1. The VCC rise must be monotonic, 2. After reset occurs, all input and feedback setup times must be met before driving the clock pin or terms high, and 3. The clock pin, and any signals from which clock terms are derived, must remain stable during tPR. Figure 4-1. Power-up Reset Waveform Table 4-1. Parameter tPR VRST Power-up Reset Description Power-up Reset Time Power-up Reset Voltage Typ 600 3.8 Max 1000 4.5 Units ns V 4 ATF2500C 0777K–PLD–1/24/08 ATF2500C 5. Preload and Observability of Registered Outputs The ATF2500Cs registers are provided with circuitry to allow loading of each register asynchronously with either a high or a low. This feature will simplify testing since any state can be forced into the registers to control test sequencing. A VIH level on the odd I/O pins will force the appropriate register high; a VIL will force it low, independent of the polarity or other configuration bit settings. The PRELOAD state is entered by placing an 10.25V to 10.75V signal on SMP lead 42. When the preload clock SMP lead 23 is pulsed high, the data on the I/O pins is placed into the 12 registers chosen by the Q select and even/odd select pins. Register 2 observability mode is entered by placing an 10.25V to 10.75V signal on pin/lead 2. In this mode, the contents of the buried register bank will appear on the associated outputs when the OE control signals are active. Figure 5-1. Preload Waveforms Table 5-1. Preload Levels Q Select Pin State Low High Low High Even/Odd Select Low Low High High Even Q1 State after Cycle High/Low X X X Even Q2 State after Cycle X High/Low X X Odd Q1 State after Cycle X X High/Low X Odd Q2 State after Cycle X X X High/Low Level Forced on Odd I/O Pin during PRELOAD Cycle VIH/VIL VIH/VIL VIH/VIL VIH/VIL 5 0777K–PLD–1/24/08 6. Software Support All family members of the ATF2500C can be designed with Atmel-WinCUPL. Additionally, the ATF2500C may be programmed to perform the ATV2500Hs functional subset (no T-type flip-flops, pin clocking or D/T2 feedback) using the ATV2500H JEDEC file. In this case, the ATF2500C becomes a direct replacement or speed upgrade for the ATV2500H. The ATF2500C are direct replacements for the ATV2500B/BQ and the ATV2500H, including the lack of extra grounds on P4 and P26. 6.1 Software Compiler Mode Selection Table 6-1. Software Compiler Mode Selection Atmel - WinCupL Device Mnemonic V2500C V2500CPPK V2500LCC V2500CPPKLCC Pin-keeper Disabled Enabled Disabled Enabled Device ATF2500C-DIP ATF2500C-PLCC 6.2 Third Party Programmer Support Table 6-2. Third Party Programmer Support Major Third Party Device Programmers support three types of JEDEC files. Description V2500 Cross-programming. JEDEC file compatible with standard V2500 JEDEC file (Total fuses in JEDEC file = 71648). The Programmer will automatically disable the User row fuses and also disable the pin-keeper feature. The Fuse checksum will be the same as the old ATV2500H/L file. This Device type is recommended for customers that are directly migrating from an ATV2500H/L device to an ATF2500C device. V2500B Cross-programming. JEDEC file compatible with standard V2500B JEDEC file (Total fuses in JEDEC file = 71745). The Programmer will automatically disable the User row fuses and also disable the pin-keeper feature. The Fuse checksum will be the same as the old ATV2500B/BQ/BQL/BL file. This Device type is recommended for customers that are directly migrating from an ATV2500B/BQ/BQL/BL device to an ATF2500C device. Programming of User Row bits supported and Pin keeper bit is userprogrammable. (Total fuses in JEDEC file = 71816). This is the default device type and is recommended for users that have Re-compiled their Source Design files to specifically target the ATF2500C device. Device ATF2500C (V2500) ATF2500C (V2500B) ATF2500C Note: The ATF2500C has 71816 Jedec fuses. 6 ATF2500C 0777K–PLD–1/24/08 ATF2500C 7. Security Fuse Usage A single fuse is provided to prevent unauthorized copying of ATF2500C fuse patterns. Once programmed, the outputs will read programmed during verify. The security fuse should be programmed last, as its effect is immediate. The security fuse also inhibits Preload and Q2 observability. 8. Bus-friendly Pin-keeper Input and I/O All ATF2500C family members have programmable internal input and I/O pin-keeper circuits. The default condition, including when using the AT2500C/CQ family to replace the AT2500B/BQ or AT2500H, is that the pin-keepers are not activated. When pin-keepers are active, inputs or I/Os not being driven externally will maintain their last driven state. This ensures that all logic array inputs and device outputs are known states. Pinkeepers are relatively weak active circuits that can be easily overridden by TTL-compatible drivers (see input and I/O diagrams below). Enabling or disabling of the pin-keeper circuits is controlled by the device type chosen in the logic compiler device selection menu. Please refer to the Software Compiler Mode Selection table for more details. Once the pin-keeper circuits are disabled, normal termination procedures required for unused inputs and I/Os. Figure 8-1. Input Diagram PROGRAMMABLE OPTION 7 0777K–PLD–1/24/08 Figure 8-2. I/O Diagram INPUT PROGRAMMABLE OPTION 9. Functional Logic Diagram Description The ATF2500C functional logic diagram describes the interconnections between the input, feedback pins and logic cells. All interconnections are routed through the single global bus. The ATF2500Cs are straightforward and uniform PLDs. The 24 macrocells are numbered 0 through 23. Each macrocell contains 17 AND gates. All AND gates have 172 inputs. The five lower product terms provide AR1, CK1, CK2, AR2, and OE. These are: one asynchronous reset and clock per flip-flop, and an output enable. The top 12 product terms are grouped into three sum terms, which are used as shown in the macrocell diagrams. Eight synchronous preset terms are distributed in a 2/4 pattern. The first four macrocells share Preset 0, the next two share Preset 1, and so on, ending with the last two macrocells sharing Preset 7. The 14 dedicated inputs and their complements use the numbered positions in the global bus as shown. Each macrocell provides six inputs to the global bus: (left to right) feedback F2(1) true and false, flip-flop Q1 true and false, and the pin true and false. The positions occupied by these signals in the global bus are the six numbers in the bus diagram next to each macrocell. Note: 1. Either the flip-flop input (D/T2) or output (Q2) may be fed back in the ATF2500Cs. 8 ATF2500C 0777K–PLD–1/24/08 ATF2500C 9.1 Functional Logic Diagram ATF2500C Notes: 1. Pin 4 and Pin 26 are “ground” connections and are not required for PLCC, LCC and JLCC versions of ATF2500C, making them compatible with ATV2500H, ATV2500B and ATV2500BQ pinouts. 2. For DIP package, VCC = P10 and GND = P30. For, PLCC, LCC and JLCC packages, VCC = P11 and P12, GND = P33 and P34, and GND = P4, P26 (See Note 1, above). 9 0777K–PLD–1/24/08 9.2 Output Logic, Registered(1) S1 0 1 1 S2 = 0 S0 0 0 1 Terms in D/T1 8 12 8 D/T2 4 4(1) 4 Output Configuration Registered (Q1); Q2 FB Registered (Q1); Q2 FB Registered (Q1); D/T2 FB S3 0 1 Output Configuration Active Low Active High S6 0 1 Q1 CLOCK CK1 CK1 • PIN1 S4 0 1 Register 1 Type D T S7 0 1 Q2 CLOCK CK2 CK2 • PIN1 S5 0 1 Register 2 Type D T 9.3 Output Logic, Combinatorial(1) S5 X X X 1 0 S2 = 1 S1 0 0 1 1 1 S0 0 1 0 1 1 Terms in D/T1 4(1) 4 4(1) 4(1) 4 D/T2 4 4 4(1) 4 4 Output Configuration Combinatorial (8 Terms); Q2 FB Combinatorial (4 Terms); Q2 FB Combinatorial (12 Terms); Q2 FB Combinatorial (8 Terms); D/T2 FB Combinatorial (4 Terms); D/T2 FB Note: 1. These four terms are shared with D/T1. Figure 9-1. Clock Option Note: 1. These diagrams show equivalent logic functions, not necessarily the actual circuit implementation. 10 ATF2500C 0777K–PLD–1/24/08 ATF2500C 10. Absolute Maximum Ratings* *NOTICE: Temperature Under Bias................................ -55°C to +125°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Storage Temperature ..................................... -65°C to +150°C Junction Temperature ............................................. 150°C Max Note: Voltage on Any Pin with Respect to Ground .........................................-2.0V to +7.0V(1) 1. Minimum voltage is -0.6V DC which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is VCC + 0.75V DC which may overshoot to +7.0V for pulses of less than 20 ns. 11. DC and AC Operating Conditions Commercial Operating Temperature VCC Power Supply 0°C - 70°C (Ambient) 5V ± 5% Industrial -40°C - 85°C (Ambient) 5V ± 10% Military -55°C - 125°C (Case) 5V ± 10% 11.1 IIL ILO ATF2500C DC Characteristics Parameter Input Load Current Output Leakage Current Power Supply Current Standby Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage VIN = VIH or VIL, VCC = 4.5V VCC = MIN IOL = 8 mA IOL = 6 mA IOH = -100 µA IOH = -4.0 mA Com., Ind. Mil. VCC - 0.3 2.4 Condition VIN = -0.1V to VCC + 1V VOUT = -0.1V to VCC + 0.1V VCC = MAX, VIN = GND or VCC f = 0 MHz, Outputs Open MIN ≤VCC ≤MAX Com. ATF2500C Ind., Mil. -0.6 2.0 80 130 0.8 VCC + 0.75 0.5 0.5 mA V V V V V 80 Min Typ Max 10 10 110 Units µA µA mA Symbol ICC VIL VIH VOL VOH Note: 1. See ICC versus frequency characterization curves. 11 0777K–PLD–1/24/08 11.2 AC Waveforms(1) Input Pin Clock 11.3 AC Waveforms(1) Product Term Clock 11.4 AC Waveforms(1) Combinatorial Outputs and Feedback Note: 1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified. 12 ATF2500C 0777K–PLD–1/24/08 ATF2500C 11.5 ATF2500C AC Characteristics -15 Symbol tPD1 tPD2 tPD3 tPD4 tEA1 tER1 tEA2 tER2 tAW tAP tAPF Parameter Input to Non-registered Output Feedback to Non-registered Output Input to Non-registered Feedback Feedback to Non-registered Feedback Input to Output Enable Input to Output Disable Feedback to Output Enable Feedback to Output Disable Asynchronous Reset Width Asynchronous Reset to Registered Output Asynchronous Reset to Registered Feedback 8 18 15 Min Max 15 15 11 11 15 15 15 15 12 22 19 Min -20 Max 20 20 15 15 20 20 20 20 Units ns ns ns ns ns ns ns ns ns ns ns 11.6 ATF2500C Register AC Characteristics, Input Pin Clock -15 -20 Max Min Max Symbol tCOS tCFS tSIS tSFS tHS tWS tPS Parameter Clock to Output Clock to Feedback Input Setup Time Feedback Setup Time Hold Time Clock Width Clock Period External Feedback 1/(tSIS + tCOS) Min Units ns ns ns ns ns ns ns 10 0 9 9 0 6 12 52 71 83 12 15 5 0 14 14 0 7 14 11 6 40 50 71 MHz MHz MHz ns FMAXS Internal Feedback 1/(tSFS + tCFS) No Feedback 1/(tPS) tARS Asynchronous Reset/Preset Recovery Time 13 0777K–PLD–1/24/08 11.7 ATF2500C Register AC Characteristics, Product Term Clock -15 -20 Max 15 5 5 5 5 7.5 15 50 58 66 8 12 12 10 10 8 10 11 22 33 38 45 Min Max 20 16 Units ns ns ns ns ns ns ns MHz MHz MHz ns Parameter Clock to Output Clock to Feedback Input Setup Time Feedback Setup Time Hold Time Clock Width Clock Period External Feedback 1/(tSIA + tCOA) Min Symbol tCOA tCFA tSIA tSFA tHA tWA tPA FMAXA Internal Feedback 1/(tSFA + tCFA) No Feedback 1/(tPS) tARA Asynchronous Reset/Preset Recovery Time 11.8 Pin Capacitance Typ Max 6 12 Units pF pF Conditions VIN = 0V VOUT = 0V f = 1 MHz, T = 25°C (1) CIN COUT Note: 4 8 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. 11.9 Test Waveforms and Measurement Levels 11.10 Output Test Load 14 ATF2500C 0777K–PLD–1/24/08 ATF2500C 12. ATF2500C Characterization Data STAND-BY ICC VS. TEMPERATURE (VCC = 5.0V) ATF2500C OUTPUT SOURCE CURRENT VS. SUPPLY VOLTAGE (VOH = 2.4V, TA = 25°C) ICC (mA) 4.75 5.00 5.25 SUPPLY VOLTAGE (V) 5.50 100.0 90.0 80.0 70.0 60.0 50.0 -40.0 -10 IOH (mA) -20 -30 -40 4.50 25.0 TEMPERATURE (°C) 85.0 15 14 IOL (mA) ATF2500C OUTPUT SINK CURRENT VS. SUPPLY VOLTAGE (V O L = 0 .5V, T A = 2 5°C) STAND-BY ICC VS. 100.0 90.0 ICC (mA) 80.0 70.0 60.0 50.0 4.5 4.8 5.0 5.3 5.5 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (TA = 25°C) 13 12 11 10 4.50 4.75 5.00 5.25 SUPPLY VOLTAGE (V) 5.50 0.0 ATF2500C OUTPUT SOURCE CURRENT VS. OUTPUT VOLTAGE (VCC = 5.0V, TA = 25°C) -10.0 IOH (mA) 50 INPUT CURRENT (mA) -20.0 ATF2500C INPUT CLAMP CURRENT VS. INPUT VOLTAGE (VCC = 5.0V, TA = 25°C) 0 -50 -100 -150 -200 -1.4 -1.2 -1.0 -0.8 -0.6 -0.4 INPUT VOLTAGE (V) -0.2 0.0 -30.0 -40.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 OUTPUT VOLTAGE (V) ATF2500C OUTPUT SINK CURRENT VS. OUTPUT VOLTAGE (V CC = 5.0V, T A = 25°C) 50 40 IOL (mA) 30 20 10 0 40 30 20 10 0 -10 -20 -30 0.0 A TF2500C IN PU T C U R R EN T VS. IN PU T VOLTA GE (V CC = 5 .0V, T A = 2 5°C ) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 OUTPUT VOLTAGE (V) ICC (mA) 0.5 1.0 1.5 2.0 2.5 3.0 3.5 INPUT VOLTAGE (V ) 4.0 4.5 5.0 15 0777K–PLD–1/24/08 0 ATF2500C OUTPUT SOURCE CURRENT VS. OUTPUT VOLTAGE (VCC = 5.0V, TA = 25°C) TPD NORMALIZED NORMALIZED TPD VS. SUPPLY VOLTAGE 1.2 1.1 1.0 0.9 0.8 4.50 (TA = 25°C) -2 I OH (mA) -4 -6 -8 4.5 4.6 4.7 4.8 4.9 5.0 Output Voltage (V) 4.75 5.00 5.25 SUPPLY VOLTAGE (V) 5.50 30 25 TPD NORMALIZED ATF2500C OUTPUT SINK CURRENT VS. OUTPUT VOLTAGE (VCC = 5.0V, TA = 25°C) NORMALIZED TPD VS. AMBIENT TEMP (VCC = 5V) 1.1 1.0 IOL (mA) 20 15 10 5 0 0.9 0.8 -40.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 OUTPUT VOLTAGE (V) 0.0 25.0 AMBIENT TEMPERATURE (°C) 85.0 NORMALIZED TCOS VS. SUPPLY VOLTAGE 1.1 TCOS NORMALIZED (TA = 25°C) 100 90 ATF2500C SUPPLY CURRENT VS. SUPPLY VOLTAGE (Freq. = 0 MHz, TA = 25°C) 1.0 ICC (mA) 80 70 60 50 0.9 4.50 4.75 5.00 Supply Voltage (V) 5.25 5.50 4.75 5.00 5.25 SUPPLY VOLTAGE (V) 5.50 4.50 NORMALIZED TCOS VS. AMBIENT TEMP (VCC = 5V) TCOS NORMALIZED 120 ATF2500C SUPPLY CURRENT VS. INPUT FREQUENCY (VCC = 5.0V, TA = 25°C) 1.1 1.0 ICC (mA) 100 0.9 80 60 0 10 20 30 40 50 60 FREQUENCY (MHz) 70 80 90 0.8 -40.0 25.0 AMBIENT TEMPERATURE (°C) 85.0 16 ATF2500C 0777K–PLD–1/24/08 ATF2500C NORMALIZED TCOA VS. SUPPLY VOLTAGE 1.3 TCOA NORMALIZED 1.2 1.1 1.0 0.9 0.8 4.50 (TA = 25°C) 1.2 TSIS NORMALIZED 1.1 1.0 0.9 0.8 -40.0 NORMALIZED TSIS VS. AMBIENT TEMP (VCC = 5V) 4.75 5.00 SUPPLY VOLTAGE (V) 5.25 5.50 25.0 AMBIENT TEMPERATURE (°C) 85.0 NORMALIZED TCOA VS. AMBIENT TEMP (VCC = 5V) 1.1 TCOA NORMALIZED TSIA NORMALIZED 1.2 1.1 1.0 0.9 0.8 4.50 NORMALIZED TSIA VS. SUPPLY VOLTAGE (TA = 25°C) 1.0 0.9 0.8 -40.0 25.0 AMBIENT TEMPERATURE (°C) 85.0 4.75 5.00 SUPPLY VOLTAGE (V) 5.25 5.50 NORMALIZED TSIS VS. SUPPLY VOLTAGE 1.2 TSIS NORMALIZED 1.1 1.0 0.9 0.8 4.50 NORMALIZED TSIA VS. AMBIENT TEMP 1.2 TSIA NORMALIZED 1.1 1.0 0.9 0.8 -40.0 (TA = 25°C) (VCC = 5V) 4.75 5.00 SUPPLY VOLTAGE (V) 5.25 5.50 25.0 AMBIENT TEMPERATURE (°C) 85.0 17 0777K–PLD–1/24/08 13. Ordering Information 13.1 tPD (ns) Standard Package Options tCOS (ns) Ext. fMAXS (MHz) Ordering Code ATF2500C-15JC Package 44J Operation Range Commercial (0° C to 70° C) Industrial (-40° C to 85° C) Commercial (0° C to 70° C) Industrial (-40° C to 85° C) 15 10 52 ATF2500C-15JI ATF2500C-20JC ATF2500C-20PC 44J 44J 40P6 44J 40P6 20 11 40 ATF2500C-20JI ATF2500C-20PI 13.2 tPD (ns) Military Temperature Grade Standard Package Options tCOS (ns) Ext. fMAXS (MHz) Ordering Code ATF2500C-20KM Package 44K 40D6 Operation Range Military (-55° C to 125° C) 20 11 40 ATF2500C-20GM 13.3 tPD (ns) 15 20 Green Package Options (Pb/Halide-free/RoHS Compliant) tCOS (ns) 10 11 Ext. fMAXS (MHz) 52 40 Ordering Code ATF2500C-15JU ATF2500C-20PU Package 44J 40P6 Operation Range Industrial (-40° C to 85° C) Package Type 40D6 40P6 44J 44K 40-lead, Non-windowed, Ceramic Dual Inline Package (Cer DIP) 40-pin, 0.600" Wide, Plastic, Dual Inline Package (PDIP) 44-lead, Plastic J-leaded Chip Carrier (PLCC) 44-lead, Non-windowed, Ceramic J-leaded Chip Carrier (JLCC) 18 ATF2500C 0777K–PLD–1/24/08 ATF2500C 14. Packaging Information 14.1 40D6 – DIP (CerDIP) Dimensions in Millimeters and (Inches). Controlling dimension: Inches. MIL-STD 1835 D-5 Config A (Glass Sealed) 53.09(2.090) 51.82(2.040) PIN 1 15.49(0.610) 12.95(0.510) 48.26(1.900) REF 5.72(0.225) MAX SEATING PLANE 1.78(0.070) 5.08(0.200) 3.18(0.125) 1.65(0.065) 2.54(0.100)BSC 1.14(0.045) 15.70(0.620) 15.00(0.590) 0.38(0.015) 0.66(0.026) 0.36(0.014) 0.127(0.005)MIN 0.46(0.018) 0.20(0.008) 0º~ 15º REF 17.80(0.700) MAX 10/23/03 2325 Orchard Parkway San Jose, CA 95131 TITLE 40D6, 40-lead, 0.600" Wide, Non-windowed, Ceramic Dual Inline Package (Cerdip) DRAWING NO. 40D6 REV. B R 19 0777K–PLD–1/24/08 14.2 40P6 – PDIP D PIN 1 E1 A SEATING PLANE L B1 e E B A1 C eB 0º ~ 15º REF SYMBOL A A1 D E E1 B COMMON DIMENSIONS (Unit of Measure = mm) MIN – 0.381 52.070 15.240 13.462 0.356 1.041 3.048 0.203 15.494 NOM – – – – – – – – – – 2.540 TYP MAX 4.826 – 52.578 15.875 13.970 0.559 1.651 3.556 0.381 17.526 Note 2 Note 2 NOTE Notes: 1. This package conforms to JEDEC reference MS-011, Variation AC. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). B1 L C eB e 09/28/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 40P6, 40-lead (0.600"/15.24 mm Wide) Plastic Dual Inline Package (PDIP) DRAWING NO. 40P6 REV. B R 20 ATF2500C 0777K–PLD–1/24/08 ATF2500C 14.3 44J – PLCC 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER 1.14(0.045) X 45˚ 0.318(0.0125) 0.191(0.0075) E1 B E B1 D2/E2 e D1 D A A2 A1 0.51(0.020)MAX 45˚ MAX (3X) COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E Notes: 1. This package conforms to JEDEC reference MS-018, Variation AC. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. E1 D2/E2 B B1 e MIN 4.191 2.286 0.508 17.399 16.510 17.399 16.510 14.986 0.660 0.330 NOM – – – – – – – – – – 1.270 TYP MAX 4.572 3.048 – 17.653 16.662 17.653 16.662 16.002 0.813 0.533 Note 2 Note 2 NOTE 10/04/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC) DRAWING NO. 44J REV. B R 21 0777K–PLD–1/24/08 14.4 44K – JLCC D 1.14 X 45˚ D1 0.89 X 45˚ C b E1 E b1 E2 e A2 A1 0.20 C D2 c SEATING PLANE SYMBOL A A1 A2 D D1 D2 E A COMMON DIMENSIONS (Unit of Measure = mm) MIN 3.93 2.28 0.89 17.40 16.38 15.00 17.40 16.38 15.00 0.66 0.43 0.15 NOM 4.36 2.66 17.52 16.63 15.50 17.52 16.63 15.50 0.73 1.27 TYP MAX 4.57 3.04 1.14 17.65 16.89 16.00 17.65 16.89 16.00 0.81 0.58 0.30 NOTE E1 E2 b .025(.635) RADIUS MAX (3X) b1 c e Note : Refer to MIL-STD-1835C-J1 TITLE 44K, 44-lead, Non-windowed, Ceramic J-leaded Chip Carrier (JLCC) 09/18/01 DRAWING NO. 44K REV. A R 2325 Orchard Parkway San Jose, CA 95131 15. Revision History 22 ATF2500C 0777K–PLD–1/24/08 ATF2500C Revision Level – Release Date J – May 2005 K – Jan. 2008 History Added fully Green and Military temperatures packages in Section 13. ”Ordering Information” on page 18. Added 40-pin CerDIP Package Option. 23 0777K–PLD–1/24/08 Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 International Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Product Contact Web Site www.atmel.com Technical Support pld@atmel.com Sales Contact www.atmel.com/contacts Literature Requests www.atmel.com/literature Disclaimer: T he information in this document is provided in connection with Atmel products. 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