ATFS05

Features • Designed to Store Configurator Programs for Field Programmable System Level • • • • • • • • Integrated Circuits (FPSLICs) In-System Programmable (ISP) via 2-wire Bus Spare Memory Available for System Parameters Storage Low-power CMOS EEPROM Process Available in 6 mm x 6 mm x 1 mm 8-lead LAP Package (Pin Compatible Across Product Family) Emulation of Atmel’s AT24CXXX Serial EEPROMs Available in 3.3V ± 10% LV Low-power Standby Mode High-reliability – Endurance: 100,000 Write Cycles – Data Retention: 90 Years for Industrial Parts (at 85°C) and 190 Years for Commercial Parts (at 70°C) Support Device ATFS05 ATFS10 ATFS40 Advance Information Description The FPSLIC Support Devices provide an easy-to-use, cost-effective configuration memory for programming Field Programmable System Level Integrated Circuits by using a simple serial-access procedure to configure one or more FPSLIC devices. See Table 1 for a list of supported FPSLIC devices. The FPSLIC Support Device can be programmed with industry-standard programmers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable. Table 1. ATFS FPSLIC Support Devices FPSLIC Device AT94K05 AT94K10 AT94K40 FPSLIC Support Device ATFS05 ATFS10 ATFS40 Configuration Data 226520 Bits 430488 Bits 815382 Bits Spare Memory 35624 Bits 93800 Bits 233194 Bits Pin Configurations 8-lead LAP DATA CLK RESET/OE CE 1 2 3 4 8 7 6 5 VCC SER_EN CEO (A2) GND Rev. 3017C–FPSLI–07/02 1 Block Diagram SER_EN PROGRAMMING MODE LOGIC PROGRAMMING DATA SHIFT REGISTER ROW ADDRESS COUNTER ROW DECODER EEPROM CELL MATRIX POWER ON RESET BIT COUNTER TC COLUMN DECODER CLK RESET/OE CE CEO(A2) DATA Device Description The control signals for the FPSLIC Support Device (CE , RESET/OE and CCLK) interface directly with the FPSLIC control signals. All FPSLIC devices can control the entire configuration process and retrieve data from the FPSLIC Support Device without requiring an external intelligent controller. The RESET/OE and CE pins control the tri-state buffer on the DATA output pin and enable the address counter. When RESET /OE is driven Low, the configuration EEPROM resets its address counter and tri-states its DATA pin. The CE pin also controls the output of the FPSLIC Support Device. If CE is held High after the RESET/OE reset pulse, the counter is disabled and the DATA output pin is tri-stated. When OE is subsequently driven High, the counter and the DATA output pin are enabled. When RESET/OE is driven Low again, the address counter is reset and the DATA output pin is tri-stated, regardless of the state of CE. When the FPSLIC Support Device has driven out all of its data and CEO is driven Low, the device tri-states the DATA pin to avoid contention with other FPSLIC Support Devices. Upon power-up, the address counter is automatically reset. 2 ATFS05/10/40 3017C–FPSLI–07/02 ATFS05/10/40 Pin Description 8 LAP Pin 1 2 3 Name DATA CLK RESET/OE I/O I/O I I Description Tri-state DATA output for configuration. Open-collector bi-directional pin for programming. Clock input. Used to increment the internal address and bit counter for reading and programming. Output Enable (active High) and RESET (active Low) when SER_EN is High. A Low level on RESET/OE resets both the address and bit counters. A High level (with CE Low) enables the data output driver. Chip Enable input (active Low). A Low level (with OE High) allows DCLK to increment the address counter and enables the data output driver. A High level on CE disables both the address and bit counters and forces the device into a low-power standby mode. Note that this pin will not enable/disable the device in the 2-wire Serial Programming mode ( SER_EN Low). Ground pin. A 0.2 µF decoupling capacitor between VCC and GND is recommended. I I Device selection input, A2. This is used to enable (or select) the device during programming (i.e., when SER_EN is Low). A2 has an internal pull-down resistor. Serial enable must be held High during FPSLIC loading operations. Bringing SER_EN Low enables the 2-wire Serial Programming Mode. For non-ISP applications, SER_EN should be tied to VCC. +3.3V power supply pin 4 CE I 5 6 7 GND A2 SER_EN 8 VCC 3 3017C–FPSLI–07/02 FPSLIC Master Serial Mode Summary The I/O and logic functions of the FPSLIC devices are established by a configuration program. The program is loaded either automatically upon power-up, or on command, depending on the state of the mode pins. In Master Mode, the FPSLIC automatically loads the configuration program from an external memory. The FPSLIC Support Device has been designed for compatibility with the Master Mode. Most connections between the FPSLIC device and the FPSLIC Support Device are simple and self-explanatory: • • • The DATA output of the FPSLIC Support Device drives DIN of the FPSLIC devices. The master FPSLIC CCLK output drives the CLK input of the FPSLIC Support Device. SER_EN must be connected to VCC (except during ISP). Control of Configuration Programming Mode The programming mode is entered by bringing SER_EN Low. In this mode the chip can be programmed by the 2-wire serial bus. The programming is done at VCC supply only. Programming super voltages are generated inside the chip. The FPSLIC Support Device enters a low-power standby mode whenever CE is asserted High. In this mode, the ATFS05 consumes less than 50 µA of current at 3.3V. The output remains in a high-impedance state regardless of the state of the OE input. Standby Mode 4 ATFS05/10/40 3017C–FPSLI–07/02 ATFS05/10/40 Example Circuits Figure 1. FPSLIC Support Device for Programming FPSLIC Devices AT94K RESET RESET DATA0 CCLK CON INIT FPSLIC Support Device DATA CLK CE RESET/OE SER_EN VCC M2 M1 M0 GND The FPSLIC ’s bi-directional CON pin drives the CE input of the FPSLIC Support Device, while the RESET/OE input is driven by the FPSLIC’s bi-directional INIT pin. This connection works under all normal circumstances, even when the user aborts the configuration before CON has gone High. A Low level on the RESET/OE input, during FPSLIC reset, clears the FPSLIC Support Device’s internal address pointer so that the reconfiguration starts at the beginning. The spare memory can be accessed by in-system programming the ATFS through a two-wire serial interface built in the FPSLIC device. For more information, refer to the “C Code for Interfacing the FPSLIC AVR Core to AT17 Series Configuration Memories” application note, available on the Atmel web site (www.atmel.com). Figure 2. In-System Programming of FPSLIC Support Devices VCC VCC 4.7 k9 4.7 k9 DATA 1 CLK 3 5 7 9 2 4 6 8 10 VCC GND AT94K RESET RESET DATA0 CCLK CON INIT FPSLIC Support Device DATA CLK CE RESET/OE SER_EN SER_EN M2 M1 M0 GND 5 3017C–FPSLI–07/02 Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125 °C Storage Temperature ..................................... -65 °C to +150°C Voltage on Any Pin with Respect to Ground ..............................-0.1V to VCC +0.5V Supply Voltage (VCC ) .........................................-0.5V to +7.0V Maximum Soldering Temp. (10 sec. @ 1/16 in.)............. 260°C ESD (RZAP = 1.5K, CZAP = 100 pF)................................. 2000V *NOTICE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those listed under operating conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability. Operating Conditions ATFS05/10/40 Symbol Description Commercial VCC Industrial Supply voltage relative to GND -0°C to +70°C Supply voltage relative to GND -40°C to +85°C Min 3.0 3.0 Max 3.6 3.6 Units V V 6 ATFS05/10/40 3017C–FPSLI–07/02 ATFS05/10/40 DC Characteristics – ATFS05 VCC = 3.3V ± 10% Symbol VIH VIL VOH VOL VOH VOL ICCA IL ICCS Description High-level Input Voltage Low-level Input Voltage High-level Output Voltage (IOH = -2.5 mA) Low-level Output Voltage (IOL = +3 mA) High-level Output Voltage (IOH = -2 mA) Low-level Output Voltage (IOL = +3 mA) Supply Current, Active Mode Input or Output Leakage Current (VIN = VCC or GND) Commercial Supply Current, Standby Mode Industrial 100 µA -10 2.4 Industrial 0.4 5 10 50 V mA µA µA Commercial 0.4 V V Min 2.0 0 2.4 Max VCC 0.8 Units V V V DC Characteristics – ATFS10/40 VCC = 3.3V ± 10% Symbol VIH VIL VOH VOL VOH VOL ICCA IL ICCS Description High-level Input Voltage Low-level Input Voltage High-level Output Voltage (IOH = -2.5 mA) Low-level Output Voltage (IOL = +3 mA) High-level Output Voltage (IOH = -2 mA) Low-level Output Voltage (IOL = +3 mA) Supply Current, Active Mode Input or Output Leakage Current (VIN = VCC or GND) Commercial Supply Current, Standby Mode Industrial 100 µA -10 2.4 Industrial 0.4 5 10 100 V mA µA µA Commercial 0.4 V V Min 2.0 0.0 2.4 Max VCC 0.8 Units V V V 7 3017C–FPSLI–07/02 AC Characteristics CE TSCE RESET/OE TLC CLK TOE TCE DATA TOH TCAC TOH TDF THC THOE TSCE THCE AC Characteristics When Cascading RESET/OE CE CLK TCDF DATA LAST BIT TOCK CEO TOCE TOCE TOOE FIRST BIT 8 ATFS05/10/40 3017C–FPSLI–07/02 ATFS05/10/40 AC Characteristics for ATFS05 VCC = 3.3V ± 10% Commercial Symbol TOE(1) TCE(1) TCAC TOH TDF TLC THC TSCE THCE THOE FMAX Notes: (2) (1) Industrial Min Max 55 60 80 0 Units ns ns ns ns 55 25 25 60 0 25 10 ns ns ns ns ns ns MHz Description OE to Data Delay CE to Data Delay CLK to Data Delay Data Hold from CE, OE, or CLK CE or OE to Data Float Delay CLK Low Time CLK High Time CE Setup Time to CLK (to guarantee proper counting) CE Hold Time from CLK (to guarantee proper counting) OE High Time (guarantees counter is reset) Maximum Input Clock Frequency Min Max 50 60 75 0 55 25 25 35 0 25 10 1. AC test lead = 50 pF. 2. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady-state active levels. AC Characteristics for ATFS05 when Cascading VCC = 3.3V ± 10% Commercial Symbol TCDF Note: (1) Industrial Min Max 60 8 Units ns MHz Description CLK to Data Float Delay Maximum Input Clock Frequency Min Max 60 FMAX 8 1. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady state active levels. 9 3017C–FPSLI–07/02 AC Characteristics for ATFS10/40 VCC = 3.3V ± 10% Commercial Symbol TOE(1) TCE(1) TCAC TOH TDF TLC THC TSCE THCE THOE FMAX Notes: (2) (1) Industrial Min Max 55 60 60 0 Units ns ns ns ns 50 25 25 35 0 25 10 ns ns ns ns ns ns MHz Description OE to Data Delay CE to Data Delay CLK to Data Delay Data Hold From CE, OE, or CLK CE or OE to Data Float Delay CLK Low Time CLK High Time CE Setup Time to CLK (to guarantee proper counting) CE Hold Time from CLK (to guarantee proper counting) OE High Time (guarantees counter is reset) MAX Input Clock Frequency Min Max 50 55 55 0 50 25 25 30 0 25 15 1. AC test load = 50 pF. 2. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady state active levels. AC Characteristics for ATFS10/40 when Cascading VCC = 3.3V ± 10% Commercial Symbol TCDF (1) Industrial Min Max 50 10 Units ns MHz Description CLK to Data Float Delay MAX Input Clock Frequency Min Max 50 FMAX Note: 12.5 1. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady state active levels. 10 ATFS05/10/40 3017C–FPSLI–07/02 ATFS05/10/40 Thermal Resistance Coefficients(1) θJA [°C/W] Airflow = 0 ft/min 115.71 135.71 Device ATFS05 ATFS10/40 Note: Package Type Leadless Array Package (LAP) Leadless Array Package (LAP) 8CN4 8CN4 θJC [°C/W] 45 45 1. For more information refer to the “Thermal Characteristics of Atmel’s Packages” application note, available on the Atmel web site. 11 3017C–FPSLI–07/02 Ordering Information Ordering Code Package 8CN4 8CN4 8CN4 8CN4 8CN4 8CN4 Operation Range Commercial (0°C to 70°C) Industrial (-40°C to 85°C) ATFS05-CC ATFS10-CC ATFS40-CC ATFS05-CI ATFS10-CI ATFS40-CI Package Type 8CN4 8-lead (6 x 6 x 1.04 mm Body), Lead Pitch 1.27 mm, Leadless Array Package (LAP) 12 ATFS05/10/40 3017C–FPSLI–07/02 ATFS05/10/40 Packaging Information 8CN4 – LAP Marked Pin1 Indentifier E D A A1 Top View 0.10 mm TYP Side View L1 Pin1 Corner 8 1 e 7 2 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN 0.94 0.30 0.45 5.89 4.89 NOM 1.04 0.34 0.50 5.99 5.99 1.27 BSC 1.10 REF 0.95 1.25 1.00 1.30 1.05 1.35 1 1 MAX 1.14 0.38 0.55 6.09 6.09 1 NOTE 6 3 A b 5 4 A1 b D E e1 L e e1 L L1 Bottom View Note: 1. Metal Pad Dimensions. 11/14/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 8CN4, 8-lead (6 x 6 x 1.04 mm Body), Lead Pitch 1.27 mm, Leadless Array Package (LAP) DRAWING NO. 8CN4 REV. A R 13 3017C–FPSLI–07/02 Atmel Headquarters Corporate Headquarters 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 487-2600 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany TEL (49) 71-31-67-0 FAX (49) 71-31-67-2340 1150 East Cheyenne Mtn. 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