ATMEGA128A-MUR

Features • High-performance, Low-power AVR® 8-bit Microcontroller • Advanced RISC Architecture – 133 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers + Peripheral Control Registers – Fully Static Operation – Up to 16 MIPS Throughput at 16 MHz – On-chip 2-cycle Multiplier High Endurance Non-volatile Memory segments – 128K Bytes of In-System Self-programmable Flash program memory – 4K Bytes EEPROM – 4K Bytes Internal SRAM – Write/Erase cycles: 10,000 Flash/100,000 EEPROM – Data retention: 20 years at 85°C/100 years at 25°C(1) – Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program True Read-While-Write Operation – Up to 64K Bytes Optional External Memory Space – Programming Lock for Software Security – SPI Interface for In-System Programming JTAG (IEEE std. 1149.1 Compliant) Interface – Boundary-scan Capabilities According to the JTAG Standard – Extensive On-chip Debug Support – Programming of Flash, EEPROM, Fuses and Lock Bits through the JTAG Interface Peripheral Features – Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes – Two Expanded 16-bit Timer/Counters with Separate Prescaler, Compare Mode and Capture Mode – Real Time Counter with Separate Oscillator – Two 8-bit PWM Channels – 6 PWM Channels with Programmable Resolution from 2 to 16 Bits – Output Compare Modulator – 8-channel, 10-bit ADC 8 Single-ended Channels 7 Differential Channels 2 Differential Channels with Programmable Gain at 1x, 10x, or 200x – Byte-oriented Two-wire Serial Interface – Dual Programmable Serial USARTs – Master/Slave SPI Serial Interface – Programmable Watchdog Timer with On-chip Oscillator – On-chip Analog Comparator Special Microcontroller Features – Power-on Reset and Programmable Brown-out Detection – Internal Calibrated RC Oscillator – External and Internal Interrupt Sources – Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and Extended Standby – Software Selectable Clock Frequency – ATmega103 Compatibility Mode Selected by a Fuse – Global Pull-up Disable I/O and Packages – 53 Programmable I/O Lines – 64-lead TQFP and 64-pad QFN/MLF Operating Voltages – 2.7 - 5.5V Speed Grades – 0 - 16 MHz • • 8-bit Microcontroller with 128K Bytes In-System Programmable Flash ATmega128A Summary • • • • • Rev. 8151GS–AVR–07/10 ATmega128A 1. Pin Configurations Figure 1-1. Pinout ATmega128A Note: The Pinout figure applies to both TQFP and MLF packages. The bottom pad under the QFN/MLF package should be soldered to ground. 2. Overview The ATmega128A is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega128A achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. (OC2/OC1C) PB7 TOSC2/PG3 TOSC1/PG4 RESET VCC GND XTAL2 XTAL1 (SCL/INT0) PD0 (SDA/INT1) PD1 (RXD1/INT2) PD2 (TXD1/INT3) PD3 (ICP1) PD4 (XCK1) PD5 (T1) PD6 (T2) PD7 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PEN RXD0/(PDI) PE0 (TXD0/PDO) PE1 (XCK0/AIN0) PE2 (OC3A/AIN1) PE3 (OC3B/INT4) PE4 (OC3C/INT5) PE5 (T3/INT6) PE6 (ICP3/INT7) PE7 (SS) PB0 (SCK) PB1 (MOSI) PB2 (MISO) PB3 (OC0) PB4 (OC1A) PB5 (OC1B) PB6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AVCC GND AREF PF0 (ADC0) PF1 (ADC1) PF2 (ADC2) PF3 (ADC3) PF4 (ADC4/TCK) PF5 (ADC5/TMS) PF6 (ADC6/TDO) PF7 (ADC7/TDI) GND VCC PA0 (AD0) PA1 (AD1) PA2 (AD2) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PA3 (AD3) PA4 (AD4) PA5 (AD5) PA6 (AD6) PA7 (AD7) PG2(ALE) PC7 (A15) PC6 (A14) PC5 (A13) PC4 (A12) PC3 (A11) PC2 (A10) PC1 (A9) PC0 (A8) PG1(RD) PG0(WR) 19 8151GS–AVR–07/10 ATmega128A 2.1 Block Diagram Block Diagram Figure 2-1. PF0 - PF7 PA0 - PA7 PC0 - PC7 VCC GND PORTF DRIVERS PORTA DRIVERS PORTC DRIVERS DATA REGISTER PORTF DATA DIR. REG. PORTF DATA REGISTER PORTA DATA DIR. REG. PORTA DATA REGISTER PORTC DATA DIR. REG. PORTC 8-BIT DATA BUS AVCC AGND AREF PROGRAM COUNTER STACK POINTER WATCHDOG TIMER ADC INTERNAL OSCILLATOR CALIB. OSC OSCILLATOR JTAG TAP OSCILLATOR ON-CHIP DEBUG PROGRAM FLASH SRAM MCU CONTROL REGISTER TIMING AND CONTROL BOUNDARYSCAN INSTRUCTION REGISTER GENERAL PURPOSE REGISTERS X Y Z TIMER/ COUNTERS PEN PROGRAMMING LOGIC INSTRUCTION DECODER INTERRUPT UNIT CONTROL LINES ALU EEPROM STATUS REGISTER USART0 SPI USART1 TWO-WIRE SERIAL INTERFACE ANALOG COMPARATOR DATA REGISTER PORTE DATA DIR. REG. PORTE DATA REGISTER PORTB DATA DIR. REG. PORTB DATA REGISTER PORTD DATA DIR. REG. PORTD DATA REG. PORTG DATA DIR. REG. PORTG + - PORTE DRIVERS PORTB DRIVERS PORTD DRIVERS PORTG DRIVERS PE0 - PE7 PB0 - PB7 PD0 - PD7 PG0 - PG4 RESET XTAL1 XTAL2 19 8151GS–AVR–07/10 ATmega128A The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATmega128A provides the following features: 128K bytes of In-System Programmable Flash with Read-While-Write capabilities, 4K bytes EEPROM, 4K bytes SRAM, 53 general purpose I/O lines, 32 general purpose working registers, Real Time Counter (RTC), four flexible Timer/Counters with compare modes and PWM, 2 USARTs, a byte oriented Two-wire Serial Interface, an 8-channel, 10-bit ADC with optional differential input stage with programmable gain, programmable Watchdog Timer with Internal Oscillator, an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface, also used for accessing the On-chip Debug system and programming and six software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run. The device is manufactured using Atmel’s high-density nonvolatile memory technology. The Onchip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program can use any interface to download the application program in the application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega128A is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega128A AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. 2.2 ATmega103 and ATmega128A Compatibility The ATmega128A is a highly complex microcontroller where the number of I/O locations supersedes the 64 I/O locations reserved in the AVR instruction set. To ensure backward compatibility with the ATmega103, all I/O locations present in ATmega103 have the same location in ATmega128A. Most additional I/O locations are added in an Extended I/O space starting from $60 to $FF, (i.e., in the ATmega103 internal RAM space). These locations can be reached by using LD/LDS/LDD and ST/STS/STD instructions only, not by using IN and OUT instructions. The relocation of the internal RAM space may still be a problem for ATmega103 users. Also, the increased number of interrupt vectors might be a problem if the code uses absolute addresses. To solve these problems, an ATmega103 compatibility mode can be selected by programming the fuse M103C. In this mode, none of the functions in the Extended I/O space are in use, so the internal RAM is located as in ATmega103. Also, the Extended Interrupt vectors are removed. 19 8151GS–AVR–07/10 ATmega128A The ATmega128A is 100% pin compatible with ATmega103, and can replace the ATmega103 on current Printed Circuit Boards. The application note “Replacing ATmega103 by ATmega128A” describes what the user should be aware of replacing the ATmega103 by an ATmega128A. 2.2.1 ATmega103 Compatibility Mode By programming the M103C fuse, the ATmega128 will be compatible with the ATmega103 regards to RAM, I/O pins and interrupt vectors as described above. However, some new features in ATmega128 are not available in this compatibility mode, these features are listed below: • One USART instead of two, Asynchronous mode only. Only the eight least significant bits of the Baud Rate Register is available. • One 16 bits Timer/Counter with two compare registers instead of two 16-bit Timer/Counters with three compare registers. • Two-wire serial interface is not supported. • Port C is output only. • Port G serves alternate functions only (not a general I/O port). • Port F serves as digital input only in addition to analog input to the ADC. • Boot Loader capabilities is not supported. • It is not possible to adjust the frequency of the internal calibrated RC Oscillator. • The External Memory Interface can not release any Address pins for general I/O, neither configure different wait-states to different External Memory Address sections. • In addition, there are some other minor differences to make it more compatible to ATmega103: • Only EXTRF and PORF exists in MCUCSR. • Timed sequence not required for Watchdog Time-out change. • External Interrupt pins 3 - 0 serve as level interrupt only. • USART has no FIFO buffer, so data overrun comes earlier. Unused I/O bits in ATmega103 should be written to 0 to ensure same operation in ATmega128. 2.3 2.3.1 Pin Descriptions VCC Digital supply voltage. 2.3.2 GND Ground. 2.3.3 Port A (PA7:PA0) Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various special features of the ATmega128A as listed on page 73. 19 8151GS–AVR–07/10 ATmega128A 2.3.4 Port B (PB7:PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATmega128A as listed on page 74. 2.3.5 Port C (PC7:PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port C also serves the functions of special features of the ATmega128A as listed on page 76. In ATmega103 compatibility mode, Port C is output only, and the port C pins are not tri-stated when a reset condition becomes active. Note: The ATmega128A is by default shipped in ATmega103 compatibility mode. Thus, if the parts are not programmed before they are put on the PCB, PORTC will be output during first power up, and until the ATmega103 compatibility mode is disabled. 2.3.6 Port D (PD7:PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATmega128A as listed on page 78. 2.3.7 Port E (PE7:PE0) Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port E also serves the functions of various special features of the ATmega128A as listed on page 81. 2.3.8 Port F (PF7:PF0) Port F serves as the analog inputs to the A/D Converter. Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide internal pull-up resistors (selected for each bit). The Port F output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port F pins that are externally pulled low will source current if the pull-up resistors are activated. The Port F pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the 19 8151GS–AVR–07/10 ATmega128A JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a Reset occurs. The TDO pin is tri-stated unless TAP states that shift out data are entered. Port F also serves the functions of the JTAG interface. In ATmega103 compatibility mode, Port F is an input Port only. 2.3.9 Port G (PG4:PG0) Port G is a 5-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port G output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port G pins that are externally pulled low will source current if the pull-up resistors are activated. The Port G pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port G also serves the functions of various special features. The port G pins are tri-stated when a reset condition becomes active, even if the clock is not running. In ATmega103 compatibility mode, these pins only serves as strobes signals to the external memory as well as input to the 32 kHz Oscillator, and the pins are initialized to PG0 = 1, PG1 = 1, and PG2 = 0 asynchronously when a reset condition becomes active, even if the clock is not running. PG3 and PG4 are oscillator pins. 2.3.10 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in “System and Reset Characteristics” on page 324. Shorter pulses are not guaranteed to generate a reset. 2.3.11 XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. 2.3.12 XTAL2 Output from the inverting Oscillator amplifier. 2.3.13 AVCC AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. 2.3.14 AREF AREF is the analog reference pin for the A/D Converter. 2.3.15 PEN PEN is a programming enable pin for the SPI Serial Programming mode, and is internally pulled high . By holding this pin low during a Power-on Reset, the device will enter the SPI Serial Programming mode. PEN has no function during normal operation. 19 8151GS–AVR–07/10 ATmega128A 3. Resources A comprehensive set of development tools, application notes, and datasheets are available for download on http://www.atmel.com/avr. ATmega128A/L rev. A - M characterization is found in the ATmega128A Appendix B. Note: 1. 4. Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. 19 8151GS–AVR–07/10 ATmega128A 5. Register Summary (Continued) Address ($FF) : ($9E) ($9D) ($9C) ($9B) ($9A) ($99) ($98) ($97) ($96) ($95) ($94) ($93) ($92) ($91) ($90) ($8F) ($8E) ($8D) ($8C) ($8B) ($8A) ($89) ($88) ($87) ($86) ($85) ($84) ($83) ($82) ($81) ($80) ($7F) ($7E) ($7D) ($7C) ($7B) ($7A) ($79) ($78) ($77) ($76) ($75) ($74) ($73) ($72) ($71) ($70) ($6F) ($6E) ($6D) ($6C) ($6B) ($6A) ($69) ($68) ($67) ($66) ($65) ($64) ($63) Name Reserved Reserved Reserved UCSR1C UDR1 UCSR1A UCSR1B UBRR1L UBRR1H Reserved Reserved UCSR0C Reserved Reserved Reserved Reserved UBRR0H Reserved Reserved Reserved TCCR3C TCCR3A TCCR3B TCNT3H TCNT3L OCR3AH OCR3AL OCR3BH OCR3BL OCR3CH OCR3CL ICR3H ICR3L Reserved Reserved ETIMSK ETIFR Reserved TCCR1C OCR1CH OCR1CL Reserved Reserved Reserved TWCR TWDR TWAR TWSR TWBR OSCCAL Reserved XMCRA XMCRB Reserved EICRA Reserved SPMCSR Reserved Reserved PORTG DDRG PING Bit 7 – – – – RXC1 RXCIE1 – – – – – – – – – – – – FOC3A COM3A1 ICNC3 Bit 6 – – – UMSEL1 TXC1 TXCIE1 – – – UMSEL0 – – – – – – – – FOC3B COM3A0 ICES3 Bit 5 – – – UPM11 UDRE1 UDRIE1 – – – UPM01 – – – – – – – – FOC3C COM3B1 – Bit 4 – – – UPM10 FE1 RXEN1 – – – UPM00 – – – – – – – – – COM3B0 WGM33 Bit 3 – – – USBS1 DOR1 TXEN1 Bit 2 – – – UCSZ11 UPE1 UCSZ12 Bit 1 – – – UCSZ10 U2X1 RXB81 Bit 0 – – – UCPOL1 MPCM1 TXB81 Page 195 192 193 194 197 197 USART1 I/O Data Register USART1 Baud Rate Register Low USART1 Baud Rate Register High – – USBS0 – – – – – – – – COM3C1 WGM32 – – UCSZ01 – – – – – – – – COM3C0 CS32 – – UCSZ00 – – – – – – – – WGM31 CS31 – – UCPOL0 – – – – 195 USART0 Baud Rate Register High – – – – WGM30 CS30 197 138 134 137 139 139 140 140 140 140 140 140 141 141 Timer/Counter3 – Counter Register High Byte Timer/Counter3 – Counter Register Low Byte Timer/Counter3 – Output Compare Register A High Byte Timer/Counter3 – Output Compare Register A Low Byte Timer/Counter3 – Output Compare Register B High Byte Timer/Counter3 – Output Compare Register B Low Byte Timer/Counter3 – Output Compare Register C High Byte Timer/Counter3 – Output Compare Register C Low Byte Timer/Counter3 – Input Capture Register High Byte Timer/Counter3 – Input Capture Register Low Byte – – – – – FOC1A – – – – – FOC1B – – TICIE3 ICF3 – FOC1C – – OCIE3A OCF3A – – – – OCIE3B OCF3B – – – – TOIE3 TOV3 – – – – OCIE3C OCF3C – – – – OCIE1C OCF1C – – 142 143 138 140 140 Timer/Counter1 – Output Compare Register C High Byte Timer/Counter1 – Output Compare Register C Low Byte – – – TWINT TWA6 TWS7 – – – TWEA TWA5 TWS6 – – – TWSTA TWA4 TWS5 – – – TWSTO TWA3 TWS4 – – – TWWC TWA2 TWS3 – – – TWEN TWA1 – – – – – TWA0 TWPS1 – – – TWIE TWGCE TWPS0 226 228 229 228 226 44 Two-wire Serial Interface Data Register Two-wire Serial Interface Bit Rate Register Oscillator Calibration Register – – XMBK – ISC31 – SPMIE – – – – – – SRL2 – – ISC30 – RWWSB – – – – – – SRL1 – – ISC21 – – – – – – – – SRL0 – – ISC20 – RWWSRE – – PORTG4 DDG4 PING4 – SRW01 – – ISC11 – BLBSET – – PORTG3 DDG3 PING3 – SRW00 XMM2 – ISC10 – PGWRT – – PORTG2 DDG2 PING2 – SRW11 XMM1 – ISC01 – PGERS – – PORTG1 DDG1 PING1 XMM0 – ISC00 – SPMEN – – PORTG0 DDG0 PING0 – 34 35 90 289 89 89 89 19 8151GS–AVR–07/10 ATmega128A 5. Register Summary (Continued) Address ($62) ($61) ($60) $3F ($5F) $3E ($5E) $3D ($5D) $3C ($5C) $3B ($5B) $3A ($5A) $39 ($59) $38 ($58) $37 ($57) $36 ($56) $35 ($55) $34 ($54) $33 ($53) $32 ($52) $31 ($51) $30 ($50) $2F ($4F) $2E ($4E) $2D ($4D) $2C ($4C) $2B ($4B) $2A ($4A) $29 ($49) $28 ($48) $27 ($47) $26 ($46) $25 ($45) $24 ($44) $23 ($43) $22 ($42) $21 ($41) $20 ($40) $1F ($3F) $1E ($3E) $1D ($3D) $1C ($3C) $1B ($3B) $1A ($3A) $19 ($39) $18 ($38) $17 ($37) $16 ($36) $15 ($35) $14 ($34) $13 ($33) $12 ($32) $11 ($31) $10 ($30) $0F ($2F) $0E ($2E) $0D ($2D) $0C ($2C) $0B ($2B) $0A ($2A) $09 ($29) $08 ($28) $07 ($27) $06 ($26) $05 ($25) $04 ($24) $03 ($23) Name PORTF DDRF Reserved SREG SPH SPL XDIV RAMPZ EICRB EIMSK EIFR TIMSK TIFR MCUCR MCUCSR TCCR0 TCNT0 OCR0 ASSR TCCR1A TCCR1B TCNT1H TCNT1L OCR1AH OCR1AL OCR1BH OCR1BL ICR1H ICR1L TCCR2 TCNT2 OCR2 OCDR WDTCR SFIOR EEARH EEARL EEDR EECR PORTA DDRA PINA PORTB DDRB PINB PORTC DDRC PINC PORTD DDRD PIND SPDR SPSR SPCR UDR0 UCSR0A UCSR0B UBRR0L ACSR ADMUX ADCSRA ADCH ADCL PORTE Bit 7 PORTF7 DDF7 – I SP15 SP7 XDIVEN – ISC71 INT7 INTF7 OCIE2 OCF2 SRE JTD FOC0 Bit 6 PORTF6 DDF6 – T SP14 SP6 XDIV6 – ISC70 INT6 INTF6 TOIE2 TOV2 SRW10 – WGM00 Bit 5 PORTF5 DDF5 – H SP13 SP5 XDIV5 – ISC61 INT5 INTF5 TICIE1 ICF1 SE – COM01 Bit 4 PORTF4 DDF4 – S SP12 SP4 XDIV4 – ISC60 INT4 INTF4 OCIE1A OCF1A SM1 JTRF COM00 Bit 3 PORTF3 DDF3 – V SP11 SP3 XDIV3 – ISC51 INT3 INTF3 OCIE1B OCF1B SM0 WDRF WGM01 Bit 2 PORTF2 DDF2 – N SP10 SP2 XDIV2 – ISC50 INT2 INTF TOIE1 TOV1 SM2 BORF CS02 Bit 1 PORTF1 DDF1 – Z SP9 SP1 XDIV1 – ISC41 INT1 INTF1 OCIE0 OCF0 IVSEL EXTRF CS01 Bit 0 PORTF0 DDF0 – C SP8 SP0 XDIV0 RAMPZ0 ISC40 INT0 INTF0 TOIE0 TOV0 IVCE PORF CS00 Page 89 89 10 13 13 38 14 91 92 92 110, 141, 162 110, 143, 162 33, 50, 63 56, 257 106 109 109 Timer/Counter0 (8 Bit) Timer/Counter0 Output Compare Register – COM1A1 ICNC1 – COM1A0 ICES1 – COM1B1 – – COM1B0 WGM13 AS0 COM1C1 WGM12 TCN0UB COM1C0 CS12 OCR0UB WGM11 CS11 TCR0UB WGM10 CS10 109 134 137 139 139 139 139 139 139 140 140 Timer/Counter1 – Counter Register High Byte Timer/Counter1 – Counter Register Low Byte Timer/Counter1 – Output Compare Register A High Byte Timer/Counter1 – Output Compare Register A Low Byte Timer/Counter1 – Output Compare Register B High Byte Timer/Counter1 – Output Compare Register B Low Byte Timer/Counter1 – Input Capture Register High Byte Timer/Counter1 – Input Capture Register Low Byte FOC2 WGM20 COM21 COM20 WGM21 CS22 CS21 CS20 Timer/Counter2 (8 Bit) Timer/Counter2 Output Compare Register IDRD/OCDR7 159 161 162 OCDR6 – – – OCDR5 – – – OCDR4 WDCE – – OCDR3 WDE ACME OCDR2 WDP2 PUD OCDR1 WDP1 PSR0 OCDR0 WDP0 PSR321 276 57 86, 111, 146, 231 30 30 30 – TSM – EEPROM Address Register High EEPROM Address Register Low Byte EEPROM Data Register – PORTA7 DDA7 PINA7 PORTB7 DDB7 PINB7 PORTC7 DDC7 PINC7 PORTD7 DDD7 PIND7 SPIF SPIE RXC0 RXCIE0 ACD REFS1 ADEN – PORTA6 DDA6 PINA6 PORTB6 DDB6 PINB6 PORTC6 DDC6 PINC6 PORTD6 DDD6 PIND6 WCOL SPE TXC0 TXCIE0 ACBG REFS0 ADSC – PORTA5 DDA5 PINA5 PORTB5 DDB5 PINB5 PORTC5 DDC5 PINC5 PORTD5 DDD5 PIND5 – DORD UDRE0 UDRIE0 ACO ADLAR ADFR – PORTA4 DDA4 PINA4 PORTB4 DDB4 PINB4 PORTC4 DDC4 PINC4 PORTD4 DDD4 PIND4 – MSTR FE0 RXEN0 ACI MUX4 ADIF EERIE PORTA3 DDA3 PINA3 PORTB3 DDB3 PINB3 PORTC3 DDC3 PINC3 PORTD3 DDD3 PIND3 – CPOL DOR0 TXEN0 ACIE MUX3 ADIE EEMWE PORTA2 DDA2 PINA2 PORTB2 DDB2 PINB2 PORTC2 DDC2 PINC2 PORTD2 DDD2 PIND2 – CPHA UPE0 UCSZ02 ACIC MUX2 ADPS2 EEWE PORTA1 DDA1 PINA1 PORTB1 DDB1 PINB1 PORTC1 DDC1 PINC1 PORTD1 DDD1 PIND1 – SPR1 U2X0 RXB80 ACIS1 MUX1 ADPS1 EERE PORTA0 DDA0 PINA0 PORTB0 DDB0 PINB0 PORTC0 DDC0 PINC0 PORTD0 DDD0 PIND0 SPI2X SPR0 MPCM0 TXB80 ACIS0 MUX0 ADPS0 30 87 87 87 87 87 87 87 87 88 88 88 88 173 173 171 192 193 194 197 231 245 247 248 248 SPI Data Register USART0 I/O Data Register USART0 Baud Rate Register Low ADC Data Register High Byte ADC Data Register Low byte PORTE7 PORTE6 PORTE5 PORTE4 PORTE3 PORTE2 PORTE1 PORTE0 88 19 8151GS–AVR–07/10 ATmega128A 5. Register Summary (Continued) Address $02 ($22) $01 ($21) $00 ($20) Name DDRE PINE PINF Bit 7 DDE7 PINE7 PINF7 Bit 6 DDE6 PINE6 PINF6 Bit 5 DDE5 PINE5 PINF5 Bit 4 DDE4 PINE4 PINF4 Bit 3 DDE3 PINE3 PINF3 Bit 2 DDE2 PINE2 PINF2 Bit 1 DDE1 PINE1 PINF1 Bit 0 DDE0 PINE0 PINF0 Page 88 88 89 Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only. 19 8151GS–AVR–07/10 ATmega128A 6. Instruction Set Summary (Continued) Mnemonics ADD ADC ADIW SUB SUBI SBC SBCI SBIW AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER MUL MULS MULSU FMUL FMULS FMULSU RJMP IJMP JMP RCALL ICALL CALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC Rd,Rr Rd,Rr Rd,Rr Rd,K Rr, b Rr, b P, b P, b s, k s, k k k k k k k k k k k k k k k k k k Operands Rd, Rr Rd, Rr Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd Rd Rd,K Rd,K Rd Rd Rd Rd Rd Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr k Description Add two Registers Add with Carry two Registers Add Immediate to Word Subtract two Registers Subtract Constant from Register Subtract with Carry two Registers Subtract with Carry Constant from Reg. Subtract Immediate from Word Logical AND Registers Logical AND Register and Constant Logical OR Registers Logical OR Register and Constant Exclusive OR Registers One’s Complement Two’s Complement Set Bit(s) in Register Clear Bit(s) in Register Increment Decrement Test for Zero or Minus Clear Register Set Register Multiply Unsigned Multiply Signed Multiply Signed with Unsigned Fractional Multiply Unsigned Fractional Multiply Signed Fractional Multiply Signed with Unsigned Relative Jump Indirect Jump to (Z) Direct Jump Relative Subroutine Call Indirect Call to (Z) Direct Subroutine Call Subroutine Return Interrupt Return Compare, Skip if Equal Compare Compare with Carry Compare Register with Immediate Skip if Bit in Register Cleared Skip if Bit in Register is Set Skip if Bit in I/O Register Cleared Skip if Bit in I/O Register is Set Branch if Status Flag Set Branch if Status Flag Cleared Branch if Equal Branch if Not Equal Branch if Carry Set Branch if Carry Cleared Branch if Same or Higher Branch if Lower Branch if Minus Branch if Plus Branch if Greater or Equal, Signed Branch if Less Than Zero, Signed Branch if Half Carry Flag Set Branch if Half Carry Flag Cleared Branch if T Flag Set Branch if T Flag Cleared Operation Rd ← Rd + Rr Rd ← Rd + Rr + C Rdh:Rdl ← Rdh:Rdl + K Rd ← Rd - Rr Rd ← Rd - K Rd ← Rd - Rr - C Rd ← Rd - K - C Rdh:Rdl ← Rdh:Rdl - K Rd ← Rd • Rr Rd ← Rd • K Rd ← Rd v Rr Rd ← Rd v K Rd ← Rd ⊕ Rr Rd ← $FF − Rd Rd ← $00 − Rd Rd ← Rd v K Rd ← Rd • ($FF - K) Rd ← Rd + 1 Rd ← Rd − 1 Rd ← Rd • Rd Rd ← Rd ⊕ Rd Rd ← $FF R1:R0 ← Rd x Rr R1:R0 ← Rd x Rr R1:R0 ← Rd x Rr Flags Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None Z,C Z,C Z,C Z,C Z,C Z,C None None None None None None None I None Z, N,V,C,H Z, N,V,C,H Z, N,V,C,H None None None None None None None None None None None None None None None None None None None None #Clocks 1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 3 3 3 4 4 4 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 ARITHMETIC AND LOGIC INSTRUCTIONS 1 R1:R0 ← (Rd x Rr)