ATMEGA162V-8PI

Features • High-performance, Low-power AVR® 8-bit Microcontroller • Advanced RISC Architecture – 131 Powerful Instructions – Most Single-clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 16 MIPS Throughput at 16 MHz – On-chip 2-cycle Multiplier Non-volatile Program and Data Memories – 16K Bytes of In-System Self-programmable Flash Endurance: 10,000 Write/Erase Cycles – Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program True Read-While-Write Operation – 512 Bytes EEPROM Endurance: 100,000 Write/Erase Cycles – 1K Bytes Internal SRAM – Up to 64K Bytes Optional External Memory Space – Programming Lock for Software Security JTAG (IEEE std. 1149.1 Compliant) Interface – Boundary-scan Capabilities According to the JTAG Standard – Extensive On-chip Debug Support – Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface Peripheral Features – Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes – Two 16-bit Timer/Counters with Separate Prescalers, Compare Modes, and Capture Modes – Real Time Counter with Separate Oscillator – Six PWM Channels – Dual Programmable Serial USARTs – Master/Slave SPI Serial Interface – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator Special Microcontroller Features – Power-on Reset and Programmable Brown-out Detection – Internal Calibrated RC Oscillator – External and Internal Interrupt Sources – Five Sleep Modes: Idle, Power-save, Power-down, Standby, and Extended Standby I/O and Packages – 35 Programmable I/O Lines – 40-pin PDIP, 44-lead TQFP, and 44-pad MLF Operating Voltages – 1.8 - 5.5V for ATmega162V – 2.7 - 5.5V for ATmega162 Speed Grades – 0 - 8 MHz for ATmega162V (see Figure 113 on page 265) – 0 - 16 MHz for ATmega162 (see Figure 114 on page 265) • • 8-bit Microcontroller with 16K Bytes In-System Programmable Flash ATmega162 ATmega162V Summary • • • • • 2513IS–AVR–02/07 Note: This is a summary document. A complete document is available on our Web site at www.atmel.com. Pin Configurations Figure 1. Pinout ATmega162 PDIP (OC0/T0) PB0 (OC2/T1) PB1 (RXD1/AIN0) PB2 (TXD1/AIN1) PB3 (SS/OC3B) PB4 (MOSI) PB5 (MISO) PB6 (SCK) PB7 RESET (RXD0) PD0 (TXD0) PD1 (INT0/XCK1) PD2 (INT1/ICP3) PD3 (TOSC1/XCK0/OC3A) PD4 (OC1A/TOSC2) PD5 (WR) PD6 (RD) PD7 XTAL2 XTAL1 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC PA0 (AD0/PCINT0) PA1 (AD1/PCINT1) PA2 (AD2/PCINT2) PA3 (AD3/PCINT3) PA4 (AD4/PCINT4) PA5 (AD5/PCINT5) PA6 (AD6/PCINT6) PA7 (AD7/PCINT7) PE0 (ICP1/INT2) PE1 (ALE) PE2 (OC1B) PC7 (A15/TDI/PCINT15) PC6 (A14/TDO/PCINT14) PC5 (A13/TMS/PCINT13) PC4 (A12/TCK/PCINT12) PC3 (A11/PCINT11) PC2 (A10/PCINT10) PC1 (A9/PCINT9) PC0 (A8/PCINT8) TQFP/MLF PB4 (SS/OC3B) PB3 (TXD1/AIN1) PB2 (RXD1/AIN0) PB1 (OC2/T1) PB0 (OC0/T0) GND VCC PA0 (AD0/PCINT0) PA1 (AD1/PCINT1) PA2 (AD2/PCINT2) PA3 (AD3/PCINT3) (MOSI) PB5 (MISO) PB6 (SCK) PB7 RESET (RXD0) PD0 VCC (TXD0) PD1 (INT0/XCK1) PD2 (INT1/ICP3) PD3 (TOSC1/XCK0/OC3A) PD4 (OC1A/TOSC2) PD5 44 42 40 38 36 34 43 41 39 37 35 33 1 32 2 31 3 30 4 29 5 28 6 27 7 26 8 25 9 24 10 23 11 13 15 17 19 21 12 14 16 18 20 22 (WR) PD6 (RD) PD7 XTAL2 XTAL1 GND VCC (A8/PCINT8) PC0 (A9/PCINT9) PC1 (A10/PCINT10) PC2 (A11/PCINT11) PC3 (TCK/A12/PCINT12) PC4 PA4 (AD4/PCINT4) PA5 (AD5/PCINT5) PA6 (AD6/PCINT6) PA7 (AD7/PCINT7) PE0 (ICP1/INT2) GND PE1 (ALE) PE2 (OC1B) PC7 (A15/TDI/PCINT15) PC6 (A14/TDO/PCINT14) PC5 (A13/TMS/PCINT13) NOTE: MLF bottom pad should be soldered to ground. Disclaimer Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized. 2 ATmega162/V 2513IS–AVR–02/07 ATmega162/V Overview The ATmega162 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega162 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Figure 2. Block Diagram PA0 - PA7 VCC PE0 - PE2 PC0 - PC7 Block Diagram PORTA DRIVERS/BUFFERS PORTE DRIVERS/ BUFFERS PORTC DRIVERS/BUFFERS GND PORTA DIGITAL INTERFACE PORTE DIGITAL INTERFACE PORTC DIGITAL INTERFACE PROGRAM COUNTER STACK POINTER INTERNAL OSCILLATOR XTAL1 PROGRAM FLASH SRAM WATCHDOG TIMER OSCILLATOR XTAL2 INSTRUCTION REGISTER GENERAL PURPOSE REGISTERS X INSTRUCTION DECODER Y Z INTERRUPT UNIT MCU CTRL. & TIMING RESET INTERNAL CALIBRATED OSCILLATOR CONTROL LINES ALU TIMERS/ COUNTERS OSCILLATOR AVR CPU STATUS REGISTER EEPROM PROGRAMMING LOGIC SPI USART0 + - COMP. INTERFACE USART1 PORTB DIGITAL INTERFACE PORTD DIGITAL INTERFACE PORTB DRIVERS/BUFFERS PORTD DRIVERS/BUFFERS PB0 - PB7 PD0 - PD7 3 2513IS–AVR–02/07 The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATmega162 provides the following features: 16K bytes of In-System Programmable Flash with Read-While-Write capabilities, 512 bytes EEPROM, 1K bytes SRAM, an external memory interface, 35 general purpose I/O lines, 32 general purpose working registers, a JTAG interface for Boundary-scan, On-chip Debugging support and programming, four flexible Timer/Counters with compare modes, internal and external interrupts, two serial programmable USARTs, a programmable Watchdog Timer with Internal Oscillator, an SPI serial port, and five software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. In Power-save mode, the Asynchronous Timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low-power consumption. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run. The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, by a conventional non-volatile memory programmer, or by an On-chip Boot Program running on the AVR core. The Boot Program can use any interface to download the Application Program in the Application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega162 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega162 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, In-Circuit Emulators, and evaluation kits. ATmega161 and ATmega162 Compatibility The ATmega162 is a highly complex microcontroller where the number of I/O locations supersedes the 64 I/O locations reserved in the AVR instruction set. To ensure backward compatibility with the ATmega161, all I/O locations present in ATmega161 have the same locations in ATmega162. Some additional I/O locations are added in an Extended I/O space starting from 0x60 to 0xFF, (i.e., in the ATmega162 internal RAM space). These locations can be reached by using LD/LDS/LDD and ST/STS/STD instructions only, not by using IN and OUT instructions. The relocation of the internal RAM space may still be a problem for ATmega161 users. Also, the increased number of Interrupt Vectors might be a problem if the code uses absolute addresses. To solve these problems, an ATmega161 compatibility mode can be selected by programming the fuse M161C. In this mode, none of the functions in the Extended I/O space are in use, so the internal RAM is located as in ATmega161. Also, the Extended Interrupt Vectors are removed. The ATmega162 is 100% pin compatible with ATmega161, and can replace the ATmega161 on current Printed Circuit Boards. However, the location of Fuse bits and the electrical characteristics differs between the two devices. 4 ATmega162/V 2513IS–AVR–02/07 ATmega162/V ATmega161 Compatibility Mode Programming the M161C will change the following functionality: • • The extended I/O map will be configured as internal RAM once the M161C Fuse is programmed. The timed sequence for changing the Watchdog Time-out period is disabled. See “Timed Sequences for Changing the Configuration of the Watchdog Timer” on page 55 for details. The double buffering of the USART Receive Registers is disabled. See “AVR USART vs. AVR UART – Compatibility” on page 167 for details. Pin change interrupts are not supported (Control Registers are located in Extended I/O). One 16 bits Timer/Counter (Timer/Counter1) only. Timer/Counter3 is not accessible. • • • Note that the shared UBRRHI Register in ATmega161 is split into two separate registers in ATmega162, UBRR0H and UBRR1H. The location of these registers will not be affected by the ATmega161 compatibility fuse. Pin Descriptions VCC GND Port A (PA7..PA0) Digital supply voltage Ground Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. When pins PA0 to PA7 are used as inputs and are externally pulled low, they will source current if the internal pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various special features of the ATmega162 as listed on page 71. Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATmega162 as listed on page 71. Port C (PC7..PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the JTAG interface is enabled, the pull-up resistors on pins PC7(TDI), PC5(TMS) and PC4(TCK) will be activated even if a Reset occurs. Port C also serves the functions of the JTAG interface and other special features of the ATmega162 as listed on page 74. 5 2513IS–AVR–02/07 Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATmega162 as listed on page 77. Port E(PE2..PE0) Port E is an 3-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port E also serves the functions of various special features of the ATmega162 as listed on page 80. RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a Reset, even if the clock is not running. The minimum pulse length is given in Table 18 on page 47. Shorter pulses are not guaranteed to generate a reset. Input to the Inverting Oscillator amplifier and input to the internal clock operating circuit. Output from the Inverting Oscillator amplifier. XTAL1 XTAL2 6 ATmega162/V 2513IS–AVR–02/07 ATmega162/V Register Summary Address (0xFF) .. (0x9E) (0x9D) (0x9C) (0x9B) (0x9A) (0x99) (0x98) (0x97) (0x96) (0x95) (0x94) (0x93) (0x92) (0x91) (0x90) (0x8F) (0x8E) (0x8D) (0x8C) (0x8B) (0x8A) (0x89) (0x88) (0x87) (0x86) (0x85) (0x84) (0x83) (0x82) (0x81) (0x80) (0x7F) (0x7E) (0x7D) (0x7C) (0x7B) (0x7A) (0x79) (0x78) (0x77) (0x76) (0x75) (0x74) (0x73) (0x72) (0x71) (0x70) (0x6F) (0x6E) (0x6D) (0x6C) (0x6B) (0x6A) (0x69) (0x68) (0x67) (0x66) (0x65) (0x64) (0x63) (0x62) (0x61) Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved TCCR3A TCCR3B TCNT3H TCNT3L OCR3AH OCR3AL OCR3BH OCR3BL Reserved Reserved ICR3H ICR3L Reserved Reserved ETIMSK ETIFR Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PCMSK1 PCMSK0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved CLKPR Bit 7 – – – – – – – – – – – – – – – – – – – – – COM3A1 ICNC3 Bit 6 – – – – – – – – – – – – – – – – – – – – – COM3A0 ICES3 Bit 5 – – – – – – – – – – – – – – – – – – – – – COM3B1 – Bit 4 – – – – – – – – – – – – – – – – – – – – – COM3B0 WGM33 Bit 3 – – – – – – – – – – – – – – – – – – – – – FOC3A WGM32 Bit 2 – – – – – – – – – – – – – – – – – – – – – FOC3B CS32 Bit 1 – – – – – – – – – – – – – – – – – – – – – WGM31 CS31 Bit 0 – – – – – – – – – – – – – – – – – – – – – WGM30 CS30 Page 130 127 132 132 132 132 132 132 Timer/Counter3 – Counter Register High Byte Timer/Counter3 – Counter Register Low Byte Timer/Counter3 – Output Compare Register A High Byte Timer/Counter3 – Output Compare Register A Low Byte Timer/Counter3 – Output Compare Register B High Byte Timer/Counter3 – Output Compare Register B Low Byte – – – – – – – – – – – – – – – – Timer/Counter3 – Input Capture Register High Byte Timer/Counter3 – Input Capture Register Low Byte – – – – – – – – – – – – – – – – – – – PCINT15 PCINT7 – – – – – – – – – CLKPCE – – – – – – – – – – – – – – – – – – – PCINT14 PCINT6 – – – – – – – – – – – – TICIE3 ICF3 – – – – – – – – – – – – – – – PCINT13 PCINT5 – – – – – – – – – – – – OCIE3A OCF3A – – – – – – – – – – – – – – – PCINT12 PCINT4 – – – – – – – – – – – – OCIE3B OCF3B – – – – – – – – – – – – – – – PCINT11 PCINT3 – – – – – – – – – CLKPS3 – – TOIE3 TOV3 – – – – – – – – – – – – – – – PCINT10 PCINT2 – – – – – – – – – CLKPS2 – – – – – – – – – – – – – – – – – – – PCINT9 PCINT1 – – – – – – – – – CLKPS1 – – – – – – – – – – – – – – – – – – – PCINT8 PCINT0 – – – – – – – – – CLKPS0 133 133 134 135 87 87 39 7 2513IS–AVR–02/07 Address (0x60) 0x3F (0x5F) 0x3E (0x5E) 0x3D (0x5D) 0x3C (0x5C) (2) (2) Name Reserved SREG SPH SPL UBRR1H UCSR1C GICR GIFR TIMSK TIFR SPMCR EMCUCR MCUCR MCUCSR TCCR0 TCNT0 OCR0 SFIOR TCCR1A TCCR1B TCNT1H TCNT1L OCR1AH OCR1AL OCR1BH OCR1BL TCCR2 ASSR ICR1H ICR1L TCNT2 OCR2 WDTCR (2) Bit 7 – I SP15 SP7 URSEL1 URSEL1 INT1 INTF1 TOIE1 TOV1 SPMIE SM0 SRE JTD FOC0 Bit 6 – T SP14 SP6 UMSEL1 INT0 INTF0 OCIE1A OCF1A RWWSB SRL2 SRW10 – WGM00 Bit 5 – H SP13 SP5 UPM11 INT2 INTF2 OCIE1B OCF1B – SRL1 SE SM2 COM01 Bit 4 – S SP12 SP4 UPM10 PCIE1 PCIF1 OCIE2 OCF2 RWWSRE SRL0 SM1 JTRF COM00 Bit 3 – V SP11 SP3 USBS1 PCIE0 PCIF0 TICIE1 ICF1 BLBSET SRW01 ISC11 WDRF WGM01 Bit 2 – N SP10 SP2 Bit 1 – Z SP9 SP1 UBRR1[11:8] UCSZ10 IVSEL – TOIE0 TOV0 PGERS SRW11 ISC01 EXTRF CS01 Bit 0 – C SP8 SP0 UCPOL1 IVCE – OCIE0 OCF0 SPMEN ISC2 ISC00 PORF CS00 Page 8 11 11 189 188 60, 85 86 101, 133, 154 102, 135, 155 220 28,42,84 28,41,83 41,50,206 99 101 101 UCSZ11 – – TOIE2 TOV2 PGWRT SRW00 ISC10 BORF CS02 0x3B (0x5B) 0x3A (0x5A) 0x39 (0x59) 0x38 (0x58) 0x37 (0x57) 0x36 (0x56) 0x35 (0x55) 0x34 (0x54) 0x33 (0x53) 0x32 (0x52) 0x31 (0x51) 0x30 (0x50) 0x2F (0x4F) 0x2E (0x4E) 0x2D (0x4D) 0x2C (0x4C) 0x2B (0x4B) 0x2A (0x4A) 0x29 (0x49) 0x28 (0x48) 0x27 (0x47) 0x26 (0x46) 0x25 (0x45) 0x24 (0x44) 0x23 (0x43) 0x22 (0x42) 0x21 (0x41) 0x20 (2) Timer/Counter0 (8 Bits) Timer/Counter0 Output Compare Register TSM COM1A1 ICNC1 XMBK COM1A0 ICES1 XMM2 COM1B1 – XMM1 COM1B0 WGM13 XMM0 FOC1A WGM12 PUD FOC1B CS12 PSR2 WGM11 CS11 PSR310 WGM10 CS10 30,69,104,156 127 130 132 132 132 132 132 132 Timer/Counter1 – Counter Register High Byte Timer/Counter1 – Counter Register Low Byte Timer/Counter1 – Output Compare Register A High Byte Timer/Counter1 – Output Compare Register A Low Byte Timer/Counter1 – Output Compare Register B High Byte Timer/Counter1 – Output Compare Register B Low Byte FOC2 – WGM20 – COM21 – COM20 – WGM21 AS2 CS22 TCON2UB CS21 OCR2UB CS20 TCR2UB 148 152 133 133 151 151 Timer/Counter1 – Input Capture Register High Byte Timer/Counter1 – Input Capture Register Low Byte Timer/Counter2 (8 Bits) Timer/Counter2 Output Compare Register – URSEL0 URSEL0 – – – UMSEL0 – – – UPM01 – WDCE – UPM00 – USBS0 – – WDE WDP2 UCSZ01 WDP1 UCSZ00 – WDP0 UCPOL0 EEAR8 UBRR0[11:8] 52 189 188 18 18 19 (0x40) UBRR0H UCSR0C EEARH EEARL EEDR EECR PORTA DDRA PINA PORTB DDRB PINB PORTC DDRC PINC PORTD DDRD PIND SPDR SPSR SPCR UDR0 UCSR0A UCSR0B UBRR0L ACSR PORTE DDRE PINE OSCCAL OCDR UDR1 UCSR1A 0x1F (0x3F) 0x1E (0x3E) 0x1D (0x3D) 0x1C (0x3C) 0x1B (0x3B) 0x1A (0x3A) 0x19 (0x39) 0x18 (0x38) 0x17 (0x37) 0x16 (0x36) 0x15 (0x35) 0x14 (0x34) 0x13 (0x33) 0x12 (0x32) 0x11 (0x31) 0x10 (0x30) 0x0F (0x2F) 0x0E (0x2E) 0x0D (0x2D) 0x0C (0x2C) 0x0B (0x2B) 0x0A (0x2A) 0x09 (0x29) 0x08 (0x28) 0x07 (0x27) 0x06 (0x26) 0x05 (0x25) 0x04(1) (0x24)(1) 0x03 (0x23) 0x02 (0x22) EEPROM Address Register Low Byte EEPROM Data Register – PORTA7 DDA7 PINA7 PORTB7 DDB7 PINB7 PORTC7 DDC7 PINC7 PORTD7 DDD7 PIND7 SPIF SPIE RXC0 RXCIE0 ACD – – – – – PORTA6 DDA6 PINA6 PORTB6 DDB6 PINB6 PORTC6 DDC6 PINC6 PORTD6 DDD6 PIND6 WCOL SPE TXC0 TXCIE0 ACBG – – – CAL6 – PORTA5 DDA5 PINA5 PORTB5 DDB5 PINB5 PORTC5 DDC5 PINC5 PORTD5 DDD5 PIND5 – DORD UDRE0 UDRIE0 ACO – – – CAL5 – PORTA4 DDA4 PINA4 PORTB4 DDB4 PINB4 PORTC4 DDC4 PINC4 PORTD4 DDD4 PIND4 – MSTR FE0 RXEN0 ACI – – – CAL4 EERIE PORTA3 DDA3 PINA3 PORTB3 DDB3 PINB3 PORTC3 DDC3 PINC3 PORTD3 DDD3 PIND3 – CPOL DOR0 TXEN0 ACIE – – – CAL3 EEMWE PORTA2 DDA2 PINA2 PORTB2 DDB2 PINB2 PORTC2 DDC2 PINC2 PORTD2 DDD2 PIND2 – CPHA UPE0 UCSZ02 ACIC PORTE2 DDE2 PINE2 CAL2 EEWE PORTA1 DDA1 PINA1 PORTB1 DDB1 PINB1 PORTC1 DDC1 PINC1 PORTD1 DDD1 PIND1 – SPR1 U2X0 RXB80 ACIS1 PORTE1 DDE1 PINE1 CAL1 EERE PORTA0 DDA0 PINA0 PORTB0 DDB0 PINB0 PORTC0 DDC0 PINC0 PORTD0 DDD0 PIND0 SPI2X SPR0 MPCM0 TXB80 ACIS0 PORTE0 DDE0 PINE0 CAL0 19 81 81 81 81 81 81 81 81 82 82 82 82 163 163 161 185 185 186 189 194 82 82 82 37 201 185 SPI Data Register USART0 I/O Data Register USART0 Baud Rate Register Low Byte On-chip Debug Register USART1 I/O Data Register RXC1 TXC1 UDRE1 FE1 DOR1 UPE1 U2X1 MPCM1 185 8 ATmega162/V 2513IS–AVR–02/07 ATmega162/V Address 0x01 (0x21) 0x00 (0x20) Name UCSR1B UBRR1L Bit 7 RXCIE1 Bit 6 TXCIE1 Bit 5 UDRIE1 Bit 4 RXEN1 Bit 3 TXEN1 Bit 2 UCSZ12 Bit 1 RXB81 Bit 0 TXB81 Page 186 189 USART1 Baud Rate Register Low Byte Notes: 1. When the OCDEN Fuse is unprogrammed, the OSCCAL Register is always accessed on this address. Refer to the debugger specific documentation for details on how to use the OCDR Register. 2. Refer to the USART description for details on how to access UBRRH and UCSRC. 3. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 4. Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 9 2513IS–AVR–02/07 Instruction Set Summary Mnemonics ADD ADC ADIW SUB SUBI SBC SBCI SBIW AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER MUL MULS MULSU FMUL FMULS FMULSU RJMP IJMP JMP RCALL ICALL CALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC Rd,Rr Rd,Rr Rd,Rr Rd,K Rr, b Rr, b P, b P, b s, k s, k k k k k k k k k k k k k k k k k k k k Operands Description Operation Rd ← Rd + Rr Rd ← Rd + Rr + C Rdh:Rdl ← Rdh:Rdl + K Rd ← Rd - Rr Rd ← Rd - K Rd ← Rd - Rr - C Rd ← Rd - K - C Rdh:Rdl ← Rdh:Rdl - K Rd ← Rd • Rr Rd ← Rd • K Rd ← Rd v Rr Rd ← Rd v K Rd ← Rd ⊕ Rr Rd ← 0xFF − Rd Rd ← 0x00 − Rd Rd ← Rd v K Rd ← Rd • (0xFF - K) Rd ← Rd + 1 Rd ← Rd − 1 Rd ← Rd • Rd Rd ← Rd ⊕ Rd Rd ← 0xFF R1:R0 ← Rd x Rr R1:R0 ← Rd x Rr R1:R0 ← Rd x Rr Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS Rd, Rr Rd, Rr Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd Rd Rd,K Rd,K Rd Rd Rd Rd Rd Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr k Add two Registers Add with Carry two Registers Add Immediate to Word Subtract two Registers Subtract Constant from Register Subtract with Carry two Registers Subtract with Carry Constant from Reg. Subtract Immediate from Word Logical AND Registers Logical AND Register and Constant Logical OR Registers Logical OR Register and Constant Exclusive OR Registers One’s Complement Two’s Complement Set Bit(s) in Register Clear Bit(s) in Register Increment Decrement Test for Zero or Minus Clear Register Set Register Multiply Unsigned Multiply Signed Multiply Signed with Unsigned Fractional Multiply Unsigned Fractional Multiply Signed Fractional Multiply Signed with Unsigned Relative Jump Indirect Jump to (Z) Direct Jump Relative Subroutine Call Indirect Call to (Z) Direct Subroutine Call Subroutine Return Interrupt Return Compare, Skip if Equal Compare Compare with Carry Compare Register with Immediate Skip if Bit in Register Cleared Skip if Bit in Register is Set Skip if Bit in I/O Register Cleared Skip if Bit in I/O Register is Set Branch if Status Flag Set Branch if Status Flag Cleared Branch if Equal Branch if Not Equal Branch if Carry Set Branch if Carry Cleared Branch if Same or Higher Branch if Lower Branch if Minus Branch if Plus Branch if Greater or Equal, Signed Branch if Less Than Zero, Signed Branch if Half Carry Flag Set Branch if Half Carry Flag Cleared Branch if T Flag Set Branch if T Flag Cleared Branch if Overflow Flag is Set Branch if Overflow Flag is Cleared Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None Z,C Z,C Z,C Z,C Z,C Z,C None None None None None None None I None Z, N,V,C,H Z, N,V,C,H Z, N,V,C,H None None None None None None None None None None None None None None None None None None None None None None 1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 3 3 3 4 4 4 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1 R1:R0 ← (Rd x Rr)