ATMEGA169V_06

Features • High Performance, Low Power AVR® 8-Bit Microcontroller • Advanced RISC Architecture – 130 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 16 MIPS Throughput at 16 MHz – On-Chip 2-cycle Multiplier Non-volatile Program and Data Memories – 16K bytes of In-System Self-Programmable Flash Endurance: 10,000 Write/Erase Cycles – Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program True Read-While-Write Operation – 512 bytes EEPROM Endurance: 100,000 Write/Erase Cycles – 1K byte Internal SRAM – Programming Lock for Software Security JTAG (IEEE std. 1149.1 compliant) Interface – Boundary-scan Capabilities According to the JTAG Standard – Extensive On-chip Debug Support – Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface Peripheral Features – 4 x 25 Segment LCD Driver – Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode – One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode – Real Time Counter with Separate Oscillator – Four PWM Channels – 8-channel, 10-bit ADC – Programmable Serial USART – Master/Slave SPI Serial Interface – Universal Serial Interface with Start Condition Detector – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator – Interrupt and Wake-up on Pin Change Special Microcontroller Features – Power-on Reset and Programmable Brown-out Detection – Internal Calibrated Oscillator – External and Internal Interrupt Sources – Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and Standby I/O and Packages – 53 Programmable I/O Lines – 64-lead TQFP and 64-pad QFN/MLF Speed Grade: – ATmega169V: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 8 MHz @ 2.7 - 5.5V – ATmega169: 0 - 8 MHz @ 2.7 - 5.5V, 0 - 16 MHz @ 4.5 - 5.5V Temperature range: – -40°C to 85°C Industrial Ultra-Low Power Consumption – Active Mode: 1 MHz, 1.8V: 350µA 32 kHz, 1.8V: 20µA (including Oscillator) 32 kHz, 1.8V: 40µA (including Oscillator and LCD) – Power-down Mode: 0.1µA at 1.8V • • • 8-bit Microcontroller with 16K Bytes In-System Programmable Flash ATmega169V ATmega169 Summary • • • • • Notice: Not recommended in new designs. 2514PS–AVR–07/06 Note: This is a summary document. A complete document is available on our Web site at www.atmel.com. Pin Configurations Figure 1. Pinout ATmega169 PF5 (ADC5/TMS) PF6 (ADC6/TDO) PF4 (ADC4/TCK) PF7 (ADC7/TDI) PA0 (COM0) PA1 (COM1) 50 61 60 59 58 57 56 55 54 53 52 51 64 63 62 49 48 PA3 (COM3) 47 PA4 (SEG0) 46 PA5 (SEG1) 45 PA6 (SEG2) 44 PA7 (SEG3) 43 PG2 (SEG4) 42 PC7 (SEG5) 41 PC6 (SEG6) 40 PC5 (SEG7) 39 PC4 (SEG8) 38 PC3 (SEG9) 37 PC2 (SEG10) 36 PC1 (SEG11) 35 PC0 (SEG12) 34 33 PG1 (SEG13) PG0 (SEG14) LCDCAP (RXD/PCINT0) PE0 (TXD/PCINT1) PE1 (XCK/AIN0/PCINT2) PE2 (AIN1/PCINT3) PE3 (USCK/SCL/PCINT4) PE4 (DI/SDA/PCINT5) PE5 (DO/PCINT6) PE6 (CLKO/PCINT7) PE7 (SS/PCINT8) PB0 (SCK/PCINT9) PB1 (MOSI/PCINT10) PB2 (MISO/PCINT11) PB3 (OC0A/PCINT12) PB4 (OC1A/PCINT13) PB5 (OC1B/PCINT14) PB6 1 2 INDEX CORNER 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ATmega169 GND 22 (TOSC2) XTAL2 23 (TOSC1) XTAL1 24 (ICP1/SEG22) PD0 25 (INT0/SEG21) PD1 26 (SEG20) PD2 27 (SEG19) PD3 28 (OC2A/PCINT15) PB7 17 (T1/SEG24) PG3 18 (T0/SEG23) PG4 19 (SEG18) PD4 29 RESET 20 VCC 21 (SEG17) PD5 30 (SEG16) PD6 31 Note: The large center pad underneath the QFN/MLF packages is made of metal and internally connected to GND. It should be soldered or glued to the board to ensure good mechanical stability. If the center pad is left unconnected, the package might loosen from the board. Disclaimer Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized. 2 ATmega169/V 2514PS–AVR–07/06 (SEG15) PD7 32 PA2 (COM2) PF0 (ADC0) PF1 (ADC1) PF2 (ADC2) PF3 (ADC3) AVCC AREF GND GND VCC ATmega169/V Overview The ATmega169 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega169 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Block Diagram Figure 2. Block Diagram PF0 - PF7 PA0 - PA7 PC0 - PC7 VCC GND PORTF DRIVERS PORTA DRIVERS PORTC DRIVERS DATA REGISTER PORTF DATA DIR. REG. PORTF DATA REGISTER PORTA DATA DIR. REG. PORTA DATA REGISTER PORTC DATA DIR. REG. PORTC 8-BIT DATA BUS AVCC ADC AREF INTERNAL OSCILLATOR CALIB. OSC OSCILLATOR JTAG TAP PROGRAM COUNTER STACK POINTER WATCHDOG TIMER TIMING AND CONTROL LCD CONTROLLER/ DRIVER ON-CHIP DEBUG PROGRAM FLASH SRAM MCU CONTROL REGISTER BOUNDARYSCAN INSTRUCTION REGISTER GENERAL PURPOSE REGISTERS X Y Z TIMER/ COUNTERS PROGRAMMING LOGIC INSTRUCTION DECODER INTERRUPT UNIT RESET CONTROL LINES ALU EEPROM AVR CPU STATUS REGISTER USART UNIVERSAL SERIAL INTERFACE SPI ANALOG COMPARATOR DATA REGISTER PORTE DATA DIR. REG. PORTE DATA REGISTER PORTB DATA DIR. REG. PORTB DATA REGISTER PORTD DATA DIR. REG. PORTD DATA REG. PORTG XTAL1 XTAL2 DATA DIR. REG. PORTG + - PORTE DRIVERS PORTB DRIVERS PORTD DRIVERS PORTG DRIVERS PE0 - PE7 PB0 - PB7 PD0 - PD7 PG0 - PG4 3 2514PS–AVR–07/06 The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATmega169 provides the following features: 16K bytes of In-System Programmable Flash with Read-While-Write capabilities, 512 bytes EEPROM, 1K byte SRAM, 53 general purpose I/O lines, 32 general purpose working registers, a JTAG interface for Boundary-scan, On-chip Debugging support and programming, a complete On-chip LCD controller with internal step-up voltage, three flexible Timer/Counters with compare modes, internal and external interrupts, a serial programmable USART, Universal Serial Interface with Start Condition Detector, an 8-channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, an SPI serial port, and five software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Powerdown mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or hardware reset. In Power-save mode, the asynchronous timer and the LCD controller continues to run, allowing the user to maintain a timer base and operate the LCD display while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer, LCD controller and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low-power consumption. The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, by a conventional non-volatile memory programmer, or by an On-chip Boot program running on the AVR core. The Boot program can use any interface to download the application program in the Application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega169 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega169 AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits. 4 ATmega169/V 2514PS–AVR–07/06 ATmega169/V Pin Descriptions VCC GND Port A (PA7..PA0) Digital supply voltage. Ground. Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various special features of the ATmega169 as listed on page 62. Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B has better driving capabilities than the other ports. Port B also serves the functions of various special features of the ATmega169 as listed on page 63. Port C (PC7..PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port C also serves the functions of special features of the ATmega169 as listed on page 66. Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATmega169 as listed on page 68. Port E (PE7..PE0) Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port E also serves the functions of various special features of the ATmega169 as listed on page 70. Port F (PF7..PF0) Port F serves as the analog inputs to the A/D Converter. Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide internal pull-up resistors (selected for each bit). The Port F output 5 2514PS–AVR–07/06 buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port F pins that are externally pulled low will source current if the pull-up resistors are activated. The Port F pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a reset occurs. Port F also serves the functions of the JTAG interface. Port G (PG4..PG0) Port G is a 5-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port G output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port G pins that are externally pulled low will source current if the pull-up resistors are activated. The Port G pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port G also serves the functions of various special features of the ATmega169 as listed on page 70. RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 16 on page 38. Shorter pulses are not guaranteed to generate a reset. Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. Output from the inverting Oscillator amplifier. AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. This is the analog reference pin for the A/D Converter. An external capacitor (typical > 470 nF) must be connected to the LCDCAP pin as shown in Figure 98. This capacitor acts as a reservoir for LCD power (VLCD). A large capacitance reduces ripple on VLCD but increases the time until VLCD reaches its target value. XTAL1 XTAL2 AVCC AREF LCDCAP 6 ATmega169/V 2514PS–AVR–07/06 ATmega169/V Register Summary Address (0xFF) (0xFE) (0xFD) (0xFC) (0xFB) (0xFA) (0xF9) (0xF8) (0xF7) (0xF6) (0xF5) (0xF4) (0xF3) (0xF2) (0xF1) (0xF0) (0xEF) (0xEE) (0xED) (0xEC) (0xEB) (0xEA) (0xE9) (0xE8) (0xE7) (0xE6) (0xE5) (0xE4) (0xE3) (0xE2) (0xE1) (0xE0) (0xDF) (0xDE) (0xDD) (0xDC) (0xDB) (0xDA) (0xD9) (0xD8) (0xD7) (0xD6) (0xD5) (0xD4) (0xD3) (0xD2) (0xD1) (0xD0) (0xCF) (0xCE) (0xCD) (0xCC) (0xCB) (0xCA) (0xC9) (0xC8) (0xC7) (0xC6) (0xC5) (0xC4) (0xC3) (0xC2) (0xC1) (0xC0) Name Reserved LCDDR18 LCDDR17 LCDDR16 LCDDR15 Reserved LCDDR13 LCDDR12 LCDDR11 LCDDR10 Reserved LCDDR8 LCDDR7 LCDDR6 LCDDR5 Reserved LCDDR3 LCDDR2 LCDDR1 LCDDR0 Reserved Reserved Reserved Reserved LCDCCR LCDFRR LCDCRB LCDCRA Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved UDR UBRRH UBRRL Reserved UCSRC UCSRB UCSRA Bit 7 – – SEG323 SEG315 SEG307 – – SEG223 SEG215 SEG207 – – SEG123 SEG115 SEG107 – – SEG023 SEG015 SEG007 – – – – LCDCD2 – LCDCS LCDEN – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Bit 6 – – SEG322 SEG314 SEG306 – – SEG222 SEG214 SEG206 – – SEG122 SEG114 SEG106 – – SEG022 SEG014 SEG006 – – – – LCDCD1 LCDPS2 LCD2B LCDAB – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Bit 5 – – SEG321 SEG313 SEG305 – – SEG221 SEG213 SEG205 – – SEG121 SEG113 SEG105 – – SEG021 SEG013 SEG005 – – – – LCDCC0 LCDPS1 LCDMUX1 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Bit 4 – – SEG320 SEG312 SEG304 – – SEG220 SEG212 SEG204 – – SEG120 SEG112 SEG104 – – SEG020 SEG012 SEG004 – – – – – LCDPS0 LCDMUX0 LCDIF – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Bit 3 – – SEG319 SEG311 SEG303 – – SEG219 SEG211 SEG203 – – SEG119 SEG111 SEG103 – – SEG019 SEG011 SEG003 – – – – LCDCC3 – – LCDIE – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Bit 2 – – SEG318 SEG310 SEG302 – – SEG218 SEG210 SEG202 – – SEG118 SEG110 SEG102 – – SEG018 SEG010 SEG002 – – – – LCDCC2 LCDCD2 LCDPM2 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Bit 1 – – SEG317 SEG309 SEG301 – – SEG217 SEG209 SEG201 – – SEG117 SEG109 SEG101 – – SEG017 SEG09 SEG001 – – – – LCDCC1 LCDCD1 LCDPM1 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Bit 0 – SEG324 SEG316 SEG308 SEG300 – SEG224 SEG216 SEG208 SEG200 – SEG124 SEG116 SEG108 SEG100 – SEG024 SEG016 SEG008 SEG000 – – – – LCDCC0 LCDCD0 LCDPM0 LCDBL – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Page 224 224 224 224 224 224 224 224 224 224 224 224 224 224 224 224 222 220 219 218 USART I/O Data Register USART Baud Rate Register High USART Baud Rate Register Low – – RXCIE RXC – UMSEL TXCIE TXC – UPM1 UDRIE UDRE – UPM0 RXEN FE – USBS TXEN DOR – UCSZ1 UCSZ2 UPE – UCSZ0 RXB8 U2X – UCPOL TXB8 MPCM 169 173 173 169 169 169 7 2514PS–AVR–07/06 Address (0xBF) (0xBE) (0xBD) (0xBC) (0xBB) (0xBA) (0xB9) (0xB8) (0xB7) (0xB6) (0xB5) (0xB4) (0xB3) (0xB2) (0xB1) (0xB0) (0xAF) (0xAE) (0xAD) (0xAC) (0xAB) (0xAA) (0xA9) (0xA8) (0xA7) (0xA6) (0xA5) (0xA4) (0xA3) (0xA2) (0xA1) (0xA0) (0x9F) (0x9E) (0x9D) (0x9C) (0x9B) (0x9A) (0x99) (0x98) (0x97) (0x96) (0x95) (0x94) (0x93) (0x92) (0x91) (0x90) (0x8F) (0x8E) (0x8D) (0x8C) (0x8B) (0x8A) (0x89) (0x88) (0x87) (0x86) (0x85) (0x84) (0x83) (0x82) (0x81) (0x80) (0x7F) (0x7E) Name Reserved Reserved Reserved Reserved Reserved USIDR USISR USICR Reserved ASSR Reserved Reserved OCR2A TCNT2 Reserved TCCR2A Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved OCR1BH OCR1BL OCR1AH OCR1AL ICR1H ICR1L TCNT1H TCNT1L Reserved TCCR1C TCCR1B TCCR1A DIDR1 DIDR0 Bit 7 – – – – – USISIF USISIE – – – – Bit 6 – – – – – USIOIF USIOIE – – – Bit 5 – – – – – USIPF USIWM1 – – – – Bit 4 – – – – – USIDC USIWM0 – EXCLK – – Bit 3 – – – – – Bit 2 – – – – – USICNT2 USICS0 – TCN2UB – – Bit 1 – – – – – USICNT1 USICLK – OCR2UB – – Bit 0 – – – – – Page USI Data Register USICNT3 USICS1 – AS2 – – USICNT0 USITC – TCR2UB – – 184 185 186 138 Timer/Counter2 Output Compare Register A Timer/Counter2 (8-bit) – FOC2A – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – WGM20 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – COM2A1 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – COM2A0 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – WGM21 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – CS22 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – CS21 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – CS20 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – 137 137 135 Timer/Counter1 - Output Compare Register B High Byte Timer/Counter1 - Output Compare Register B Low Byte Timer/Counter1 - Output Compare Register A High Byte Timer/Counter1 - Output Compare Register A Low Byte Timer/Counter1 - Input Capture Register High Byte Timer/Counter1 - Input Capture Register Low Byte Timer/Counter1 - Counter Register High Byte Timer/Counter1 - Counter Register Low Byte – FOC1A ICNC1 COM1A1 – ADC7D – FOC1B ICES1 COM1A0 – ADC6D – – – COM1B1 – ADC5D – – WGM13 COM1B0 – ADC4D – – WGM12 – – ADC3D – – CS12 – – ADC2D – – CS11 WGM11 AIN1D ADC1D – – CS10 WGM10 AIN0D ADC0D 121 121 121 121 122 122 121 121 120 119 117 191 208 8 ATmega169/V 2514PS–AVR–07/06 ATmega169/V Address (0x7D) (0x7C) (0x7B) (0x7A) (0x79) (0x78) (0x77) (0x76) (0x75) (0x74) (0x73) (0x72) (0x71) (0x70) (0x6F) (0x6E) (0x6D) (0x6C) (0x6B) (0x6A) (0x69) (0x68) (0x67) (0x66) (0x65) (0x64) (0x63) (0x62) (0x61) (0x60) 0x3F (0x5F) 0x3E (0x5E) 0x3D (0x5D) 0x3C (0x5C) 0x3B (0x5B) 0x3A (0x5A) 0x39 (0x59) 0x38 (0x58) 0x37 (0x57) 0x36 (0x56) 0x35 (0x55) 0x34 (0x54) 0x33 (0x53) 0x32 (0x52) 0x31 (0x51) 0x30 (0x50) 0x2F (0x4F) 0x2E (0x4E) 0x2D (0x4D) 0x2C (0x4C) 0x2B (0x4B) 0x2A (0x4A) 0x29 (0x49) 0x28 (0x48) 0x27 (0x47) 0x26 (0x46) 0x25 (0x45) 0x24 (0x44) 0x23 (0x43) 0x22 (0x42) 0x21 (0x41) 0x20 (0x40) 0x1F (0x3F) 0x1E (0x3E) 0x1D (0x3D) 0x1C (0x3C) Name Reserved ADMUX ADCSRB ADCSRA ADCH ADCL Reserved Reserved Reserved Reserved Reserved Reserved Reserved TIMSK2 TIMSK1 TIMSK0 Reserved PCMSK1 PCMSK0 Reserved EICRA Reserved Reserved OSCCAL Reserved PRR Reserved Reserved CLKPR WDTCR SREG SPH SPL Reserved Reserved Reserved Reserved Reserved SPMCSR Reserved MCUCR MCUSR SMCR Reserved OCDR ACSR Reserved SPDR SPSR SPCR GPIOR2 GPIOR1 Reserved Reserved OCR0A TCNT0 Reserved TCCR0A GTCCR EEARH EEARL EEDR EECR GPIOR0 EIMSK EIFR Bit 7 – REFS1 – ADEN Bit 6 – REFS0 ACME ADSC Bit 5 – ADLAR – ADATE Bit 4 – MUX4 – ADIF Bit 3 – MUX3 – ADIE Bit 2 – MUX2 ADTS2 ADPS2 Bit 1 – MUX1 ADTS1 ADPS1 Bit 0 – MUX0 ADTS0 ADPS0 Page 204 189, 208 206 207 207 ADC Data Register High byte ADC Data Register Low byte – – – – – – – – – – – PCINT15 PCINT7 – – – – – – – – CLKPCE – I – SP7 – – – – – – – – – – – PCINT14 PCINT6 – – – – – – – – – – T – SP6 – – – – – – – – ICIE1 – – PCINT13 PCINT5 – – – – – – – – – – H – SP5 – – – – – – – – – – – PCINT12 PCINT4 – – – – – PRLCD – – – WDCE S – SP4 – – – – – – – – – – – PCINT11 PCINT3 – – – – – PRTIM1 – – CLKPS3 WDE V – SP3 – – – – – – – – OCIE1B – – PCINT10 PCINT2 – – – – – PRSPI – – CLKPS2 WDP2 N SP10 SP2 – – – – – – – OCIE2A OCIE1A OCIE0A – PCINT9 PCINT1 – ISC01 – – – PRUSART0 – – CLKPS1 WDP1 Z SP9 SP1 – – – – – – – TOIE2 TOIE1 TOIE0 – PCINT8 PCINT0 – ISC00 – – 140 122 92 54 54 52 Oscillator Calibration Register – PRADC – – CLKPS0 WDP0 C SP8 SP0 28 34 30 43 9 11 11 SPMIE – JTD – – – IDRD/OCD ACD – SPIF SPIE RWWSB – – – – – OCDR6 ACBG – WCOL SPE – – – – – – OCDR5 ACO – – DORD RWWSRE – PUD JTRF – – OCDR4 ACI – – MSTR BLBSET – – WDRF SM2 – OCDR3 ACIE – PGWRT – – BORF SM1 – OCDR2 ACIC – – CPHA PGERS – IVSEL EXTRF SM0 – OCDR1 ACIS1 – – SPR1 SPMEN – IVCE PORF SE – OCDR0 ACIS0 – 256 234 235 32 230 189 149 SPI Data Register – CPOL SPI2X SPR0 149 147 22 22 General Purpose I/O Register 2 General Purpose I/O Register 1 – – – – – – – – – – – – – – – – Timer/Counter0 Output Compare Register A Timer/Counter0 (8 Bit) – FOC0A TSM – – WGM00 – – – COM0A1 – – – COM0A0 – – – WGM01 – – – CS02 – – – CS01 PSR2 – – CS00 PSR10 EEAR8 92 91 89 94 18 18 18 EEPROM Address Register Low Byte EEPROM Data Register – PCIE1 PCIF1 – PCIE0 PCIF0 – – – – – – EERIE – – EEMWE – – EEWE – – EERE INT0 INTF0 General Purpose I/O Register 0 18 22 53 53 9 2514PS–AVR–07/06 Address 0x1B (0x3B) 0x1A (0x3A) 0x19 (0x39) 0x18 (0x38) 0x17 (0x37) 0x16 (0x36) 0x15 (0x35) 0x14 (0x34) 0x13 (0x33) 0x12 (0x32) 0x11 (0x31) 0x10 (0x30) 0x0F (0x2F) 0x0E (0x2E) 0x0D (0x2D) 0x0C (0x2C) 0x0B (0x2B) 0x0A (0x2A) 0x09 (0x29) 0x08 (0x28) 0x07 (0x27) 0x06 (0x26) 0x05 (0x25) 0x04 (0x24) 0x03 (0x23) 0x02 (0x22) 0x01 (0x21) 0x00 (0x20) Name Reserved Reserved Reserved Reserved TIFR2 TIFR1 TIFR0 PORTG DDRG PING PORTF DDRF PINF PORTE DDRE PINE PORTD DDRD PIND PORTC DDRC PINC PORTB DDRB PINB PORTA DDRA PINA Bit 7 – – – – – – – – – – PORTF7 DDF7 PINF7 PORTE7 DDE7 PINE7 PORTD7 DDD7 PIND7 PORTC7 DDC7 PINC7 PORTB7 DDB7 PINB7 PORTA7 DDA7 PINA7 Bit 6 – – – – – – – – – – PORTF6 DDF6 PINF6 PORTE6 DDE6 PINE6 PORTD6 DDD6 PIND6 PORTC6 DDC6 PINC6 PORTB6 DDB6 PINB6 PORTA6 DDA6 PINA6 Bit 5 – – – – – ICF1 – – – – PORTF5 DDF5 PINF5 PORTE5 DDE5 PINE5 PORTD5 DDD5 PIND5 PORTC5 DDC5 PINC5 PORTB5 DDB5 PINB5 PORTA5 DDA5 PINA5 Bit 4 – – – – – – – PORTG4 DDG4 PING4 PORTF4 DDF4 PINF4 PORTE4 DDE4 PINE4 PORTD4 DDD4 PIND4 PORTC4 DDC4 PINC4 PORTB4 DDB4 PINB4 PORTA4 DDA4 PINA4 Bit 3 – – – – – – – PORTG3 DDG3 PING3 PORTF3 DDF3 PINF3 PORTE3 DDE3 PINE3 PORTD3 DDD3 PIND3 PORTC3 DDC3 PINC3 PORTB3 DDB3 PINB3 PORTA3 DDA3 PINA3 Bit 2 – – – – – OCF1B – PORTG2 DDG2 PING2 PORTF2 DDF2 PINF2 PORTE2 DDE2 PINE2 PORTD2 DDD2 PIND2 PORTC2 DDC2 PINC2 PORTB2 DDB2 PINB2 PORTA2 DDA2 PINA2 Bit 1 – – – – OCF2A OCF1A OCF0A PORTG1 DDG1 PING1 PORTF1 DDF1 PINF1 PORTE1 DDE1 PINE1 PORTD1 DDD1 PIND1 PORTC1 DDC1 PINC1 PORTB1 DDB1 PINB1 PORTA1 DDA1 PINA1 Bit 0 – – – – TOV2 TOV1 TOV0 PORTG0 DDG0 PING0 PORTF0 DDF0 PINF0 PORTE0 DDE0 PINE0 PORTD0 DDD0 PIND0 PORTC0 DDC0 PINC0 PORTB0 DDB0 PINB0 PORTA0 DDA0 PINA0 Page 141 123 92 78 78 78 77 77 78 77 77 77 77 77 77 76 76 77 76 76 76 76 76 76 Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The ATmega169 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. 10 ATmega169/V 2514PS–AVR–07/06 ATmega169/V Instruction Set Summary Mnemonics ADD ADC ADIW SUB SUBI SBC SBCI SBIW AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER MUL MULS MULSU FMUL FMULS FMULSU RJMP IJMP JMP RCALL ICALL CALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC Rd,Rr Rd,Rr Rd,Rr Rd,K Rr, b Rr, b P, b P, b s, k s, k k k k k k k k k k k k k k k k k k k k Operands Rd, Rr Rd, Rr Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd Rd Rd,K Rd,K Rd Rd Rd Rd Rd Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr k Add two Registers Description Rd ← Rd + Rr Operation Flags Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None Z,C Z,C Z,C Z,C Z,C Z,C None None None None None None None I None Z, N,V,C,H Z, N,V,C,H Z, N,V,C,H None None None None None None None None None None None None None None None None None None None None None None #Clocks 1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 3 3 3 4 4 4 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 ARITHMETIC AND LOGIC INSTRUCTIONS Add with Carry two Registers Add Immediate to Word Subtract two Registers Subtract Constant from Register Subtract with Carry two Registers Subtract with Carry Constant from Reg. Subtract Immediate from Word Logical AND Registers Logical AND Register and Constant Logical OR Registers Logical OR Register and Constant Exclusive OR Registers One’s Complement Two’s Complement Set Bit(s) in Register Clear Bit(s) in Register Increment Decrement Test for Zero or Minus Clear Register Set Register Multiply Unsigned Multiply Signed Multiply Signed with Unsigned Fractional Multiply Unsigned Fractional Multiply Signed Fractional Multiply Signed with Unsigned Relative Jump Indirect Jump to (Z) Direct Jump Relative Subroutine Call Indirect Call to (Z) Direct Subroutine Call Subroutine Return Interrupt Return Compare, Skip if Equal Compare Compare with Carry Compare Register with Immediate Skip if Bit in Register Cleared Skip if Bit in Register is Set Skip if Bit in I/O Register Cleared Skip if Bit in I/O Register is Set Branch if Status Flag Set Branch if Status Flag Cleared Branch if Equal Branch if Not Equal Branch if Carry Set Branch if Carry Cleared Branch if Same or Higher Branch if Lower Branch if Minus Branch if Plus Branch if Greater or Equal, Signed Branch if Less Than Zero, Signed Branch if Half Carry Flag Set Branch if Half Carry Flag Cleared Branch if T Flag Set Branch if T Flag Cleared Branch if Overflow Flag is Set Branch if Overflow Flag is Cleared Rd ← Rd + Rr + C Rdh:Rdl ← Rdh:Rdl + K Rd ← Rd - Rr Rd ← Rd - K Rd ← Rd - Rr - C Rd ← Rd - K - C Rdh:Rdl ← Rdh:Rdl - K Rd ← Rd • Rr Rd ← Rd • K Rd ← Rd v Rr Rd ← Rd v K Rd ← Rd ⊕ Rr Rd ← 0xFF − Rd Rd ← 0x00 − Rd Rd ← Rd v K Rd ← Rd • (0xFF - K) Rd ← Rd + 1 Rd ← Rd − 1 Rd ← Rd • Rd Rd ← Rd ⊕ Rd Rd ← 0xFF R1:R0 ← Rd x Rr R1:R0 ← Rd x Rr R1:R0 ← Rd x Rr 1 R1:R0 ← (Rd x Rr)