ATMEGA16M1_1

Features • High Performance, Low Power AVR® 8-bit Microcontroller • Advanced RISC Architecture – 131 Powerful Instructions - Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 1 MIPS throughput per MHz – On-chip 2-cycle Multiplier Data and Non-Volatile Program Memory – 16K/32K/64K Bytes Flash of In-System Programmable Program Memory • Endurance: 10,000 Write/Erase Cycles – Optional Boot Code Section with Independent Lock Bits – In-System Programming by On-chip Boot Program • True Read-While-Write Operation – 512/1024/2048 Bytes of In-System Programmable EEPROM • Endurance: 100,000 Write/Erase Cycles Programming Lock for Flash Program and EEPROM Data Security 1024/2048/4096 Bytes Internal SRAM On Chip Debug Interface (debugWIRE) CAN 2.0A/B with 6 Message Objects - ISO 16845 Certified (1) LIN 2.1 and 1.3 Controller or 8-Bit UART One 12-bit High Speed PSC (Power Stage Controller) (only ATmega16/32/64M1) • Non Overlapping Inverted PWM Output Pins With Flexible Dead-Time • Variable PWM duty Cycle and Frequency • Synchronous Update of all PWM Registers • Auto Stop Function for Emergency Event Peripheral Features – One 8-bit General purpose Timer/Counter with Separate Prescaler, Compare Mode and Capture Mode – One 16-bit General purpose Timer/Counter with Separate Prescaler, Compare Mode and Capture Mode – One Master/Slave SPI Serial Interface – 10-bit ADC • Up To 11 Single Ended Channels and 3 Fully Differential ADC Channel Pairs • Programmable Gain (5x, 10x, 20x, 40x) on Differential Channels • Internal Reference Voltage • Direct Power Supply Voltage Measurement – 10-bit DAC for Variable Voltage Reference (Comparators, ADC) – Four Analog Comparators with Variable Threshold Detection – 100µA ±6% Current Source (LIN Node Identification) – Interrupt and Wake-up on Pin Change – Programmable Watchdog Timer with Separate On-Chip Oscillator – On-chipTemperature Sensor Special Microcontroller Features – Low Power Idle, Noise Reduction, and Power Down Modes – Power On Reset and Programmable Brown Out Detection – In-System Programmable via SPI Port – High Precision Crystal Oscillator for CAN Operations (16 MHz) See certification on Atmel® web site and note on “Baud Rate” on page 177. • • • • • • • 8-bit Microcontroller with 16K/32K/64K Bytes In-System Programmable Flash ATmega16M1 ATmega32M1 ATmega64M1 ATmega32C1 ATmega64C1 Automotive • • 1. 7647F–AVR–04/09 – Internal Calibrated RC Oscillator (8 MHz) – On-chip PLL for fast PWM (32 MHz, 64 MHz) and CPU (16 MHz) • Operating Voltage: – 2.7V - 5.5V • Extended Operating Temperature: – -40°C to +125°C • Core Speed Grade: – 0 - 8 MHz @ 2.7 - 4.5V – 0 - 16 MHz @ 4.5 - 5.5V ATmega32/64/M1/C1 Product Line-up Part Number Flash Size RAM Size EEPROM Size 8-bit Timer 16-bit Timer PSC PWM Outputs Fault Inputs (PSC) PLL 10-bit ADC Channels 10-bit DAC Analog Comparators Current Source CAN LIN/UART On-Chip Temp. Sensor SPI Interface 4 0 No 4 0 10 3 32/64 MHz 11 single 3 Differential Yes 4 Yes Yes Yes Yes Yes ATmega32C1 32 Kbyte 2048 bytes 1024 bytes ATmega64C1 64 Kbyte 4096 bytes 2048 bytes ATmega16M1 16 Kbyte 1024 bytes 512 bytes Yes Yes Yes 10 3 10 3 ATmega32M1 32 Kbyte 2048 bytes 1024 bytes ATmega64M1 64 Kbyte 4096 bytes 2048 bytes 2 ATmega16/32/64/M1/C1 7647F–AVR–04/09 ATmega16/32/64/M1/C1 1. Pin Configurations Figure 1-1. ATmega16/32/64M1 TQFP32/QFN32 (7*7 mm) Package. PB7 (ADC4/PSCOUT0B/SCK/PCINT7) PB6 (ADC7/PSCOUT1B/PCINT6) PB5 (ADC6/INT2/ACMPN1/AMP2-/PCINT5) PC7 (D2A/AMP2+/PCINT15) ATmega32/64M1 TQFP32/QFN32 PC0(PCINT8/INT3/PSCOUT1A) PD1(PCINT17/PSCIN0/CLKO) PE0 (PCINT24/RESET/OCD) 32 31 30 29 28 27 26 25 PD0 (PCINT16/PSCOUT0A) (PCINT18/PSCIN2/OC1A/MISO_A) PD2 (PCINT19/TXD/TXLIN/OC0A/SS/MOSI_A) PD3 (PCINT9/PSCIN1/OC1B/SS_A) PC1 VCC GND (PCINT10/T0/TXCAN) PC2 (PCINT11/T1/RXCAN/ICP1B) PC3 (PCINT0/MISO/PSCOUT2A) PB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 PB4 (AMP0+/PCINT4) PB3 (AMP0-/PCINT3) PC6 (ADC10/ACMP1/PCINT14) AREF(ISRC) AGND AVCC PC5 (ADC9/ACMP3/AMP1+/PCINT13) PC4 (ADC8/ACMPN3/AMP1-/PCINT12) Note: On the engineering samples (Parts marked AT90PWM324), the ACMPN3 alternate function is not located on PC4. It is located on PE2. (PCINT1/MOSI/PSCOUT2B) PB1 (PCINT25/OC0B/XTAL1) PE1 (PCINT26/ADC0/XTAL2) PE2 (PCINT20/ADC1/RXD/RXLIN/ICP1A/SCK_A) PD4 (ADC2/ACMP2/PCINT21) PD5 (ADC3/ACMPN2/INT0/PCINT22) PD6 (ACMP0/PCINT23) PD7 (ADC5/INT1/ACMPN0/PCINT2) PB2 3 7647F–AVR–04/09 Figure 1-2. ATmega32/64C1 TQFP32/QFN32 (7*7 mm) Package PB7 (ADC4/SCK/PCINT7) PB6 (ADC7PCINT6) PB5 (ADC6/INT2/ACMPN1/AMP2-/PCINT5) PC7 (D2A/AMP2+/PCINT15) ATmega32/64C1 TQFP32/QFN32 PE0 (PCINT24/RESET/OCD) PD1(PCINT17/CLKO) PC0(PCINT8/INT3) 32 31 30 29 28 27 26 25 PD0 (PCINT16) (PCINT18/OC1A/MISO_A) PD2 (PCINT19/TXD/TXLIN/OC0A/SS/MOSI_A) PD3 (PCINT9/OC1B/SS_A) PC1 VCC GND (PCINT10/T0/TXCAN) PC2 (PCINT11/T1/RXCAN/ICP1B) PC3 (PCINT0/MISO) PB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 PB4 (AMP0+/PCINT4) PB3 (AMP0-/PCINT3) PC6 (ADC10/ACMP1/PCINT14) AREF(ISRC) AGND AVCC PC5 (ADC9/ACMP3/AMP1+/PCINT13) PC4 (ADC8/ACMPN3/AMP1-/PCINT12) Note: On the first engineering samples (Parts marked AT90PWM324), the ACMPN3 alternate function is not located on PC4. It is located on PE2. 4 ATmega16/32/64/M1/C1 7647F–AVR–04/09 (PCINT1/MOSI) PB1 (PCINT25/OC0B/XTAL1) PE1 (PCINT26/ADC0/XTAL2) PE2 (PCINT20/ADC1/RXD/RXLIN/ICP1A/SCK_A) PD4 (ADC2/ACMP2/PCINT21) PD5 (ADC3/ACMPN2/INT0/PCINT22) PD6 (ACMP0/PCINT23) PD7 (ADC5/INT1/ACMPN0/PCINT2) PB2 ATmega16/32/64/M1/C1 1.1 Pin Descriptions : Table 1-1. QFN32 Pin Number 5 20 4 Pin out description Mnemonic GND AGND VCC Type Power Power Power Name, Function & Alternate Function Ground: 0V reference Analog Ground: 0V reference for analog part Power Supply Analog Power Supply: This is the power supply voltage for analog part For a normal use this pin must be connected. Analog Reference : reference for analog converter . This is the reference voltage of the A/D converter. As output, can be used by external analog ISRC (Current Source Output) MISO (SPI Master In Slave Out) 19 AVCC Power 21 AREF Power 8 PB0 I/O PSCOUT2A(1) (PSC Module 2 Output A) PCINT0 (Pin Change Interrupt 0) MOSI (SPI Master Out Slave In) 9 PB1 I/O PSCOUT2B(1) (PSC Module 2 Output B) PCINT1 (Pin Change Interrupt 1) ADC5 (Analog Input Channel 5 ) 16 PB2 I/O INT1 (External Interrupt 1 Input) ACMPN0 (Analog Comparator 0 Negative Input) PCINT2 (Pin Change Interrupt 2) 23 PB3 I/O AMP0- (Analog Differential Amplifier 0 Negative Input) PCINT3 (Pin Change Interrupt 3) AMP0+ (Analog Differential Amplifier 0 Positive Input) PCINT4 (Pin Change Interrupt 4) ADC6 (Analog Input Channel 6) INT2 (External Interrupt 2 Input) 24 PB4 I/O 26 PB5 I/O ACMPN1 (Analog Comparator 1 Negative Input) AMP2- (Analog Differential Amplifier 2 Negative Input) PCINT5 (Pin Change Interrupt 5) ADC7 (Analog Input Channel 7) 27 PB6 I/O PSCOUT1B(1) (PSC Module 1 Output A) PCINT6 (Pin Change Interrupt 6) ADC4 (Analog Input Channel 4) 28 PB7 I/O PSCOUT0B(1) (PSC Module 0 Output B) SCK (SPI Clock) PCINT7 (Pin Change Interrupt 7) PSCOUT1A(1) (PSC Module 1 Output A) 30 PC0 I/O INT3 (External Interrupt 3 Input) PCINT8 (Pin Change Interrupt 8) 5 7647F–AVR–04/09 Table 1-1. QFN32 Pin Number Pin out description (Continued) Mnemonic Type Name, Function & Alternate Function PSCIN1 (PSC Digital Input 1) 3 PC1 I/O OC1B (Timer 1 Output Compare B) SS_A (Alternate SPI Slave Select) PCINT9 (Pin Change Interrupt 9) T0 (Timer 0 clock input) 6 PC2 I/O TXCAN (CAN Transmit Output) PCINT10 (Pin Change Interrupt 10) T1 (Timer 1 clock input) 7 PC3 I/O RXCAN (CAN Receive Input) ICP1B (Timer 1 input capture alternate B input) PCINT11 (Pin Change Interrupt 11) ADC8 (Analog Input Channel 8) 17 PC4 I/O AMP1- (Analog Differential Amplifier 1 Negative Input) ACMPN3 (Analog Comparator 3 Negative Input) PCINT12 (Pin Change Interrupt 12) ADC9 (Analog Input Channel 9) 18 PC5 I/O AMP1+ (Analog Differential Amplifier 1 Positive Input) ACMP3 (Analog Comparator 3 Positive Input) PCINT13 (Pin Change Interrupt 13) ADC10 (Analog Input Channel 10) 22 PC6 I/O ACMP1 (Analog Comparator 1 Positive Input) PCINT14 (Pin Change Interrupt 14) D2A (DAC output) 25 PC7 I/O AMP2+ (Analog Differential Amplifier 2 Positive Input) PCINT15 (Pin Change Interrupt 15) 29 PD0 I/O PSCOUT0A(1) (PSC Module 0 Output A) PCINT16 (Pin Change Interrupt 16) PSCIN0 (PSC Digital Input 0) 32 PD1 I/O CLKO (System Clock Output) PCINT17 (Pin Change Interrupt 17) OC1A (Timer 1 Output Compare A) 1 PD2 I/O PSCIN2 (PSC Digital Input 2) MISO_A (Programming & alternate SPI Master In Slave Out) PCINT18 (Pin Change Interrupt 18) TXD (UART Tx data) TXLIN (LIN Transmit Output) OC0A (Timer 0 Output Compare A) SS (SPI Slave Select) MOSI_A (Programming & alternate Master Out SPI Slave In) PCINT19 (Pin Change Interrupt 19) 2 PD3 I/O 6 ATmega16/32/64/M1/C1 7647F–AVR–04/09 ATmega16/32/64/M1/C1 Table 1-1. QFN32 Pin Number Pin out description (Continued) Mnemonic Type Name, Function & Alternate Function ADC1 (Analog Input Channel 1) RXD (UART Rx data) RXLIN (LIN Receive Input) ICP1A (Timer 1 input capture alternate A input) SCK_A (Programming & alternate SPI Clock) PCINT20 (Pin Change Interrupt 20) ADC2 (Analog Input Channel 2) 12 PD4 I/O 13 PD5 I/O ACMP2 (Analog Comparator 2 Positive Input) PCINT21 (Pin Change Interrupt 21) ADC3 (Analog Input Channel 3) 14 PD6 I/O ACMPN2 (Analog Comparator 2 Negative Input) INT0 (External Interrupt 0 Input) PCINT22 (Pin Change Interrupt 22) 15 PD7 I/O ACMP0 (Analog Comparator 0 Positive Input) PCINT23 (Pin Change Interrupt 23) RESET (Reset Input) 31 PE0 I/O or I OCD (On Chip Debug I/O) PCINT24 (Pin Change Interrupt 24) XTAL1 (XTAL Input) 10 PE1 I/O OC0B (Timer 0 Output Compare B) PCINT25 (Pin Change Interrupt 25) XTAL2 (XTAL Output) 11 PE2 I/O ADC0 (Analog Input Channel 0) PCINT26 (Pin Change Interrupt 26) Note: 1. Only for ATmega32/64M1. 2. On the first engineering samples (Parts marked AT90PWM324), the ACMPN3 alternate function is not located on PC4. It is located on PE2. 7 7647F–AVR–04/09 2. Overview The ATmega16/32/64/M1/C1 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega16/32/64/M1/C1 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Figure 2-1. Block Diagram Data Bus 8-bit Flash Program Memory Program Counter Status and Control Interrupt Unit SPI Unit Instruction Register 32 x 8 General Purpose Registrers Watchdog Timer 4 Analog Comparators Indirect Addressing Instruction Decoder Direct Addressing ALU HW LIN/UART Control Lines Timer 0 Timer 1 Data SRAM ADC EEPROM DAC I/O Lines MPSC Current Source CAN The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. 8 ATmega16/32/64/M1/C1 7647F–AVR–04/09 ATmega16/32/64/M1/C1 The ATmega16/32/64/M1/C1 provides the following features: 16K/32K/64K bytes of In-System Programmable Flash with Read-While-Write capabilities, 512/1024/2048 bytes EEPROM, 1024/2048/4096 bytes SRAM, 27 general purpose I/O lines, 32 general purpose working registers, one Motor Power Stage Controller, two flexible Timer/Counters with compare modes and PWM, one UART with HW LIN, an 11-channel 10-bit ADC with two differential input stages with programmable gain, a 10-bit DAC, a programmable Watchdog Timer with Internal Individual Oscillator, an SPI serial port, an On-chip Debug system and four software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI ports, CAN, LIN/UART and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize switching noise during ADC conversions. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. The device is manufactured using Atmel’s high-density nonvolatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program can use any interface to download the application program in the application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega16/32/64/M1/C1 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega16/32/64/M1/C1 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. 2.2 Automotive Quality Grade The ATmega16/32/64/M1/C1 have been developed and manufactured according to the most stringent requirements of the international standard ISO-TS-16949. This data sheet contains limit values extracted from the results of extensive characterization (Temperature and Voltage). The quality and reliability of the ATmega16/32/64/M1/C1 have been verified during regular product qualification as per AEC-Q100 grade 1. As indicated in the ordering information paragraph, the products are available in only one temperature grade. Table 2-1. Temperature Grade Identification for Automotive Products Temperature Identifier Z Comments Full AutomotiveTemperature Range Temperature -40 ; +125 9 7647F–AVR–04/09 2.3 2.3.1 Pin Descriptions VCC Digital supply voltage. 2.3.2 GND Ground. 2.3.3 Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATmega16/32/64/M1/C1 as listed on page 69. 2.3.4 Port C (PC7..PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port C also serves the functions of special features of the ATmega16/32/64/M1/C1 as listed on page 72. 2.3.5 Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATmega16/32/64/M1/C1 as listed on page 75. 2.3.6 Port E (PE2..0) RESET/ XTAL1/ XTAL2 Port E is an 3-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the RSTDISBL Fuse is programmed, PE0 is used as an I/O pin. Note that the electrical characteristics of PE0 differ from those of the other pins of Port E. If the RSTDISBL Fuse is unprogrammed, PE0 is used as a Reset input. A low level on this pin for longer than the minimum pulse length will generate a Reset, even if the clock is not running. The minimum pulse length is given in Table 7-1 on page 47. Shorter pulses are not guaranteed to generate a Reset. 10 ATmega16/32/64/M1/C1 7647F–AVR–04/09 ATmega16/32/64/M1/C1 Depending on the clock selection fuse settings, PE1 can be used as input to the inverting Oscillator amplifier and input to the internal clock operating circuit. Depending on the clock selection fuse settings, PE2 can be used as output from the inverting Oscillator amplifier. The various special features of Port E are elaborated in “Alternate Functions of Port E” on page 78 and “Clock Systems and their Distribution” on page 29. 2.3.7 AVCC AVCC is the supply voltage pin for the A/D Converter, D/A Converter, Current source. It should be externally connected to VCC, even if the ADC, DAC are not used. If the ADC is used, it should be connected to VCC through a low-pass filter (see Section 18.6.2 “Analog Noise Canceling Techniques” on page 238). 2.3.8 AREF This is the analog reference pin for the A/D Converter. 2.4 About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details. 11 7647F–AVR–04/09 3. AVR CPU Core 3.1 Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. 3.2 Architectural Overview Figure 3-1. Block Diagram of the AVR Architecture Data Bus 8-bit Flash Program Memory Program Counter Status and Control Instruction Register 32 x 8 General Purpose Registrers Interrupt Unit SPI Unit Watchdog Timer Indirect Addressing Instruction Decoder Direct Addressing ALU Control Lines Analog Comparator I/O Module1 Data SRAM I/O Module 2 I/O Module n EEPROM I/O Lines In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable Flash memory. 12 ATmega16/32/64/M1/C1 7647F–AVR–04/09 ATmega16/32/64/M1/C1 The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation. Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction. Program Flash memory space is divided in two sections, the Boot Program section and the Application Program section. Both sections have dedicated Lock bits for write and read/write protection. The SPM (Store Program Memory) instruction that writes into the Application Flash memory section must reside in the Boot Program section. During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher is the priority. The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the ATmega16/32/64/M1/C1 has Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used. 3.3 ALU – Arithmetic Logic Unit The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description. 13 7647F–AVR–04/09 3.4 Status Register The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. The AVR Status Register – SREG – is defined as: Bit 7 I Read/Write Initial Value R/W 0 6 T R/W 0 5 H R/W 0 4 S R/W 0 3 V R/W 0 2 N R/W 0 1 Z R/W 0 0 C R/W 0 SREG • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set to enabled the interrupts. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference. • Bit 6 – T: Bit Copy Storage The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction. • Bit 5 – H: Half Carry Flag The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful in BCD arithmetic. See the “Instruction Set Description” for detailed information. • Bit 4 – S: Sign Bit, S = N ⊕ V The S-bit is always an exclusive or between the negative flag N and the Two’s Complement Overflow Flag V. See the “Instruction Set Description” for detailed information. • Bit 3 – V: Two’s Complement Overflow Flag The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction Set Description” for detailed information. • Bit 2 – N: Negative Flag The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 1 – Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. 14 ATmega16/32/64/M1/C1 7647F–AVR–04/09 ATmega16/32/64/M1/C1 • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. 3.5 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: • One 8-bit output operand and one 8-bit result input • Two 8-bit output operands and one 8-bit result input • Two 8-bit output operands and one 16-bit result input • One 16-bit output operand and one 16-bit result input Figure 3-2 shows the structure of the 32 general purpose working registers in the CPU. Figure 3-2. AVR CPU General Purpose Working Registers 7 R0 R1 R2 … R13 General Purpose Working Registers R14 R15 R16 R17 … R26 R27 R28 R29 R30 R31 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F X-register Low Byte X-register High Byte Y-register Low Byte Y-register High Byte Z-register Low Byte Z-register High Byte 0x0D 0x0E 0x0F 0x10 0x11 0 Addr. 0x00 0x01 0x02 Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions. As shown in Figure 3-2, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file. 3.5.1 The X-register, Y-register, and Z-register The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 3-3. 15 7647F–AVR–04/09 Figure 3-3. The X-, Y-, and Z-registers 15 XH 0 7 R26 (0x1A) XL 0 0 X-register 7 R27 (0x1B) 15 Y-register 7 R29 (0x1D) 15 Z-register 7 R31 (0x1F) YH 0 7 R28 (0x1C) ZH 0 7 R30 (0x1E) YL 0 0 ZL 0 0 In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 3.6 Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations to lower memory locations. This implies that a Stack PUSH command decreases the Stack Pointer. The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to point above 0x100. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when the return address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when data is popped from the Stack with return from subroutine RET or return from interrupt RETI. The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present. Bit 15 SP15 SP7 7 Read/Write R/W R/W Initial Value 0 0 14 SP14 SP6 6 R/W R/W 0 0 13 SP13 SP5 5 R/W R/W 0 0 12 SP12 SP4 4 R/W R/W 0 0 11 SP11 SP3 3 R/W R/W 0 0 10 SP10 SP2 2 R/W R/W 0 0 9 SP9 SP1 1 R/W R/W 0 0 8 SP8 SP0 0 R/W R/W 0 0 SPH SPL 16 ATmega16/32/64/M1/C1 7647F–AVR–04/09 ATmega16/32/64/M1/C1 3.7 Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. Figure 3-4 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. Figure 3-4. The Parallel Instruction Fetches and Instruction Executions T1 T2 T3 T4 clkCPU 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch Figure 3-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. Figure 3-5. Single Cycle ALU Operation T1 T2 T3 T4 clkCPU Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back 3.8 Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt. Depending on the Program Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves software security. See the section “Memory Programming” on page 296 for details. 17 7647F–AVR–04/09 The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 57. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is ANACOMP0 – the Analog Comparator 0 Interrupt. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL bit in the MCU Control Register (MCUCR). Refer to “Interrupts” on page 57 for more information. The Reset Vector can also be moved to the start of the Boot Flash section by programming the BOOTRST Fuse, see “Boot Loader Support – Read-While-Write Self-Programming ATmega16/32/64/M1/C1” on page 279. 3.8.1 Interrupt Behavior When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed. There are basically two types of interrupts. The first type is triggered by an event that sets the interrupt flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding interrupt flag. Interrupt flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the interrupt flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding interrupt flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority. The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have interrupt flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software. When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence. 18 ATmega16/32/64/M1/C1 7647F–AVR–04/09 ATmega16/32/64/M1/C1 Assembly Code Example in r16, SREG cli sbi EECR, EEMWE sbi EECR, EEWE out SREG, r16 ; restore SREG value (I-bit) ; store SREG value ; disable interrupts during timed sequence ; start EEPROM write C Code Example char cSREG; cSREG = SREG; _CLI(); EECR |= (1