ATMEGA16U4_10

Features • High Performance, Low Power AVR® 8-Bit Microcontroller • Advanced RISC Architecture – 135 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 16 MIPS Throughput at 16 MHz – On-Chip 2-cycle Multiplier Non-volatile Program and Data Memories – 16/32K Bytes of In-System Self-Programmable Flash (ATmega16U4/ATmega32U4) – 1.25/2.5K Bytes Internal SRAM (ATmega16U4/ATmega32U4) – 512Bytes/1K Bytes Internal EEPROM (ATmega16U4/ATmega32U4) – Write/Erase Cycles: 10,000 Flash/100,000 EEPROM – Data retention: 20 years at 85°C/ 100 years at 25°C(1) – Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program True Read-While-Write Operation All supplied parts are preprogramed with a default USB bootloader – Programming Lock for Software Security JTAG (IEEE std. 1149.1 compliant) Interface – Boundary-scan Capabilities According to the JTAG Standard – Extensive On-chip Debug Support – Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface USB 2.0 Full-speed/Low Speed Device Module with Interrupt on Transfer Completion – Complies fully with Universal Serial Bus Specification Rev 2.0 – Supports data transfer rates up to 12 Mbit/s and 1.5 Mbit/s – Endpoint 0 for Control Transfers: up to 64-bytes – 6 Programmable Endpoints with IN or Out Directions and with Bulk, Interrupt or Isochronous Transfers – Configurable Endpoints size up to 256 bytes in double bank mode – Fully independent 832 bytes USB DPRAM for endpoint memory allocation – Suspend/Resume Interrupts – CPU Reset possible on USB Bus Reset detection – 48 MHz from PLL for Full-speed Bus Operation – USB Bus Connection/Disconnection on Microcontroller Request – Crystal-less operation for Low Speed mode Peripheral Features – On-chip PLL for USB and High Speed Timer: 32 up to 96 MHz operation – One 8-bit Timer/Counter with Separate Prescaler and Compare Mode – Two 16-bit Timer/Counter with Separate Prescaler, Compare- and Capture Mode – One 10-bit High-Speed Timer/Counter with PLL (64 MHz) and Compare Mode – Four 8-bit PWM Channels – Four PWM Channels with Programmable Resolution from 2 to 16 Bits – Six PWM Channels for High Speed Operation, with Programmable Resolution from 2 to 11 Bits – Output Compare Modulator – 12-channels, 10-bit ADC (features Differential Channels with Programmable Gain) – Programmable Serial USART with Hardware Flow Control – Master/Slave SPI Serial Interface • • 8-bit Microcontroller with 16/32K Bytes of ISP Flash and USB Controller ATmega16U4 ATmega32U4 • Preliminary Summary • 7766ES–AVR–04/10 ATmega16U4/ATmega32U4 – Byte Oriented 2-wire Serial Interface – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator – Interrupt and Wake-up on Pin Change – On-chip Temperature Sensor Special Microcontroller Features – Power-on Reset and Programmable Brown-out Detection – Internal 8 MHz Calibrated Oscillator – Internal clock prescaler & On-the-fly Clock Switching (Int RC / Ext Osc) – External and Internal Interrupt Sources – Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and Extended Standby I/O and Packages – All I/O combine CMOS outputs and LVTTL inputs – 26 Programmable I/O Lines – 44-lead TQFP Package, 10x10mm – 44-lead QFN Package, 7x7mm Operating Voltages – 2.7 - 5.5V Operating temperature – Industrial (-40°C to +85°C) Maximum Frequency – 8 MHz at 2.7V - Industrial range – 16 MHz at 4.5V - Industrial range 1. See “Data Retention” on page 8 for details. • • • • • Note: 2 7766ES–AVR–04/10 ATmega16U4/ATmega32U4 1. Pin Configurations Figure 1-1. Pinout ATmega16U4/ATmega32U4 PF5 (ADC5/TMS) PF6 (ADC6/TDO) PF4 (ADC4/TCK) PF7 (ADC7/TDI) PF0 (ADC0) PF1 (ADC1) AVCC AREF GND GND 35 44 43 42 41 40 39 38 37 36 34 VCC (INT.6/AIN0) PE6 UVcc DD+ UGnd UCap VBus (SS/PCINT0) PB0 (PCINT1/SCLK) PB1 (PDI/PCINT2/MOSI) PB2 (PDO/PCINT3/MISO) PB3 1 2 INDEX CORNER 33 PE2 (HWB) 32 PC7 (ICP3/CLK0/OC4A) 31 PC6 (OC3A/OC4A) 30 PB6 (PCINT6/OC1B/OC4B/ADC13) 29 PB5 (PCINT5/OC1A/OC4B/ADC12) 3 4 5 6 7 8 9 10 11 12 13 VCC 14 GND 15 XTAL2 16 XTAL1 17 18 19 20 21 22 (XCK1/CTS) PD5 ATmega32U4 ATmega16U4 44-pin QFN/TQFP 28 PB4 (PCINT4/ADC11) 27 PD7 (T0/OC4D/ADC10) 26 PD6 (T1/OC4D/ADC9) 25 PD4 (ICP1/ADC8) 24 AVCC 23 GND (SDA/INT1) PD1 (OC0B/SCL/INT0) PD0 (RXD1/INT2) PD2 2. Overview The ATmega16U4/ATmega32U4 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega16U4/ATmega32U4 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. (PCINT7/OC0A/OC1C/RTS) PB7 (TXD1/INT3) PD3 RESET 3 7766ES–AVR–04/10 ATmega16U4/ATmega32U4 2.1 Block Diagram Block Diagram Figure 2-1. PF7 - PF4 PF1 PF0 PC7 PC6 VCC GND PORTF DRIVERS PORTC DRIVERS DATA REGISTER PORTF DATA DIR. REG. PORTF DATA REGISTER PORTC 8-BIT DA TA BUS DATA DIR. REG. PORTC POR - BOD RESET INTERNAL OSCILLATOR CALIB. OSC JTAG TAP PROGRAM COUNTER STACK POINTER WATCHDOG TIMER OSCILLATOR ON-CHIP DEBUG PROGRAM FLASH SRAM MCU CONTROL REGISTER TIMERS/ COUNTERS INTERRUPT UNIT TIMING AND CONTROL BOUNDARYSCAN INSTRUCTION REGISTER GENERAL PURPOSE REGISTERS X Y Z RESET XTAL1 XTAL2 UVcc ON-CHIP USB PAD 3V REGULATOR PROGRAMMING LOGIC INSTRUCTION DECODER EEPROM UCap 1uF TEMPERATURE SENSOR AVCC AGND AREF ADC CONTROL LINES ALU HIGH SPEED STATUS REGISTER TIMER/PWM PLL VBUS DP USB 2.0 DM TWO-WIRE SERIAL INTERFACE ANALOG COMPARATOR USART1 SPI DATA REGISTER PORTE DATA DIR. REG. PORTE DATA REGISTER PORTB DATA DIR. REG. PORTB DATA REGISTER PORTD DATA DIR. REG. PORTD PORTE DRIVERS PORTB DRIVERS PORTD DRIVERS PE6 PE2 PB7 - PB0 PD7 - PD0 The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATmega16U4/ATmega32U4 provides the following features: 16/32K bytes of In-System Programmable Flash with Read-While-Write capabilities, 512Bytes/1K bytes EEPROM, 1.25/2.5K bytes SRAM, 26 general purpose I/O lines (CMOS outputs and LVTTL inputs), 32 general purpose working registers, four flexible Timer/Counters with compare modes and PWM, one more high-speed Timer/Counter with compare modes and PLL adjustable source, one USART (including CTS/RTS flow control signals), a byte oriented 2-wire Serial Interface, a 12- 4 7766ES–AVR–04/10 ATmega16U4/ATmega32U4 channels 10-bit ADC with optional differential input stage with programmable gain, an on-chip calibrated temperature sensor, a programmable Watchdog Timer with Internal Oscillator, an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface, also used for accessing the On-chip Debug system and programming and six software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize switching noise during ADC conversions. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. The device is manufactured using ATMEL’s high-density nonvolatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program can use any interface to download the application program in the application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the ATMEL ATmega16U4/ATmega32U4 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega16U4/ATmega32U4 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, incircuit emulators, and evaluation kits. 2.2 2.2.1 Pin Descriptions VCC Digital supply voltage. 2.2.2 GND Ground. 2.2.3 Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B has better driving capabilities than the other ports. Port B also serves the functions of various special features of the ATmega16U4/ATmega32U4 as listed on page 72. 2.2.4 Port C (PC7,PC6) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. 5 7766ES–AVR–04/10 ATmega16U4/ATmega32U4 Only bits 6 and 7 are present on the product pinout. Port C also serves the functions of special features of the ATmega16U4/ATmega32U4 as listed on page 75. 2.2.5 Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATmega16U4/ATmega32U4 as listed on page 77. 2.2.6 Port E (PE6,PE2) Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. Only bits 2 and 6 are present on the product pinout. Port E also serves the functions of various special features of the ATmega16U4/ATmega32U4 as listed on page 80. 2.2.7 Port F (PF7..PF4, PF1,PF0) Port F serves as analog inputs to the A/D Converter. Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter channels are not used. Port pins can provide internal pull-up resistors (selected for each bit). The Port F output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port F pins that are externally pulled low will source current if the pull-up resistors are activated. The Port F pins are tri-stated when a reset condition becomes active, even if the clock is not running. Bits 2 and 3 are not present on the product pinout. Port F also serves the functions of the JTAG interface. If the JTAG interface is enabled, the pullup resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a reset occurs. 2.2.8 DUSB Full speed / Low Speed Negative Data Upstream Port. Should be connected to the USB Dconnector pin with a serial 22 Ohms resistor. 2.2.9 D+ USB Full speed / Low Speed Positive Data Upstream Port. Should be connected to the USB D+ connector pin with a serial 22 Ohms resistor. 2.2.10 UGND USB Pads Ground. 6 7766ES–AVR–04/10 ATmega16U4/ATmega32U4 2.2.11 UVCC USB Pads Internal Regulator Input supply voltage. 2.2.12 UCAP USB Pads Internal Regulator Output supply voltage. Should be connected to an external capacitor (1µF). 2.2.13 VBUS USB VBUS monitor input. 2.2.14 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 8-1 on page 50. Shorter pulses are not guaranteed to generate a reset. 2.2.15 XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. 2.2.16 XTAL2 Output from the inverting Oscillator amplifier. 2.2.17 AVCC AVCC is the supply voltage pin (input) for all the A/D Converter channels. If the ADC is not used, it should be externally connected to VCC. If the ADC is used, it should be connected to VCC through a low-pass filter. 2.2.18 AREF This is the analog reference pin (input) for the A/D Converter. 7 7766ES–AVR–04/10 ATmega16U4/ATmega32U4 3. About 3.1 Disclaimer Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized. 3.2 Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 3.3 Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details. These code examples assume that the part specific header file is included before compilation. For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instructions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR". 3.4 Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. 8 7766ES–AVR–04/10 ATmega16U4/ATmega32U4 4. Register Summary Address (0xFF) (0xFE) (0xFD) (0xFC) (0xFB) (0xFA) (0xF9) (0xF8) (0xF7) (0xF6) (0xF5) (0xF4) (0xF3) (0xF2) (0xF1) (0xF0) (0xEF) (0xEE) (0xED) (0xEC) (0xEB) (0xEA) (0xE9) (0xE8) (0xE7) (0xE6) (0xE5) (0xE4) (0xE3) (0xE2) (0xE1) (0xE0) (0xDF) (0xDE) (0xDD) (0xDC) (0xDB) (0xDA) (0xD9) (0xD8) (0xD7) (0xD6) (0xD5) (0xD4) (0xD3) (0xD2) (0xD1) (0xD0) (0xCF) (0xCE) (0xCD) (0xCC) (0xCB) (0xCA) (0xC9) (0xC8) (0xC7) (0xC6) (0xC5) (0xC4) (0xC3) (0xC2) (0xC1) (0xC0) (0xBF) Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved UEINT UEBCHX UEBCLX UEDATX UEIENX UESTA1X UESTA0X UECFG1X UECFG0X UECONX UERST UENUM UEINTX Reserved UDMFN UDFNUMH UDFNUML UDADDR UDIEN UDINT UDCON Reserved Reserved Reserved Reserved Reserved USBINT USBSTA USBCON UHWCON Reserved Reserved DT4 Reserved OCR4D OCR4C OCR4B OCR4A UDR1 UBRR1H UBRR1L Reserved UCSR1C UCSR1B UCSR1A CLKSTA CLKSEL1 CLKSEL0 TCCR4E TCCR4D TCCR4C TCCR4B TCCR4A TC4H Bit 7 - Bit 6 - Bit 5 - Bit 4 - Bit 3 EPINT6:0 BYCT7:0 DAT7:0 Bit 2 - Bit 1 BYCT10:8 Bit 0 - Page FLERRE CFGOK NAKINE OVERFI UNDERFI EPSIZE2:0 - NAKOUTE STALLRQC NAKOUTI FNCERR - RXSTPE - RXOUTE CTRLDIR STALLEDE TXINE CURRBK1:0 NBUSYBK1:0 ALLOC EPDIR EPEN DTSEQ1:0 EPBK1:0 RSTDT EPRST6:0 RXSTPI FNUM7:0 UADD6:0 RXOUTI - EPTYPE1:0 FIFOCON ADDEN UPRSME UPRSMI NAKINI - STALLRQ RWAL - EPNUM2:0 STALLEDI TXINI - FNUM10:8 EORSME EORSMI - WAKEUPE WAKEUPI - EORSTE EORSTI RSTCPU SOFE SOFI LSM MSOFE MSOFI RMWKUP SUSPE SUSPI DETACH USBE - - FRZCLK - OTGPADE - - - ID - VBUSTI VBUS VBUSTE UVREGE DT4H3 DT4H2 DT4H1 DT4H0 DT4L3 DT4L2 DT4L1 DT4L0 Timer/Counter4 - Output Compare Register D Timer/Counter4 - Output Compare Register C Timer/Counter4 - Output Compare Register B Timer/Counter4 - Output Compare Register A USART1 I/O Data Register UMSEL11 RXCIE1 RXC1 RCCKSEL3 RCSUT1 TLOCK4 FPIE4 COM4A1S PWM4X COM4A1 UMSEL10 TXCIE1 TXC1 RCCKSEL2 RCSUT0 ENHC4 FPEN4 COM4A0S PSR4 COM4A0 UPM11 UDRIE1 UDRE1 RCCKSEL1 EXSUT1 OC4OE5 FPNC4 COM4B1S DTPS41 COM4B1 UPM10 RXEN1 FE1 RCCKSEL0 EXSUT0 OC4OE4 FPES4 COM4B0S DTPS40 COM4B0 USBS1 TXEN1 DOR1 EXCKSEL3 RCE OC4OE3 FPAC4 COM4D1S CS43 FOC4A USART1 Baud Rate Register High Byte UCSZ11 UCSZ12 PE1 EXCKSEL2 EXTE OC4OE2 FPF4 COM4D0S CS42 FOC4B UCSZ10 RXB81 U2X1 RCON EXCKSEL1 OC4OE1 WGM41 FOC4D CS41 PWM4A Timer/Counter4 High Byte UCPOL1 TXB81 MPCM1 EXTON EXCKSEL0 CLKS OC4OE0 WGM40 PWM4D CS40 PWM4B USART1 Baud Rate Register Low Byte 9 7766ES–AVR–04/10 ATmega16U4/ATmega32U4 Address (0xBE) (0xBD) (0xBC) (0xBB) (0xBA) (0xB9) (0xB8) (0xB7) (0xB6) (0xB5) (0xB4) (0xB3) (0xB2) (0xB1) (0xB0) (0xAF) (0xAE) (0xAD) (0xAC) (0xAB) (0xAA) (0xA9) (0xA8) (0xA7) (0xA6) (0xA5) (0xA4) (0xA3) (0xA2) (0xA1) (0xA0) (0x9F) (0x9E) (0x9D) (0x9C) (0x9B) (0x9A) (0x99) (0x98) (0x97) (0x96) (0x95) (0x94) (0x93) (0x92) (0x91) (0x90) (0x8F) (0x8E) (0x8D) (0x8C) (0x8B) (0x8A) (0x89) (0x88) (0x87) (0x86) (0x85) (0x84) (0x83) (0x82) (0x81) (0x80) (0x7F) (0x7E) (0x7D) Name TCNT4 TWAMR TWCR TWDR TWAR TWSR TWBR Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved OCR3CH OCR3CL OCR3BH OCR3BL OCR3AH OCR3AL ICR3H ICR3L TCNT3H TCNT3L Reserved TCCR3C TCCR3B TCCR3A Reserved Reserved OCR1CH OCR1CL OCR1BH OCR1BL OCR1AH OCR1AL ICR1H ICR1L TCNT1H TCNT1L Reserved TCCR1C TCCR1B TCCR1A DIDR1 DIDR0 DIDR2 Bit 7 TWAM6 TWINT TWA6 TWS7 - Bit 6 TWAM5 TWEA TWA5 TWS6 - Bit 5 TWAM4 TWSTA TWA4 TWS5 - Bit 4 TWAM3 TWSTO TWA3 TWS4 - Bit 3 TWAM2 TWWC TWA2 TWS3 - Bit 2 TWAM1 TWEN TWA1 - Bit 1 TWAM0 TWA0 TWPS1 - Bit 0 TWIE TWGCE TWPS0 - Page Timer/Counter4 - Counter Register Low Byte 2-wire Serial Interface Data Register 2-wire Serial Interface Bit Rate Register Timer/Counter3 - Output Compare Register C High Byte Timer/Counter3 - Output Compare Register C Low Byte Timer/Counter3 - Output Compare Register B High Byte Timer/Counter3 - Output Compare Register B Low Byte Timer/Counter3 - Output Compare Register A High Byte Timer/Counter3 - Output Compare Register A Low Byte Timer/Counter3 - Input Capture Register High Byte Timer/Counter3 - Input Capture Register Low Byte Timer/Counter3 - Counter Register High Byte Timer/Counter3 - Counter Register Low Byte FOC3A ICNC3 COM3A1 ICES3 COM3A0 COM3B1 WGM33 COM3B0 WGM32 COM3C1 CS32 COM3C0 CS31 WGM31 CS30 WGM30 - Timer/Counter1 - Output Compare Register C High Byte Timer/Counter1 - Output Compare Register C Low Byte Timer/Counter1 - Output Compare Register B High Byte Timer/Counter1 - Output Compare Register B Low Byte Timer/Counter1 - Output Compare Register A High Byte Timer/Counter1 - Output Compare Register A Low Byte Timer/Counter1 - Input Capture Register High Byte Timer/Counter1 - Input Capture Register Low Byte Timer/Counter1 - Counter Register High Byte Timer/Counter1 - Counter Register Low Byte FOC1A ICNC1 COM1A1 ADC7D FOC1B ICES1 COM1A0 ADC6D FOC1C COM1B1 ADC5D ADC13D WGM13 COM1B0 ADC4D ADC12D WGM12 COM1C1 ADC11D CS12 COM1C0 ADC10D CS11 WGM11 ADC1D ADC9D CS10 WGM10 AIN0D ADC0D ADC8D 10 7766ES–AVR–04/10 ATmega16U4/ATmega32U4 Address (0x7C) (0x7B) (0x7A) (0x79) (0x78) (0x77) (0x76) (0x75) (0x74) (0x73) (0x72) (0x71) (0x70) (0x6F) (0x6E) (0x6D) (0x6C) (0x6B) (0x6A) (0x69) (0x68) (0x67) (0x66) (0x65) (0x64) (0x63) (0x62) (0x61) (0x60) 0x3F (0x5F) 0x3E (0x5E) 0x3D (0x5D) 0x3C (0x5C) 0x3B (0x5B) 0x3A (0x5A) 0x39 (0x59) 0x38 (0x58) 0x37 (0x57) 0x36 (0x56) 0x35 (0x55) 0x34 (0x54) 0x33 (0x53) 0x32 (0x52) 0x31 (0x51) 0x30 (0x50) 0x2F (0x4F) 0x2E (0x4E) 0x2D (0x4D) 0x2C (0x4C) 0x2B (0x4B) 0x2A (0x4A) 0x29 (0x49) 0x28 (0x48) 0x27 (0x47) 0x26 (0x46) 0x25 (0x45) 0x24 (0x44) 0x23 (0x43) 0x22 (0x42) 0x21 (0x41) 0x20 (0x40) 0x1F (0x3F) 0x1E (0x3E) 0x1D (0x3D) 0x1C (0x3C) Name ADMUX ADCSRB ADCSRA ADCH ADCL Reserved Reserved Reserved Reserved Reserved TIMSK4 TIMSK3 Reserved TIMSK1 TIMSK0 Reserved Reserved PCMSK0 EICRB EICRA PCICR RCCTRL OSCCAL PRR1 PRR0 Reserved Reserved CLKPR WDTCSR SREG SPH SPL Reserved RAMPZ Reserved Reserved Reserved SPMCSR Reserved MCUCR MCUSR SMCR PLLFRQ OCDR/ MONDR ACSR Reserved SPDR SPSR SPCR GPIOR2 GPIOR1 PLLCSR OCR0B OCR0A TCNT0 TCCR0B TCCR0A GTCCR EEARH EEARL EEDR EECR GPIOR0 EIMSK EIFR Bit 7 REFS1 ADHSM ADEN Bit 6 REFS0 ACME ADSC Bit 5 ADLAR MUX5 ADATE Bit 4 MUX4 ADIF Bit 3 MUX3 ADTS3 ADIE Bit 2 MUX2 ADTS2 ADPS2 Bit 1 MUX1 ADTS1 ADPS1 Bit 0 MUX0 ADTS0 ADPS0 Page ADC Data Register High byte ADC Data Register Low byte OCIE4D PCINT7 ISC31 PRUSB PRTWI CLKPCE WDIF I SP15 SP7 SPMIE JTD PINMUX OCDR7 ACD SPIF SPIE OCIE4A PCINT6 ISC30 WDIE T SP14 SP6 RWWSB PLLUSB OCDR6 ACBG WCOL SPE OCIE4B ICIE3 ICIE1 PCINT5 ISC61 ISC21 PRTIM0 WDP3 H SP13 SP5 SIGRD USBRF PLLTM1 OCDR5 ACO DORD PCINT4 ISC60 ISC20 PRTIM4 WDCE S SP12 SP4 RWWSRE PUD JTRF PLLTM0 OCDR4 ACI MSTR OCIE3C OCIE1C PCINT3 ISC11 PRTIM3 PRTIM1 CLKPS3 WDE V SP11 SP3 BLBSET WDRF SM2 PDIV3 OCDR3 ACIE SPI Data Register CPOL CPHA SPR1 SPI2X SPR0 TOIE4 OCIE3B OCIE1B OCIE0B PCINT2 ISC10 PRSPI CLKPS2 WDP2 N SP10 SP2 PGWRT BORF SM1 PDIV2 OCDR2 ACIC OCIE3A OCIE1A OCIE0A PCINT1 ISC01 CLKPS1 WDP1 Z SP9 SP1 RAMPZ1 PGERS IVSEL EXTRF SM0 PDIV1 OCDR1 ACIS1 TOIE3 TOIE1 TOIE0 PCINT0 ISC00 PCIE0 RCFREQ PRUSART1 PRADC CLKPS0 WDP0 C SP8 SP0 RAMPZ0 SPMEN IVCE PORF SE PDIV0 OCDR0 ACIS0 - RC Oscillator Calibration Register Monitor Data Register General Purpose I/O Register 2 General Purpose I/O Register 1 PINDIV PLLE PLOCK Timer/Counter0 Output Compare Register B Timer/Counter0 Output Compare Register A Timer/Counter0 (8 Bit) FOC0A COM0A1 TSM FOC0B COM0A0 COM0B1 COM0B0 EEPROM Data Register INT6 INTF6 EEPM1 EEPM0 EERIE INT3 INTF3 EEMPE INT2 INTF2 EEPE INT1 INTF1 EERE INT0 INTF0 General Purpose I/O Register 0 WGM02 CS02 CS01 WGM01 PSRASY CS00 WGM00 PSRSYNC EEPROM Address Register High Byte EEPROM Address Register Low Byte 11 7766ES–AVR–04/10 ATmega16U4/ATmega32U4 Address 0x1B (0x3B) 0x1A (0x3A) 0x19 (0x39) 0x18 (0x38) 0x17 (0x37) 0x16 (0x36) 0x15 (0x35) 0x14 (0x34) 0x13 (0x33) 0x12 (0x32) 0x11 (0x31) 0x10 (0x30) 0x0F (0x2F) 0x0E (0x2E) 0x0D (0x2D) 0x0C (0x2C) 0x0B (0x2B) 0x0A (0x2A) 0x09 (0x29) 0x08 (0x28) 0x07 (0x27) 0x06 (0x26) 0x05 (0x25) 0x04 (0x24) 0x03 (0x23) 0x02 (0x22) 0x01 (0x21) 0x00 (0x20) Name PCIFR Reserved TIFR4 TIFR3 Reserved TIFR1 TIFR0 Reserved Reserved Reserved PORTF DDRF PINF PORTE DDRE PINE PORTD DDRD PIND PORTC DDRC PINC PORTB DDRB PINB Reserved Reserved Reserved Bit 7 OCF4D PORTF7 DDF7 PINF7 PORTD7 DDD7 PIND7 PORTC7 DDC7 PINC7 PORTB7 DDB7 PINB7 - Bit 6 OCF4A PORTF6 DDF6 PINF6 PORTE6 DDE6 PINE6 PORTD6 DDD6 PIND6 PORTC6 DDC6 PINC6 PORTB6 DDB6 PINB6 - Bit 5 OCF4B ICF3 ICF1 PORTF5 DDF5 PINF5 PORTD5 DDD5 PIND5 PORTB5 DDB5 PINB5 - Bit 4 PORTF4 DDF4 PINF4 PORTD4 DDD4 PIND4 PORTB4 DDB4 PINB4 - Bit 3 OCF3C OCF1C PORTD3 DDD3 PIND3 PORTB3 DDB3 PINB3 - Bit 2 TOV4 OCF3B OCF1B OCF0B PORTE2 DDE2 PINE2 PORTD2 DDD2 PIND2 PORTB2 DDB2 PINB2 - Bit 1 OCF3A OCF1A OCF0A PORTF1 DDF1 PINF1 PORTD1 DDD1 PIND1 PORTB1 DDB1 PINB1 - Bit 0 PCIF0 TOV3 TOV1 TOV0 PORTF0 DDF0 PINF0 PORTD0 DDD0 PIND0 PORTB0 DDB0 PINB0 - Page Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 4. When using the I/O specific commands IN and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O registers as data space using LD and ST instructions, $20 must be added to these addresses. The ATmega16U4/ATmega32U4 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from $60 - $1FF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. 12 7766ES–AVR–04/10 ATmega16U4/ATmega32U4 5. Instruction Set Summary Mnemonics ADD ADC ADIW SUB SUBI SBC SBCI SBIW AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER MUL MULS MULSU FMUL FMULS FMULSU RJMP IJMP EIJMP JMP RCALL ICALL EICALL CALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS Rd,Rr Rd,Rr Rd,Rr Rd,K Rr, b Rr, b P, b P, b s, k s, k k k k k k k k k k k k k k k k k k k Operands Rd, Rr Rd, Rr Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd Rd Rd,K Rd,K Rd Rd Rd Rd Rd Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr k Description Add two Registers Add with Carry two Registers Add Immediate to Word Subtract two Registers Subtract Constant from Register Subtract with Carry two Registers Subtract with Carry Constant from Reg. Subtract Immediate from Word Logical AND Registers Logical AND Register and Constant Logical OR Registers Logical OR Register and Constant Exclusive OR Registers One’s Complement Two’s Complement Set Bit(s) in Register Clear Bit(s) in Register Increment Decrement Test for Zero or Minus Clear Register Set Register Multiply Unsigned Multiply Signed Multiply Signed with Unsigned Fractional Multiply Unsigned Fractional Multiply Signed Fractional Multiply Signed with Unsigned BRANCH INSTRUCTIONS Relative Jump Indirect Jump to (Z) Extended Indirect Jump to (Z) Direct Jump Relative Subroutine Call Indirect Call to (Z) Extended Indirect Call to (Z) Direct Subroutine Call Subroutine Return Interrupt Return Compare, Skip if Equal Compare Compare with Carry Compare Register with Immediate Skip if Bit in Register Cleared Skip if Bit in Register is Set Skip if Bit in I/O Register Cleared Skip if Bit in I/O Register is Set Branch if Status Flag Set Branch if Status Flag Cleared Branch if Equal Branch if Not Equal Branch if Carry Set Branch if Carry Cleared Branch if Same or Higher Branch if Lower Branch if Minus Branch if Plus Branch if Greater or Equal, Signed Branch if Less Than Zero, Signed Branch if Half Carry Flag Set Branch if Half Carry Flag Cleared Branch if T Flag Set Branch if T Flag Cleared Branch if Overflow Flag is Set Operation Rd ← Rd + Rr Rd ← Rd + Rr + C Rdh:Rdl ← Rdh:Rdl + K Rd ← Rd - Rr Rd ← Rd - K Rd ← Rd - Rr - C Rd ← Rd - K - C Rdh:Rdl ← Rdh:Rdl - K Rd ← Rd • Rr Rd ← Rd • K Rd ← Rd v Rr Rd ← Rd v K Rd ← Rd ⊕ Rr Rd ← 0xFF − Rd Rd ← 0x00 − Rd Rd ← Rd v K Rd ← Rd • (0xFF - K) Rd ← Rd + 1 Rd ← Rd − 1 Rd ← Rd • Rd Rd ← Rd ⊕ Rd Rd ← 0xFF R1:R0 ← Rd x Rr R1:R0 ← Rd x Rr R1:R0 ← Rd x Rr R1:R0 ← (Rd x Rr)