ATMEGA325P-20MU

Features • High Performance, Low Power AVR® 8-bit Microcontroller • Advanced RISC Architecture – 131 Powerful Instructions - Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 4 MIPS Throughput at 4 MHz High Endurance Non-volatile Memorie segments – 8K/16K Bytes of In-System Self-Programmable Flash Program Memory(ATmega8HVA/16HVA) – 256 Bytes EEPROM – 512 Bytes Internal SRAM – Write/Erase cycles: 10,000 Flash/100,000 EEPROM – Data Retention: 20 years at 85°C /100 years at 25°C(1) – Programming Lock for Software Security Battery Management Features – One or Two Cells in Series – Over-current Protection (Charge and Discharge) – Short-circuit Protection (Discharge) – High Voltage Outputs to Drive N-Channel Charge/Discharge FETs Peripheral Features – Two configurable 8- or 16-bit Timers with Separate Prescaler, Optional Input Capture (IC), Compare Mode and CTC – SPI - Serial Programmable Interface – 12-bit Voltage ADC, Four External and One Internal ADC Inputs – High Resolution Coulomb Counter ADC for Current Measurements – Programmable Watchdog Timer Special Microcontroller Features – debugWIRE On-chip Debug System – In-System Programmable via SPI ports – Power-on Reset – On-chip Voltage Regulator with Short-circuit Monitoring Interface – External and Internal Interrupt Sources – Sleep Modes: Idle, ADC Noise Reduction, Power-save, and Power-off Additional Secure Authentication Features available only under NDA Packages – 36-pad LGA – 28-lead TSOP Operating Voltage: 1.8 - 9V Maximum Withstand Voltage (High-voltage pins): 28V Temperature Range: - 20°C to 85°C Speed Grade: 1-4 MHz • • 8-bit Microcontroller with 8K/16K Bytes In-System Programmable Flash ATmega8HVA ATmega16HVA Preliminary Summary • • • • • • • • 8024AS–AVR–04/08 1. Pin Configurations 1.1 LGA Figure 1-1. LGA - Pinout ATmega8HVA/16HVA 1 A B C D E 2 3 4 5 6 7 8 Figure 1-2. 1 A B C D E DNC CF2P VREF PI DNC LGA - pinout ATmega8HVA/16HVA 2 PV2 CF2N VREFGND NI DNC 3 PV1 VFET VREG GND PA1 4 NV CF1P CF1N GND PA0 5 GND GND VCC GND PB1 6 OC PC0 GND PB2 PB0 7 OD DNC GND PB3 RESET 8 DNC GND BATT GND DNC 2 ATmega8HVA/16HVA 8024AS–AVR–04/08 ATmega8HVA/16HVA 1.2 TSOP Figure 1-3. TSOP - pinout ATmega8HVA/16HVA PV2 PV1 NV GND VFET CF1P CF1N CF2P CF2N VREG VREF VREFGND PI NI 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 OD OC GND BATT PC0 (RXD/TXD/INT0) VCC GND PB3 (MISO/INT2) PB2 (MOSI/INT1) PB1 (SCK) PB0 (SS/CKOUT) PA2 (RESET/dW) PA1 (ADC1/SGND/T1) PA0 (ADC0/SGND/T0) 1.3 1.3.1 Pin Descriptions VFET Input to the internal voltage regulator. 1.3.2 VCC Digital supply voltage. Normally connected to VREG. 1.3.3 VREG Output from the internal voltage regulator. 1.3.4 CF1P/CF1N/CF2P/CF2N CF1P/CF1N/CF2P/CF2N are the connection pins for connecting external fly capacitors to the step-up regulator. 1.3.5 VREF Internal Voltage Reference for external decoupling. 1.3.6 VREFGND Ground for decoupling of Internal Voltage Reference. Do not connect to GND or SGND on PCB. 3 8024AS–AVR–04/08 1.3.7 GND Ground 1.3.8 Port A (PA1..PA0) Port A serves as a low-voltage 2-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various special features of the ATmega8HVA/16HVA as listed in ”Alternate Functions of Port A” on page 70. 1.3.9 Port B (PB3..PB0) Port B is a low-voltage 4-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATmega8HVA/16HVA as listed in ”Alternate Functions of Port B” on page 71. 1.3.10 PC0 Port C serves the functions of various special features of the ATmega8HVA/16HVA as listed in ”Alternate Functions of Port C” on page 61. 1.3.11 OC High voltage output to drive Charge FET. 1.3.12 OD High voltage output to drive Discharge FET. 1.3.13 NI NI is the filtered negative input from the current sense resistor. 1.3.14 PI PI is the filtered positive input from the current sense resistor. 1.3.15 NV/PV1/PV2 NV, PV1, and PV2 are the inputs for battery cells 1 and 2. 1.3.16 BATT Input for detecting when a charger is connected. 1.3.17 RESET/dw Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 11 on page 38. Shorter pulses are not guaranteed to generate a reset. This pin is also used as debugWIRE communication pin. 4 ATmega8HVA/16HVA 8024AS–AVR–04/08 ATmega8HVA/16HVA 2. Overview The ATmega8HVA/16HVA is a monitoring and protection circuit for 1-cell and 2-cell Li-ion applications with focus on high security/authentication, accurate monitoring, low cost and high utilization of the cell energy. The device contains secure authentication features as well as autonomous battery protection during charging and discharging. The chip allows very accurate accumulated current measurements using an 18-bit ADC with a resolution of 0.84 µV. The feature set makes the ATmega8HVA/16HVA a key component in any system focusing on high security, battery protection, accurate monitoring, high system utilization and low cost. Figure 2-1. Block Diagram PB3..0 PC0 PB0 Oscillator Circuits / Clock Generation Oscillator Sampling Interface Program Logic Flash RESET/dW Power Supervision POR & RESET debugWIRE PORTB (4) PORTC (1) FET Control OC OD Watchdog Oscillator VCC Watchdog Timer SPI 8/16-bit T/C0 Battery Protection PV2 PV1 NV SRAM 8/16-bit T/C1 Voltage ADC VPTAT CPU EEPROM Voltage Reference VREF VREFGND PI NI GND BATT Charger Detect Security Module DATA BUS Coulumb Counter ADC VFET VREG Voltage Regulator Voltage Regulator Monitor Interface PORTA (2) PA1..0 CF1N CF1P CF2P CF2N PA1..0 A combined step-up and linear voltage regulator ensures that the chip can operate with supply voltages as low as 1.8V for 1-cell applications. The regulator automatically switches to linear mode when the input voltage is sufficiently high, thereby ensuring a minimum power consumption at all times. For 2-cell applications, only linear regulation is enabled. The regulator capabilities, combined with an extremely low power consumption in the power saving modes, greatly enhances the cell energy utilization compared to existing solutions. The chip utilizes Atmel's patented Deep Under-voltage Recovery (DUVR) mode that supports pre-charging of deeply discharged battery cells without using a separate Pre-charge FET. 5 8024AS–AVR–04/08 The ATmega8HVA/16HVA contains a 12-bit ADC that can be used to measure the voltage of each cell individually. The ADC can also be used to monitor temperature, either on-chip temperature using the built-in temperature sensor, external temperature using thermistors connected to dedicated ADC inputs. The ATmega8HVA/16HVA contains a high-voltage tolerant, open-drain IO pin that supports serial communication. Programming can be done in-system using the 4 General Purpose IO ports that support SPI programming. The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The MCU includes 8K/16K bytes of In-System Programmable Flash with Read-While-Write capabilities, 256 bytes EEPROM, 512 bytes SRAM, 32 general purpose working registers, 6 general purpose I/O lines, debugWIRE for On-chip debugging and SPI for In-system Programming, two flexible Timer/Counters with Input Capture and compare modes, internal and external interrupts, a 12-bit Sigma Delta ADC for voltage and temperature measurements, a high resolution Sigma Delta ADC for Coulomb Counting and instantaneous current measurements, Additional Secure Authentication Features, an authonomous Battery Protection module, a programmable Watchdog Timer with wake-up capabilities, and software selectable power saving modes. The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two indepdent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The device is manufactured using Atmel’s high voltage high density non-volatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed In-System, through an SPI serial interface, by a conventional non-volatile memory programmer or by an Onchip Boot program running on the AVR core. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash, fuel gauging ADCs, dedicated battery protection circuitry, and a voltage regulator on a monolithic chip, the ATmega8HVA/16HVA is a powerful microcontroller that provides a highly flexible and cost effective solution for Li-ion Smart Battery applications. The ATmega8HVA/16HVA AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, and Onchip Debugger. The ATmega8HVA/16HVA is a low-power CMOS 8-bit microcontroller based on the AVR architecture. It is part of the AVR Smart Battery family that provides secure authentication, highly accurate monitoring and autonomous protection for Lithium-ion battery cells. 6 ATmega8HVA/16HVA 8024AS–AVR–04/08 ATmega8HVA/16HVA 2.1 Comparison Between ATmega8HVA and ATmega16HVA The ATmega8HVA and ATmega16HVA differ only in memory size and interrupt vector size. Table 2-1 summarizes the different configuration for the two devices. Table 2-1. Configuration summary Device ATmega8HVA ATmega16HVA Flash 8K 16K Interrupt vector size 1 Word 2 Word 3. Disclaimer All Min, Typ and Max values contained in this datasheet are preliminary estimates based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Final values will be available after the device is characterized. 4. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. Note: 1. 5. Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. 7 8024AS–AVR–04/08 6. Register Summary Address (0xFF) (0xFE) (0xFD) (0xFC) (0xFB) (0xFA) (0xF9) (0xF8) (0xF7) (0xF6) (0xF5) (0xF4) (0xF3) (0xF2) (0xF1) (0xF0) (0xEF) (0xEE) (0xED) (0xEC) (0xEB) (0xEA) (0xE9) (0xE8) (0xE7) (0xE6) (0xE5) (0xE4) (0xE3) (0xE2) (0xE1) (0xE0) (0xDF) (0xDE) (0xDD) (0xDC) (0xDB) (0xDA) (0xD9) (0xD8) (0xD7) (0xD6) (0xD5) (0xD4) (0xD3) (0xD2) (0xD1) (0xD0) (0xCF) (0xCE) (0xCD) (0xCC) (0xCB) (0xCA) (0xC9) (0xC8) (0xC7) (0xC6) (0xC5) (0xC4) (0xC3) (0xC2) (0xC1) (0xC0) Name Reserved BPPLR BPCR BPHCTR BPOCTR BPSCTR BPCHCD BPDHCD BPCOCD BPDOCD BPSCD Reserved BPIFR BPIMSK Reserved FCSR Reserved Reserved Reserved Reserved Reserved Reserved CADICH CADICL Reserved CADRC CADCSRB CADCSRA CADAC3 CADAC2 CADAC1 CADAC0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved BGCRR BGCCR Reserved Reserved Reserved Reserved Reserved Reserved Reserved ROCR Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Bit 7 – – – – – – Bit 6 – – – – – Bit 5 – – – Bit 4 – – SCD Bit 3 – – DOCD Bit 2 – – COCD HCPT[5:0] OCPT[5:0] Bit 1 – BPPLE DHCD Bit 0 – BPPL CHCD Page 127 127 130 129 128 132 132 131 131 131 SCPT[6:0] CHCDL[7:0] DHCDL[7:0] COCDL[7:0] DOCDL[7:0] SCDL[7:0] – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – SCIF SCIE – – – – – – – – CADIC[15:8] CADIC[7:0] – DOCIF DOCIE – DUVRD – – – – – – – COCIF COCIE – CPS – – – – – – – DHCIF DHCIE – DFE – – – – – – – CHCIF CHCIE – CFE – – – – – – 110 110 138 134 133 – – CADEN – CADACIE CADPOL – – CADUB – CADRC[7:0] CADICIE CADAS[1:0] – – – CADACIF – CADRCIF – 111 CADICIF CADSE 109 107 110 110 110 110 CADSI[1:0] CADAC[31:24] CADAC[23:16] CADAC[15:8] CADAC[7:0] – – – – – – – – – – – – – – BGD – – – – – – – ROCS – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – BGCR[7:0] BGCC[5:0] – – – – – – – – – – – – – – – – – – – – – – – ROCWIF – – – – – – – – – – – – – – – ROCWIE – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – 119 118 123 8 ATmega8HVA/16HVA 8024AS–AVR–04/08 ATmega8HVA/16HVA Address (0xBF) (0xBE) (0xBD) (0xBC) (0xBB) (0xBA) (0xB9) (0xB8) (0xB7) (0xB6) (0xB5) (0xB4) (0xB3) (0xB2) (0xB1) (0xB0) (0xAF) (0xAE) (0xAD) (0xAC) (0xAB) (0xAA) (0xA9) (0xA8) (0xA7) (0xA6) (0xA5) (0xA4) (0xA3) (0xA2) (0xA1) (0xA0) (0x9F) (0x9E) (0x9D) (0x9C) (0x9B) (0x9A) (0x99) (0x98) (0x97) (0x96) (0x95) (0x94) (0x93) (0x92) (0x91) (0x90) (0x8F) (0x8E) (0x8D) (0x8C) (0x8B) (0x8A) (0x89) (0x88) (0x87) (0x86) (0x85) (0x84) (0x83) (0x82) (0x81) (0x80) (0x7F) (0x7E) Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved OCR1B OCR1A Reserved Reserved TCNT1H TCNT1L Reserved Reserved TCCR1B TCCR1A Reserved DIDR0 Bit 7 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Bit 6 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Bit 5 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Bit 4 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Bit 3 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Bit 2 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Bit 1 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Bit 0 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Page Timer/Counter1 – Output Compare Register B Timer/Counter1 – Output Compare Register A – – – – – – – – – – – – – – – – 92 91 Timer/Counter1 (8 Bit) High Byte Timer/Counter1 (8 Bit) Low Byte – – – TCW1 – – – – – ICEN1 – – – – – ICNC1 – – – – – ICES1 – – – – – ICS1 – – – – CS12 – – – – – CS11 – – PA1DID – – CS10 WGM10 – PA0DID 91 91 76 90 116 9 8024AS–AVR–04/08 Address (0x7D) (0x7C) (0x7B) (0x7A) (0x79) (0x78) (0x77) (0x76) (0x75) (0x74) (0x73) (0x72) (0x71) (0x70) (0x6F) (0x6E) (0x6D) (0x6C) (0x6B) (0x6A) (0x69) (0x68) (0x67) (0x66) (0x65) (0x64) (0x63) (0x62) (0x61) (0x60) 0x3F (0x5F) 0x3E (0x5E) 0x3D (0x5D) 0x3C (0x5C) 0x3B (0x5B) 0x3A (0x5A) 0x39 (0x59) 0x38 (0x58) 0x37 (0x57) 0x36 (0x56) 0x35 (0x55) 0x34 (0x54) 0x33 (0x53) 0x32 (0x52) 0x31 (0x51) 0x30 (0x50) 0x2F (0x4F) 0x2E (0x4E) 0x2D (0x4D) 0x2C (0x4C) 0x2B (0x4B) 0x2A (0x4A) 0x29 (0x49) 0x28 (0x48) 0x27 (0x47) 0x26 (0x46) 0x25 (0x45) 0x24 (0x44) 0x23 (0x43) 0x22 (0x42) 0x21 (0x41) 0x20 (0x40) 0x1F (0x3F) 0x1E (0x3E) 0x1D (0x3D) 0x1C (0x3C) Name Reserved VADMUX Reserved VADCSR VADCH VADCL Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved TIMSK1 TIMSK0 Reserved Reserved Reserved Reserved EICRA Reserved Reserved FOSCCAL Reserved PRR0 Reserved Reserved CLKPR WDTCSR SREG SPH SPL Reserved Reserved Reserved Reserved Reserved SPMCSR Reserved MCUCR MCUSR SMCR Reserved DWDR Reserved Reserved SPDR SPSR SPCR GPIOR2 GPIOR1 OCR0B OCR0A TCNT0H TCNT0L TCCR0B TCCR0A GTCCR Reserved EEAR EEDR EECR GPIOR0 EIMSK EIFR Bit 7 – – – – – – – – – – – – – – – – – – – – – – – – – – CLKPCE WDIF I SP15 SP7 – – – – – – – – – – – – – SPIF SPIE Bit 6 – – – – – – – – – – – – – – – – – – – – – – – – – – – WDIE T SP14 SP6 – – – – – – – – – – – – – WCOL SPE Bit 5 – – – – – – – – – – – – – – – – – – – ISC21 – – – PRVRM – – – WDP3 H SP13 SP5 – – – – – SIGRD – CKOE – – – – – – DORD Bit 4 – – – – – Bit 3 – – VADEN Bit 2 – Bit 1 – Bit 0 – Page 114 VADMUX[3:0] – VADSC – VADCCIF – VADCCIE 114 115 115 VADC Data Register High byte – – – – – – – – ICIE1 ICIE0 – – – – ISC11 – – – PRSPI – – – WDE V SP11 SP3 – – – – – RFLB – – WDRF – – – – CPOL – – – – – – – – OCIE1B OCIE0B – – – – ISC10 – – – PRTIM1 – – – WDP2 N SP10 SP2 – – – – – PGWRT – – BODRF SM[2:0] – – – – CPHA – – – – SPR1 – – – – – – – – OCIE1A OCIE0A – – – – ISC01 – – – PRTIM0 – – CLKPS1 WDP1 Z SP9 SP1 – – – – – PGERS – – EXTRF – – – – – – – – TOIE1 TOIE0 – – – – ISC00 – – VADC Data Register Low byte – – – – – – – – – – – – – – ISC20 – – – – – – – WDCE S SP12 SP4 – – – – – CTPB – PUD OCDRF – – – – – MSTR debugWIRE Data Register – – 92 92 56 Fast Oscillator Calibration Register – PRVADC – – CLKPS0 WDP0 C SP8 SP0 – – – – – SPMEN – – PORF SE – 30 39 31 49 9 12 12 147 73/31 49 39 140 SPI Data Register SPI2X SPR0 103 102 101 23 23 92 91 91 91 CS02 – – – CS01 – – – CS00 WGM00 PSRSYNC – 19 19 EEMPE INT2 INTF2 EEPE INT1 INTF1 EERE INT0 INTF0 19 23 57 57 76 90 General Purpose I/O Register 2 General Purpose I/O Register 1 Timer/Counter0 Output Compare Register B Timer/Counter0 Output Compare Register A Timer/Counter0 (8 Bit) High Byte Timer/Counter0 (8 Bit) Low Byte – TCW0 TSM – – ICEN0 – – – ICNC0 – – – ICES0 – – – ICS0 – – EEPROM Address Register Low Byte EEPROM Data Register – – – – – – EEPM1 – – EEPM0 – – EERIE – – General Purpose I/O Register 0 10 ATmega8HVA/16HVA 8024AS–AVR–04/08 ATmega8HVA/16HVA Address 0x1B (0x3B) 0x1A (0x3A) 0x19 (0x39) 0x18 (0x38) 0x17 (0x37) 0x16 (0x36) 0x15 (0x35) 0x14 (0x34) 0x13 (0x33) 0x12 (0x32) 0x11 (0x31) 0x10 (0x30) 0x0F (0x2F) 0x0E (0x2E) 0x0D (0x2D) 0x0C (0x2C) 0x0B (0x2B) 0x0A (0x2A) 0x09 (0x29) 0x08 (0x28) 0x07 (0x27) 0x06 (0x26) 0x05 (0x25) 0x04 (0x24) 0x03 (0x23) 0x02 (0x22) 0x01 (0x21) 0x00 (0x20) Name Reserved Reserved Reserved Reserved OSICSR TIFR1 TIFR0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PORTC Reserved PINC PORTB DDRB PINB PORTA DDRA PINA Bit 7 – – – – – – – – – – – – – – – – – – – – – – – – – – – – Bit 6 – – – – – – – – – – – – – – – – – – – – – – – – – – – – Bit 5 – – – – – – – – – – – – – – – – – – – – – – – – – – – – Bit 4 – – – – OSISEL0 – – – – – – – – – – – – – – – – – – – – – – – Bit 3 – – – – – ICF1 ICF0 – – – – – – – – – – – – – – – PORTB3 DDB3 PINB3 – – – Bit 2 – – – – – OCF1B OCF0B – – – – – – – – – – – – – – – PORTB2 DDB2 PINB2 – – – Bit 1 – – – – OSIST OCF1A OCF0A – – – – – – – – – – – – – – – PORTB1 DDB1 PINB1 PORTA1 DDA1 PINA1 Bit 0 – – – – OSIEN TOV1 TOV0 – – – – – – – – – – – – PORTC0 – PINC0 PORTB0 DDB0 PINB0 PORTA0 DDA0 PINA0 Page 32 93 93 62 62 73 73 73 73 73 73 Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 4. When using the I/O specific commands IN and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O registers as data space using LD and ST instructions, $20 must be added to these addresses. The ATmega8HVA/16HVA is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from $60 - $FF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. 11 8024AS–AVR–04/08 7. Instruction Set Summary Mnemonics ADD ADC ADIW SUB SUBI SBC SBCI SBIW AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER MUL MULS MULSU FMUL FMULS FMULSU RJMP IJMP JMP(1) RCALL ICALL CALL(1) RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC Rd,Rr Rd,Rr Rd,Rr Rd,K Rr, b Rr, b P, b P, b s, k s, k k k k k k k k k k k k k k k k k k k k Operands Rd, Rr Rd, Rr Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd Rd Rd,K Rd,K Rd Rd Rd Rd Rd Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr k Add two Registers Description Rd ← Rd + Rr Operation Flags Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None Z,C Z,C Z,C Z,C Z,C Z,C None None None None None None None I None Z, N,V,C,H Z, N,V,C,H Z, N,V,C,H None None None None None None None None None None None None None None None None None None None None None None #Clocks 1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 3 3 3 4 4 4 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 ARITHMETIC AND LOGIC INSTRUCTIONS Add with Carry two Registers Add Immediate to Word Subtract two Registers Subtract Constant from Register Subtract with Carry two Registers Subtract with Carry Constant from Reg. Subtract Immediate from Word Logical AND Registers Logical AND Register and Constant Logical OR Registers Logical OR Register and Constant Exclusive OR Registers One’s Complement Two’s Complement Set Bit(s) in Register Clear Bit(s) in Register Increment Decrement Test for Zero or Minus Clear Register Set Register Multiply Unsigned Multiply Signed Multiply Signed with Unsigned Fractional Multiply Unsigned Fractional Multiply Signed Fractional Multiply Signed with Unsigned Relative Jump Indirect Jump to (Z) Direct Jump Relative Subroutine Call Indirect Call to (Z) Direct Subroutine Call Subroutine Return Interrupt Return Compare, Skip if Equal Compare Compare with Carry Compare Register with Immediate Skip if Bit in Register Cleared Skip if Bit in Register is Set Skip if Bit in I/O Register Cleared Skip if Bit in I/O Register is Set Branch if Status Flag Set Branch if Status Flag Cleared Branch if Equal Branch if Not Equal Branch if Carry Set Branch if Carry Cleared Branch if Same or Higher Branch if Lower Branch if Minus Branch if Plus Branch if Greater or Equal, Signed Branch if Less Than Zero, Signed Branch if Half Carry Flag Set Branch if Half Carry Flag Cleared Branch if T Flag Set Branch if T Flag Cleared Branch if Overflow Flag is Set Branch if Overflow Flag is Cleared Rd ← Rd + Rr + C Rdh:Rdl ← Rdh:Rdl + K Rd ← Rd - Rr Rd ← Rd - K Rd ← Rd - Rr - C Rd ← Rd - K - C Rdh:Rdl ← Rdh:Rdl - K Rd ← Rd • Rr Rd ← Rd • K Rd ← Rd v Rr Rd ← Rd v K Rd ← Rd ⊕ Rr Rd ← 0xFF − Rd Rd ← 0x00 − Rd Rd ← Rd v K Rd ← Rd • (0xFF - K) Rd ← Rd + 1 Rd ← Rd − 1 Rd ← Rd • Rd Rd ← Rd ⊕ Rd Rd ← 0xFF R1:R0 ← Rd x Rr R1:R0 ← Rd x Rr R1:R0 ← Rd x Rr 1 R1:R0 ← (Rd x Rr)