ATMEGA406

Features • High Performance, Low Power AVR® 8-bit Microcontroller • Advanced RISC Architecture – 124 Powerful Instructions - Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 1 MIPS Throughput at 1 MHz Nonvolatile Program and Data Memories – 40K Bytes of In-System Self-Programmable Flash, Endurance: 10,000 Write/Erase Cycles – Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program True Read-While-Write Operation – 512 bytes EEPROM, Endurance: 100,000 Write/Erase Cycles – 2K Bytes Internal SRAM – Programming Lock for Software Security On-chip Debugging – Extensive On-chip Debug Support – Available through JTAG interface Battery Management Features – Two, Three, or Four Cells in Series – Deep Under-voltage Protection – Over-current Protection (Charge and Discharge) – Short-circuit Protection (Discharge) – Integrated Cell Balancing FETs – High Voltage Outputs to Drive Charge/Precharge/Discharge FETs Peripheral Features – One 8-bit Timer/Counter with Separate Prescaler, Compare Mode, and PWM – One 16-bit Timer/Counter with Separate Prescaler and Compare Mode – 12-bit Voltage ADC, Eight External and Two Internal ADC Inputs – High Resolution Coulomb Counter ADC for Current Measurements – TWI Serial Interface for SM-Bus – Programmable Wake-up Timer – Programmable Watchdog Timer Special Microcontroller Features – Power-on Reset – On-chip Voltage Regulator – External and Internal Interrupt Sources – Four Sleep Modes: Idle, Power-save, Power-down, and Power-off Packages – 48-pin LQFP Operating Voltage: 4.0 - 25V Maximum Withstand Voltage (High-voltage pins): 28V Temperature Range: -30°C to 85°C – Speed Grade: 1 MHz • • 8-bit Microcontroller with 40K Bytes In-System Programmable Flash ATmega406 Preliminary Summary • • • • • • • 2548ES–AVR–07/06 1. Pin Configurations Figure 1-1. Pinout ATmega406. Top View NNI NI PI PPI VREFGND VREF NV PV1 PV2 PV3 PV4 GND 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 SGND (ADC0/PCINT0) PA0 (ADC1/PCINT1) PA1 (ADC2/PCINT2) PA2 (ADC3/PCINT3) PA3 VREG VCC GND (ADC4/INT0/PCINT4) PA4 (INT1/PCINT5) PA5 (INT2/PCINT6) PA6 (INT3/PCINT7) PA7 1 2 3 4 5 6 7 8 9 10 11 12 PVT OD VFET OC OPC BATT PC0 GND PD1 PD0 (T0) PB7 (OC0B/PCINT15) PB6 (OC0A/PCINT14) 1.1 Disclaimer Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized. 2 ATmega406 2548ES–AVR–07/06 RESET XTAL1 XTAL2 GND (TDO/PCINT8) PB0 (TDI/PCINT9) PB1 (TMS/PCINT10) PB2 (TCK/PCINT11) PB3 (PCINT12) PB4 (PCINT13) PB5 SCL SDA ATmega406 2. Overview The ATmega406 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega406 achieves throughputs approaching 1 MIPS at 1 MHz. 2.1 Block Diagram Block Diagram PD1..0 PB7..0 Figure 2-1. XTAL1 Oscillator Circuits / Clock Generation XTAL2 Watchdog Oscillator Watchdog Timer Flash RESET Power Supervision POR & RESET SRAM 16 bit T/C1 PORTD (2) PORTB (8) OPC OC OD PPI NNI PVT PV4 PV3 PV2 PV1 NV SGND FET Control Battery Protection Wake-Up Timer JTAG 8 bit T/C0 Cell Balancing VCC Voltage ADC CPU EEPROM Voltage Reference VREF VREFGND PI NI GND BATT Charger Detect Coulumb Counter ADC DATA BUS VFET VREG Voltage Regulator TWI PORTC (1) PORTA (8) PA3..0 SCL SCA PC0 PA7..0 The ATmega406 provides the following features: a Voltage Regulator, dedicated Battery Protection Circuitry, integrated cell balancing FETs, high-voltage analog front-end, and an MCU with two ADCs with On-chip voltage reference for battery fuel gauging. The voltage regulator operates at a wide range of voltages, 4.0 - 25 volts. This voltage is regulated to a constant supply voltage of nominally 3.3 volts for the integrated logic and analog functions. The battery protection monitors the battery voltage and charge/discharge current to detect illegal conditions and protect the battery from these when required. The illegal conditions are deep under-voltage during discharging, short-circuit during discharging and over-current during charging and discharging. 3 2548ES–AVR–07/06 The integrated cell balancing FETs allow cell balancing algorithms to be implemented in software. The MCU provides the following features: 40K bytes of In-System Programmable Flash with Read-While-Write capabilities, 512 bytes EEPROM, 2K byte SRAM, 32 general purpose working registers, 18 general purpose I/O lines, 11 high-voltage I/O lines, a JTAG Interface for On-chip Debugging support and programming, two flexible Timer/Counters with PWM and compare modes, one Wake-up Timer, an SM-Bus compliant TWI module, internal and external interrupts, a 12-bit Sigma Delta ADC for voltage and temperature measurements, a high resolution Sigma Delta ADC for Coulomb Counting and instantaneous current measurements, a programmable Watchdog Timer with internal Oscillator, and four software selectable power saving modes. The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The Idle mode stops the CPU while allowing the other chip function to continue functioning. The Power-down mode allows the voltage regulator, battery protection, regulator current detection, Watchdog Timer, and Wake-up Timer to operate, while disabling all other chip functions until the next Interrupt or Hardware Reset. In Power-save mode, the Wake-up Timer and Coulomb Counter ADC continues to run. The device is manufactured using Atmel’s high voltage high density non-volatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed In-System, by a conventional non-volatile memory programmer or by an On-chip Boot program running on the AVR core. The Boot program can use any interface to download the application program in the Application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash, fuel gauging ADCs, dedicated battery protection circuitry, Cell Balancing FETs, and a voltage regulator on a monolithic chip, the Atmel ATmega406 is a powerful microcontroller that provides a highly flexible and cost effective solution for Li-ion Smart Battery applications. The ATmega406 AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, and On-chip Debugger. 4 ATmega406 2548ES–AVR–07/06 ATmega406 2.2 2.2.1 Pin Descriptions VFET High voltage supply pin. This pin is used as supply for the internal voltage regulator, described in ”Voltage Regulator” on page 114. In addition the voltage level on this pin is monitored by the battery protection circuit, for deep-under-voltage protection. For details, see ”Battery Protection” on page 125. 2.2.2 VCC Digital supply voltage. Normally connected to VREG. 2.2.3 VREG Output from the internal Voltage Regulator. Used for external decoupling to ensure stable regulator operation. For details, see ”Voltage Regulator” on page 114. 2.2.4 VREF Internal Voltage Reference for external decoupling. For details, see ”Voltage Reference and Temperature Sensor” on page 121. 2.2.5 VREFGND Ground for decoupling of Internal Voltage Reference. For details, see ”Voltage Reference and Temperature Sensor” on page 121. 2.2.6 GND Ground 2.2.7 SGND Signal ground pin, used as reference for Voltage-ADC conversions. For details, see ”Voltage ADC – 10-channel General Purpose 12-bit Sigma-Delta ADC” on page 116. 2.2.8 Port A (PA7:PA0) PA3:PA0 serves as the analog inputs to the Voltage A/D Converter. Port A also serves as a low-voltage 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various special features of the ATmega406 as listed in ”Alternate Functions of Port A” on page 68. 2.2.9 Port B (PB7:PB0) Port B is a low-voltage 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATmega406 as listed in ”Alternate Functions of Port B” on page 70. 5 2548ES–AVR–07/06 2.2.10 Port C (PC0) Port C is a high voltage Open Drain output port. 2.2.11 Port D (PD1:PD0) Port D is a low-voltage 2-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATmega406 as listed in ”Alternate Functions of Port D” on page 72. 2.2.12 SCL SMBUS clock, Open Drain bidirectional pin. 2.2.13 SDA SMBUS data, Open Drain bidirectional pin. 2.2.14 OC/OD/OPC High voltage output to drive external Charge/Discharge/Pre-charge FETs. For details, see ”FET Control” on page 133. 2.2.15 PI/NI Unfiltered positive/negative input from external current sense resistor, used by the battery protection circuit, for over-current and short-circuit detection. For details, see ”Battery Protection” on page 125. 2.2.16 PPI/NNI Filtered positive/negative input from external current sense resistor, used to by the Coulomb Counter ADC to measure charge/discharge currents flowing in the battery pack. For details, see ”Coulomb Counter - Dedicated Fuel Gauging Sigma-delta ADC” on page 106. 2.2.17 NV/PV1/PV2/PV3/PV4 NV, PV1, PV2, PV3, and PV4 are the inputs for battery cells 1, 2, 3 and 4, used by the Voltage ADC to measure each cell voltage. For details, see ”Voltage ADC – 10-channel General Purpose 12-bit Sigma-Delta ADC” on page 116. PVT PVT defines the pull-up level for the OD output. 2.2.18 2.2.19 BATT Input for detecting when a charger is connected. This pin also defines the pull-up level for OC and OPC outputs. 2.2.20 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 11 on page 38. Shorter pulses are not guaranteed to generate a reset. 6 ATmega406 2548ES–AVR–07/06 ATmega406 2.2.21 XTAL1 Input to the inverting Oscillator amplifier. 2.2.22 XTAL2 Output from the inverting Oscillator amplifier. 3. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 7 2548ES–AVR–07/06 4. Register Summary Address (0xFF) (0xFE) (0xFD) (0xFC) (0xFB) (0xFA) (0xF9) (0xF8) (0xF7) (0xF6) (0xF5) (0xF4) (0xF3) (0xF2) (0xF1) (0xF0) (0xEF) (0xEE) (0xED) (0xEC) (0xEB) (0xEA) (0xE9) (0xE8) (0xE7) (0xE6) (0xE5) (0xE4) (0xE3) (0xE2) (0xE1) (0xE0) (0xDF) (0xDE) (0xDD) (0xDC) (0xDB) (0xDA) (0xD9) (0xD8) (0xD7) (0xD6) (0xD5) (0xD4) (0xD3) (0xD2) (0xD1) (0xD0) (0xCF) (0xCE) (0xCD) (0xCC) (0xCB) (0xCA) (0xC9) (0xC8) (0xC7) (0xC6) (0xC5) (0xC4) (0xC3) (0xC2) (0xC1) (0xC0) Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved BPPLR BPCR CBPTR BPOCD BPSCD BPDUV BPIR CBCR FCSR Reserved Reserved Reserved Reserved Reserved Reserved CADICH CADICL CADRDC CADRCC CADCSRB CADCSRA CADAC3 CADAC2 CADAC1 CADAC0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved BGCRR BGCCR Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved CCSR Bit 7 – – – – – – – – – Bit 6 – – – – – – – – – SCPT[3:0] DCDL[3:0] Bit 5 – – – – – – – – – Bit 4 – – – – – – – – – Bit 3 – – – – – – – – DUVD Bit 2 – – – – – – – – SCD Bit 1 – – – – – – – BPPLE DCD OCPT[3:0] CCDL[3:0] Bit 0 – – – – – – – BPPL CCD Page 128 128 129 130 130 131 – – DUVIF – – – – – – – – – – COCIF – – – – – – – – – DUVT1 DOCIF – PWMOC – – – – – – – DUVT0 SCIF – PWMOPC – – – – – – CADIC[15:8] CADIC[7:0] CADRDC[7:0] CADRCC[7:0] DUVIE CBE4 CPS – – – – – – COCIE CBE3 DFE – – – – – – SCDL[3:0] DUDL[3:0] DOCIE CBE2 CFE – – – – – – SCIE CBE1 PFD – – – – – – 132 137 134 111 111 112 112 – CADACIF CADSI1 CADRCIF CADSI0 CADICIF CADSE 110 109 111 111 111 111 – – – – – – – – – – – – – – – – – – – – – – – – – – – – BGCR2 BGCC2 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – BGCR1 BGCC1 – – – – – – – – – – – – – – – XOE – – – – – – – – – – – – – – BGCR0 BGCC0 – – – – – – – – – – – – – – – ACS 29 123 123 – CADEN CADACIE – CADRCIE CADUB CADICIE CADAS1 CADAS0 CADAC[31:24] CADAC[23:16] CADAC[15:8] CADAC[7:0] – – – – – – – – – – – – – – BGCR7 BGEN – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – BGCR6 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – BGCR5 BGCC5 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – BGCR4 BGCC4 – – – – – – – – – – – – – – – – BGCR3 BGCC3 – – – – – – – – – – – – – – – – 8 ATmega406 2548ES–AVR–07/06 ATmega406 Address (0xBF) (0xBE) (0xBD) (0xBC) (0xBB) (0xBA) (0xB9) (0xB8) (0xB7) (0xB6) (0xB5) (0xB4) (0xB3) (0xB2) (0xB1) (0xB0) (0xAF) (0xAE) (0xAD) (0xAC) (0xAB) (0xAA) (0xA9) (0xA8) (0xA7) (0xA6) (0xA5) (0xA4) (0xA3) (0xA2) (0xA1) (0xA0) (0x9F) (0x9E) (0x9D) (0x9C) (0x9B) (0x9A) (0x99) (0x98) (0x97) (0x96) (0x95) (0x94) (0x93) (0x92) (0x91) (0x90) (0x8F) (0x8E) (0x8D) (0x8C) (0x8B) (0x8A) (0x89) (0x88) (0x87) (0x86) (0x85) (0x84) (0x83) (0x82) (0x81) (0x80) (0x7F) (0x7E) Name Reserved TWBCSR TWAMR TWCR TWDR TWAR TWSR TWBR Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved OCR1AH OCR1AL Reserved Reserved TCNT1H TCNT1L Reserved Reserved TCCR1B Reserved Reserved DIDR0 Bit 7 – TWBCIF TWINT Bit 6 – TWBCIE TWEA Bit 5 – – TWSTA Bit 4 – – TWAM[6:0] TWSTO TWA[6:0] Bit 3 – – TWWC Bit 2 – TWBDT1 TWEN Bit 1 – TWBDT0 – Bit 0 – TWBCIP – TWIE TWGCE Page 169 150 147 149 149 148 147 2–wire Serial Interface Data Register TWS[7:3] 2–wire Serial Interface Bit Rate Register – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – TWPS1 TWPS0 Timer/Counter1 – Output Compare Register A High Byte Timer/Counter1 – Output Compare Register A Low Byte – – – – – – – – – – – – – – – – 101 101 Timer/Counter1 – Counter Register High Byte Timer/Counter1 – Counter Register Low Byte – – – – – – – – – – – – – – – – – – – – – – – – – – CTC1 – – VADC3D – – CS12 – – VADC2D – – CS11 – – VADC1D – – CS10 – – VADC0D 101 101 100 120 9 2548ES–AVR–07/06 Address (0x7D) (0x7C) (0x7B) (0x7A) (0x79) (0x78) (0x77) (0x76) (0x75) (0x74) (0x73) (0x72) (0x71) (0x70) (0x6F) (0x6E) (0x6D) (0x6C) (0x6B) (0x6A) (0x69) (0x68) (0x67) (0x66) (0x65) (0x64) (0x63) (0x62) (0x61) (0x60) 0x3F (0x5F) 0x3E (0x5E) 0x3D (0x5D) 0x3C (0x5C) 0x3B (0x5B) 0x3A (0x5A) 0x39 (0x59) 0x38 (0x58) 0x37 (0x57) 0x36 (0x56) 0x35 (0x55) 0x34 (0x54) 0x33 (0x53) 0x32 (0x52) 0x31 (0x51) 0x30 (0x50) 0x2F (0x4F) 0x2E (0x4E) 0x2D (0x4D) 0x2C (0x4C) 0x2B (0x4B) 0x2A (0x4A) 0x29 (0x49) 0x28 (0x48) 0x27 (0x47) 0x26 (0x46) 0x25 (0x45) 0x24 (0x44) 0x23 (0x43) 0x22 (0x42) 0x21 (0x41) 0x20 (0x40) 0x1F (0x3F) 0x1E (0x3E) 0x1D (0x3D) 0x1C (0x3C) Name Reserved VADMUX Reserved VADCSR VADCH VADCL Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved TIMSK1 TIMSK0 Reserved PCMSK1 PCMSK0 Reserved EICRA PCICR Reserved FOSCCAL Reserved PRR0 Reserved WUTCSR Reserved WDTCSR SREG SPH SPL Reserved Reserved Reserved Reserved Reserved SPMCSR Reserved MCUCR MCUSR SMCR Reserved OCDR Reserved Reserved Reserved Reserved Reserved GPIOR2 GPIOR1 Reserved OCR0B OCR0A TCNT0 TCCR0B TCCR0A GTCCR EEARH EEARL EEDR EECR GPIOR0 EIMSK EIFR Bit 7 – – – – – – – – – – – – – – – – Bit 6 – – – – – – – – – – – – – – – – Bit 5 – – – – – – – – – – – – – – – – Bit 4 – – – – – Bit 3 – VADMUX3 – VADEN Bit 2 – VADMUX2 – VADSC Bit 1 – VADMUX1 – VADCCIF Bit 0 – VADMUX0 – VADCCIE Page 118 118 119 119 VADC Data Register High byte – – – – – – – – – – – PCINT[15:8] PCINT[7:0] – – – – – – – – – OCIE0B – – – – – – – – – OCIE1A OCIE0A – – – – – – – – – TOIE1 TOIE0 – VADC Data Register Low byte – – – – – – – – – – – 102 93 59 59 – ISC31 – – – – – WUTIF – WDIF I SP15 SP7 – – – – – SPMIE – JTD – – – – – – – – – ISC30 – – – – – WUTIE – WDIE T SP14 SP6 – – – – – RWWSB – – – – – – – – – – – ISC21 – – – – – WUTCF – WDP3 H SP13 SP5 – – – – – SIGRD – – – – – – – – – – – ISC20 – – – – – WUTR – WDCE S SP12 SP4 – – – – – RWWSRE – PUD JTRF – – – – – – – – ISC11 – – – PRTWI – WUTE – WDE V SP11 SP3 – – – – – BLBSET – – WDRF SM2 – – – – – – – ISC10 – – – PRTIM1 – WUTP2 – WDP2 N SP10 SP2 – – – – – PGWRT – – BODRF SM1 – – – – – – – ISC01 PCIE1 – – PRTIM0 – WUTP1 – WDP1 Z SP9 SP1 – – – – – PGERS – IVSEL EXTRF SM0 – – – – – – – ISC00 PCIE0 – 29 – PRVADC – WUTP0 – WDP0 C SP8 SP0 – – – – – SPMEN – IVCE PORF SE – 176 – – – – – 24 24 55/73/176 46 31 183 47 10 12 12 49 36 56 58 Fast Oscillator Calibration Register On-Chip Debug Register General Purpose I/O Register 2 General Purpose I/O Register 1 – – – – – – – – Timer/Counter0 Output Compare Register B Timer/Counter0 Output Compare Register A Timer/Counter0 (8 Bit) FOC0A COM0A1 TSM – FOC0B COM0A0 – – – COM0B1 – – – COM0B0 – – WGM02 – – – CS02 – – – CS01 WGM01 – – CS00 WGM00 PSRSYNC High Byte 92 92 92 91 88 105 19 19 19 EEPROM Address Register Low Byte EEPROM Data Register – – – – – – EEPM1 – – EEPM0 – – EERIE INT3 INTF3 EEMPE INT2 INTF2 EEPE INT1 INTF1 EERE INT0 INTF0 General Purpose I/O Register 0 19 24 57 57 10 ATmega406 2548ES–AVR–07/06 ATmega406 Address 0x1B (0x3B) 0x1A (0x3A) 0x19 (0x39) 0x18 (0x38) 0x17 (0x37) 0x16 (0x36) 0x15 (0x35) 0x14 (0x34) 0x13 (0x33) 0x12 (0x32) 0x11 (0x31) 0x10 (0x30) 0x0F (0x2F) 0x0E (0x2E) 0x0D (0x2D) 0x0C (0x2C) 0x0B (0x2B) 0x0A (0x2A) 0x09 (0x29) 0x08 (0x28) 0x07 (0x27) 0x06 (0x26) 0x05 (0x25) 0x04 (0x24) 0x03 (0x23) 0x02 (0x22) 0x01 (0x21) 0x00 (0x20) Name PCIFR Reserved Reserved Reserved Reserved TIFR1 TIFR0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PORTD DDRD PIND PORTC Reserved Reserved PORTB DDRB PINB PORTA DDRA PINA Bit 7 – – – – – – – – – – – – – – – – – – – – – – PORTB7 DDB7 PINB7 PORTA7 DDA7 PINA7 Bit 6 – – – – – – – – – – – – – – – – – – – – – – PORTB6 DDB6 PINB6 PORTA6 DDA6 PINA6 Bit 5 – – – – – – – – – – – – – – – – – – – – – – PORTB5 DDB5 PINB5 PORTA5 DDA5 PINA5 Bit 4 – – – – – – – – – – – – – – – – – – – – – – PORTB4 DDB4 PINB4 PORTA4 DDA4 PINA4 Bit 3 – – – – – – – – – – – – – – – – – – – – – – PORTB3 DDB3 PINB3 PORTB3 DDA3 PINA3 Bit 2 – – – – – – OCF0B – – – – – – – – – – – – – – – PORTB2 DDB2 PINB2 PORTA2 DDA2 PINA2 Bit 1 PCIF1 – – – – OCF1A OCF0A – – – – – – – – – PORTD1 DDD1 PIND1 – – – PORTB1 DDB1 PINB1 PORTA1 DDA1 PINA1 Bit 0 PCIF0 – – – – TOV1 TOV0 – – – – – – – – – PORTD0 DDD0 PIND0 PORTC0 – – PORTB0 DDB0 PINB0 PORTA0 DDA0 PINA0 Page 102 94 74 74 74 76 74 74 74 73 73 73 Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 4. When using the I/O specific commands IN and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O registers as data space using LD and ST instructions, $20 must be added to these addresses. The ATmega406 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from $60 - $FF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. 11 2548ES–AVR–07/06 5. Instruction Set Summary Mnemonics ADD ADC ADIW SUB SUBI SBC SBCI SBIW AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER MUL MULS MULSU FMUL FMULS FMULSU RJMP IJMP JMP RCALL ICALL CALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC Rd,Rr Rd,Rr Rd,Rr Rd,K Rr, b Rr, b P, b P, b s, k s, k k k k k k k k k k k k k k k k k k k k Operands Rd, Rr Rd, Rr Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd Rd Rd,K Rd,K Rd Rd Rd Rd Rd Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr k Add two Registers Description Rd ← Rd + Rr Operation Flags Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None Z,C Z,C Z,C Z,C Z,C Z,C None None None None None None None I None Z, N,V,C,H Z, N,V,C,H Z, N,V,C,H None None None None None None None None None None None None None None None None None None None None None None #Clocks 1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 3 3 3 4 4 4 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 ARITHMETIC AND LOGIC INSTRUCTIONS Add with Carry two Registers Add Immediate to Word Subtract two Registers Subtract Constant from Register Subtract with Carry two Registers Subtract with Carry Constant from Reg. Subtract Immediate from Word Logical AND Registers Logical AND Register and Constant Logical OR Registers Logical OR Register and Constant Exclusive OR Registers One’s Complement Two’s Complement Set Bit(s) in Register Clear Bit(s) in Register Increment Decrement Test for Zero or Minus Clear Register Set Register Multiply Unsigned Multiply Signed Multiply Signed with Unsigned Fractional Multiply Unsigned Fractional Multiply Signed Fractional Multiply Signed with Unsigned Relative Jump Indirect Jump to (Z) Direct Jump Relative Subroutine Call Indirect Call to (Z) Direct Subroutine Call Subroutine Return Interrupt Return Compare, Skip if Equal Compare Compare with Carry Compare Register with Immediate Skip if Bit in Register Cleared Skip if Bit in Register is Set Skip if Bit in I/O Register Cleared Skip if Bit in I/O Register is Set Branch if Status Flag Set Branch if Status Flag Cleared Branch if Equal Branch if Not Equal Branch if Carry Set Branch if Carry Cleared Branch if Same or Higher Branch if Lower Branch if Minus Branch if Plus Branch if Greater or Equal, Signed Branch if Less Than Zero, Signed Branch if Half Carry Flag Set Branch if Half Carry Flag Cleared Branch if T Flag Set Branch if T Flag Cleared Branch if Overflow Flag is Set Branch if Overflow Flag is Cleared Rd ← Rd + Rr + C Rdh:Rdl ← Rdh:Rdl + K Rd ← Rd - Rr Rd ← Rd - K Rd ← Rd - Rr - C Rd ← Rd - K - C Rdh:Rdl ← Rdh:Rdl - K Rd ← Rd • Rr Rd ← Rd • K Rd ← Rd v Rr Rd ← Rd v K Rd ← Rd ⊕ Rr Rd ← 0xFF − Rd Rd ← 0x00 − Rd Rd ← Rd v K Rd ← Rd • (0xFF - K) Rd ← Rd + 1 Rd ← Rd − 1 Rd ← Rd • Rd Rd ← Rd ⊕ Rd Rd ← 0xFF R1:R0 ← Rd x Rr R1:R0 ← Rd x Rr R1:R0 ← Rd x Rr 1 R1:R0 ← (Rd x Rr)