ATMEGA4HVD

Features • High Performance, Low Power AVR® 8-bit Microcontroller • Advanced RISC Architecture – 124 Powerful Instructions - Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 4 MIPS Throughput at 4 MHz Nonvolatile Program and Data Memories – 4K/8K Bytes of In-System Self-Programmable Flash (ATmega4HVD/8HVD) – 256 Bytes EEPROM – 512 Bytes Internal SRAM – Write/Erase Cycles: 10,000 Flash/ 100,000 EEPROM – Data Retention: 20 years at 85°C /100 years at 25°C(1) – Programming Lock for Software Security Battery Management Features – One Cell Batteries – Short-circuit Protection (Discharge) – Over-current Protection (Charge and Discharge) – External Protection Input – High Voltage Outputs to Drive N-Channel Charge/Discharge FETs – Operation with 1 FET or 2 FETs supported Charge FET is optional – Battery authentication features (Available only under NDA) Peripheral Features – Two 8/16-bit Timer/Counters with Separate Prescaler and two output compare units – 10-bit ADC with One External Input – Two High-voltage open-drain I/O pins – Programmable Watchdog Timer Special Microcontroller Features – debugWIRE On-chip Debug System – In-System Programmable – Power-on Reset – On-chip Voltage Reference with built-in Temperature Sensor – On-chip Voltage Regulator – External and Internal Interrupt Sources – Sleep Modes: Idle, ADC Noise Reduction, Power-save, and Power-off Package – 18-pad DRDFN/ MLF Operating Voltage (VFET): 2.1 - 6.0V Operating Voltage (VCC ):2.0 - 2.4V Maximum Withstand Voltage (VFET): 12V Maximum Withstand Voltage (High-voltage pins): 5V Temperature Range: -20°C to 85°C Speed Grade: 1 - 4 MHz • • 8-bit Microcontroller with 4K/8K Bytes In-System Programmable Flash ATmega4HVD ATmega8HVD Preliminary Summary • • • • • • • • • 8052BS–AVR–09/08 ATmega4HVD/8HVD 1. Pin Configurations Figure 1-1. Dual Row DFN/ MLF-pinout ATmega4HVD/8HVD. Top view Bottom view B10 A8 B9 A7 B8 A6 B7 A5 B6 B5 B4 A4 B3 A3 B2 A2 B1 A1 Table 1-1. 1 DNC Dual Row DFN/ MLF-pinout ATmega4HVD/8HVD. 2 BATT 3 GND 4 PV1 5 PB1 (SCK/ SGND/T0) NI 6 DNC PB0 (ADC0) 7 VCC PB2 (MISO/CKOUT/T1) 8 PC1 (MOSI/INT1/ EXT_PROT) GND 9 PC0 (INT0/ICP0/XTAL) 10 - A B OD OC VFET VREG RESET 2 8052BS–AVR–09/08 ATmega4HVD/8HVD 1.1 1.1.1 Pin Descriptions VFET Input to the internal voltage regulator. 1.1.2 VCC Pin for connection of external decoupling capacitor. VCC is internally connected to the voltage regulator output VREG. 1.1.3 VREG Output from the internal voltage regulator. Internally connected to VCC. 1.1.4 GND Ground 1.1.5 Port B (PB2:PB0) Port B is a low-voltage 3-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATmega4HVD/8HVD. 1.1.6 Port C (PC1:PC0) Port C is a High-voltage open-drain 2 bit bi-directional I/O port. Port C also serves the functions of various special features of the ATmega4HVD/8HVD. 1.1.7 OC High voltage output to drive Charge FET (optional). 1.1.8 OD High voltage output to drive Discharge FET. 1.1.9 NI Negative input from the battery protection resistor. 1.1.10 PV1 Input from battery cell to ADC. 1.1.11 BATT Input for detecting when a charger is connected. 1.1.12 RESET/dw Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. This pin is also used as debugWIRE communication pin. 3 8052BS–AVR–09/08 ATmega4HVD/8HVD 2. Overview The ATmega4HVD/8HVD is a monitoring and protection circuit for 1-cell Li-ion applications with focus on high security/authentication, low cost and high utilization of the cell energy. The device contains secure authentication features as well as autonomous battery protection during charging and discharging. The External Protection Input can be used to implement other battery protection mechanisms using external components, e.g. protection against chargers with too high charge voltage can be easily implemented with a few low cost passive components. The feature set makes the ATmega4HVD/8HVD a key component in any system focusing on high security, battery protection, high system utilization and low cost. Figure 2-1. Block Diagram PB2:0 Oscillator Circuits / Clock Generation PB2 (CKOUT) PORTB (3) PB0 (ADC0) Watchdog Oscillator VCC Watchdog Timer Oscillator Sampling Interface SPI Program Logic Flash SRAM FET Control 8/16-bit T/C0 OC OD 8/16-bit T/C1 Battery Protection NI RESET/dW Power Supervision POR & RESET debugWIRE EEPROM CPU Voltage ADC PV1 GND GND BATT Charger Detect Security Module DATA BUS Voltage Reference VFET VREG Voltage Regulator Voltage Regulator Monitor Interface PORTC (2) PC1 (External Protection Input) PC1:0 An integrated, low-dropout linear regulator that can handle input voltages as low as 2.1V, ensures that the stored energy can be fully exploited. The regulator capabilities, combined with a extremely low power consumption in the power saving modes, greatly enhances the cell energy utilization compared to existing solutions. The chip utilizes Atmel's Deep Under-voltage Recovery (DUVR) mode that supports precharging of deeply discharged battery cells without using a separate Pre-charge FET. An enhanced start-up scheme allows the chip to operate correctly even with only Discharge FET connected. This makes it possible to further reduce system cost for applications that do not require Charge Over-current protection. The ATmega4HVD/8HVD contains a 10-bit ADC for cell voltage measurements. The ADC is also used to monitor the on-chip temperature. Temperature is measured by the integrated Voltage Reference, which contains a built-in temperature sensor. ATmega4HVD/8HVD con4 8052BS–AVR–09/08 ATmega4HVD/8HVD tains a high-voltage tolerant, open-drain IO pin that supports serial communication. Programming can be done in-system using the 4 General Purpose IO ports that support SPI programming The MCU includes 4K/8K bytes of In-System Programmable Flash with Self-programming capabilities, 256 bytes EEPROM, 512 bytes SRAM, 32 general purpose working registers, 4 general purpose I/O lines, debugWIRE for On-chip debugging and SPI for In-system Programming, two flexible Timer/Counters with Input Capture, internal and external interrupts, a 10-bit ADC for measuring the cell voltage and on-chip temperature, a programmable Watchdog Timer with wake-up capabilities, and software selectable power saving modes. The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The device is manufactured using Atmel’s high voltage high density non-volatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed In-System, by a conventional non-volatile memory programmer or by an On-chip Boot program running on the AVR core. The ATmega4HVD/8HVD AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, and On-chip Debugger. The ATmega4HVD/8HVD is a low-power CMOS 8-bit microcontroller based on the AVR architecture. It is part of the AVR Smart Battery family that provides secure authentication, highly accurate monitoring and autonomous protection for Lithium-ion battery cells. 3. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. Note: 1. 4. Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. 5 8052BS–AVR–09/08 ATmega4HVD/8HVD 5. Register Summary Address (0xFF) (0xFE) (0xFD) (0xFC) (0xFB) (0xFA) (0xF9) (0xF8) (0xF7) (0xF6) (0xF5) (0xF4) (0xF3) (0xF2) (0xF1) (0xF0) (0xEF) (0xEE) (0xED) (0xEC) (0xEB) (0xEA) (0xE9) (0xE8) (0xE7) (0xE6) (0xE5) (0xE4) (0xE3) (0xE2) (0xE1) (0xE0) (0xDF) (0xDE) (0xDD) (0xDC) (0xDB) (0xDA) (0xD9) (0xD8) (0xD7) (0xD6) (0xD5) (0xD4) (0xD3) (0xD2) (0xD1) (0xD0) (0xCF) (0xCE) (0xCD) (0xCC) (0xCB) (0xCA) (0xC9) (0xC8) (0xC7) (0xC6) (0xC5) (0xC4) (0xC3) (0xC2) (0xC1) (0xC0) Name Reserved BPPLR BPCR Reserved BPOCTR BPSCTR Reserved Reserved BPCOCD BPDOCD BPSCD Reserved BPIFR BPIMSK Reserved FCSR Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved ROCR Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Bit 7 – – – – – – – – Bit 6 – – – – – – – Bit 5 – – EPID – Bit 4 – – SCD – Bit 3 – – DOCD – Bit 2 – – COCD – OCTR[5:0] Bit 1 – BPPLE – – Bit 0 – BPPL – – Page SCTR[6:0] – – – – COCDL[7:0] DOCDL[7:0] SCDL[7:0] – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – ROCS – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – SCIF SCIE – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – DOCIF DOCIE – DUVRD – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – COCIF COCIE – CPS – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – RSCDEN – – – – – – – – – – – – DFE – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – RSCWIF – – – – – – – – – – – – CFE – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – RSCWIE – – – – – – – – 6 8052BS–AVR–09/08 ATmega4HVD/8HVD Address (0xBF) (0xBE) (0xBD) (0xBC) (0xBB) (0xBA) (0xB9) (0xB8) (0xB7) (0xB6) (0xB5) (0xB4) (0xB3) (0xB2) (0xB1) (0xB0) (0xAF) (0xAE) (0xAD) (0xAC) (0xAB) (0xAA) (0xA9) (0xA8) (0xA7) (0xA6) (0xA5) (0xA4) (0xA3) (0xA2) (0xA1) (0xA0) (0x9F) (0x9E) (0x9D) (0x9C) (0x9B) (0x9A) (0x99) (0x98) (0x97) (0x96) (0x95) (0x94) (0x93) (0x92) (0x91) (0x90) (0x8F) (0x8E) (0x8D) (0x8C) (0x8B) (0x8A) (0x89) (0x88) (0x87) (0x86) (0x85) (0x84) (0x83) (0x82) (0x81) (0x80) (0x7F) (0x7E) Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved OCR1B OCR1A Reserved Reserved TCNT1H TCNT1L Reserved Reserved TCCR1B TCCR1A Reserved DIDR0 Bit 7 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Bit 6 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Bit 5 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Bit 4 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Bit 3 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Bit 2 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Bit 1 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Bit 0 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Page Timer/Counter1 - Output Compare Register B Timer/Counter1 - Output Compare Register A – – – – – – – – – – – – – – – – Timer/Counter1 - Counter Register High Byte Timer/Counter1 - Counter Register Low Byte – – – TCW1 – – – – – ICEN1 – – – – – ICNC1 – – – – – ICES1 – – – – – ICS1 – – – – CS12 – – – – – CS11 – – – – – CS10 WGM10 – PB0DID 7 8052BS–AVR–09/08 ATmega4HVD/8HVD Address (0x7D) (0x7C) (0x7B) (0x7A) (0x79) (0x78) (0x77) (0x76) (0x75) (0x74) (0x73) (0x72) (0x71) (0x70) (0x6F) (0x6E) (0x6D) (0x6C) (0x6B) (0x6A) (0x69) (0x68) (0x67) (0x66) (0x65) (0x64) (0x63) (0x62) (0x61) (0x60) 0x3F (0x5F) 0x3E (0x5E) 0x3D (0x5D) 0x3C (0x5C) 0x3B (0x5B) 0x3A (0x5A) 0x39 (0x59) 0x38 (0x58) 0x37 (0x57) 0x36 (0x56) 0x35 (0x55) 0x34 (0x54) 0x33 (0x53) 0x32 (0x52) 0x31 (0x51) 0x30 (0x50) 0x2F (0x4F) 0x2E (0x4E) 0x2D (0x4D) 0x2C (0x4C) 0x2B (0x4B) 0x2A (0x4A) 0x29 (0x49) 0x28 (0x48) 0x27 (0x47) 0x26 (0x46) 0x25 (0x45) 0x24 (0x44) 0x23 (0x43) 0x22 (0x42) 0x21 (0x41) 0x20 (0x40) 0x1F (0x3F) 0x1E (0x3E) 0x1D (0x3D) 0x1C (0x3C) Name Reserved Reserved Reserved ADCSRA ADCH ADCL Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved TIMSK1 TIMSK0 Reserved Reserved Reserved Reserved EICRA Reserved Reserved FOSCCAL Reserved PRR0 Reserved Reserved CLKPR WDTCSR SREG SPH SPL Reserved Reserved Reserved Reserved Reserved SPMCSR Reserved MCUCR MCUSR SMCR Reserved DWDR Reserved Reserved Reserved Reserved Reserved GPIOR2 GPIOR1 OCR0B OCR0A TCNT0H TCNT0L TCCR0B TCCR0A GTCCR Reserved EEARL EEDR EECR GPIOR0 EIMSK EIFR Bit 7 – – – ADEN – – – – – – – – – – – – – – – – – – – – – – CLKPCE WDIF I SP15 SP7 – – – – – – – – – – – – – – – – Bit 6 – – – ADSC – – – – – – – – – – – – – – – – – – – – – – – WDIE T SP14 SP6 – – – – – – – – – – – – – – – – Bit 5 – – – – – – – – – – – – – – – – – – – – – – – PRVRM – – – WDP3 H SP13 SP5 – – – – – SIGRD – CKOE – – – – – – – – Bit 4 – – – ADIF – ADC[7:0] – – – – – – – – – – – – – – – – – – – – – – WDCE S SP12 SP4 – – – – – CTPB – PUD OCDRF – – – – – – – Bit 3 – – – ADIE – – – – – – – – – ICIE1 ICIE0 – – – – ISC11 – – – PRSPI – – – WDE V SP11 SP3 – – – – – RFLB – – WDRF SM2 – – – – – – Bit 2 – – – – – – – – – – – – – OCIE1B OCIE0B – – – – ISC10 – – – PRTIM1 – – – WDP2 N SP10 SP2 – – – – – PGWRT – – – SM1 – – – – – – Bit 1 – – – ADMUX1 ADC9 – – – – – – – – OCIE1A OCIE0A – – – – ISC01 – – – PRTIM0 – – CLKPS1 WDP1 Z SP9 SP1 – – – – – PGERS – – EXTRF SM0 – – – – – – Bit 0 – – – ADMUX0 ADC8 – – – – – – – – TOIE1 TOIE0 – – – – ISC00 – – – PRADC – – CLKPS0 WDP0 C SP8 SP0 – – – – – SPMEN – – PORF SE – – – – – – Page Fast Oscillator Calibration Register debugWIRE Data Register General Purpose I/O Register 2 General Purpose I/O Register 1 Timer/Counter0 - Output Compare Register A Timer/Counter0 - Output Compare Register B Timer/Counter0 - Counter Register High Byte Timer/Counter0 - Counter Register Low Byte – TCW0 TSM – – ICEN0 – – – ICNC0 – – – ICES0 – – – ICS0 – – CS02 – – – CS01 – – – CS00 WGM00 PSR – EEPROM Address Register EEPROM Data Register – – – – – – EEPM1 – – EEPM0 – – EERIE – – EEMPE – – EEPE INT1 INTF1 EERE INT0 INTF0 General Purpose I/O Register 0 8 8052BS–AVR–09/08 ATmega4HVD/8HVD Address 0x1B (0x3B) 0x1A (0x3A) 0x19 (0x39) 0x18 (0x38) 0x17 (0x37) 0x16 (0x36) 0x15 (0x35) 0x14 (0x34) 0x13 (0x33) 0x12 (0x32) 0x11 (0x31) 0x10 (0x30) 0x0F (0x2F) 0x0E (0x2E) 0x0D (0x2D) 0x0C (0x2C) 0x0B (0x2B) 0x0A (0x2A) 0x09 (0x29) 0x08 (0x28) 0x07 (0x27) 0x06 (0x26) 0x05 (0x25) 0x04 (0x24) 0x03 (0x23) 0x02 (0x22) 0x01 (0x21) 0x00 (0x20) Name Reserved Reserved Reserved Reserved OSICSR TIFR1 TIFR0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PORTC Reserved PINC PORTB DDRB PINB Reserved Reserved Reserved Bit 7 – – – – – – – – – – – – – – – – – – – – – – – – – – – – Bit 6 – – – – – – – – – – – – – – – – – – – – – – – – – – – – Bit 5 – – – – – – – – – – – – – – – – – – – – – – – – – – – – Bit 4 – – – – OSISEL0 – – – – – – – – – – – – – – – – – – – – – – – Bit 3 – – – – – ICF1 ICF0 – – – – – – – – – – – – – – – – – – – – – Bit 2 – – – – – OCF1B OCF0B – – – – – – – – – – – – – – – PORTB2 DDB2 PINB2 – – – Bit 1 – – – – OSIST OCF1A OCF0A – – – – – – – – – – – – PORTC1 – PINC1 PORTB1 DDB1 PINB1 – – – Bit 0 – – – – OSIEN TOV1 TOV0 – – – – – – – – – – – – PORTC0 – PINC0 PORTB0 DDB0 PINB0 – – – Page Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 4. When using the I/O specific commands IN and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O registers as data space using LD and ST instructions, $20 must be added to these addresses. The ATmega4HVD/8HVD is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from $60 - $FF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. 9 8052BS–AVR–09/08 ATmega4HVD/8HVD 6. Instruction Set Summary Mnemonics ADD ADC ADIW SUB SUBI SBC SBCI SBIW AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER MUL MULS MULSU FMUL FMULS FMULSU RJMP IJMP JMP RCALL ICALL CALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS Rd,Rr Rd,Rr Rd,Rr Rd,K Rr, b Rr, b P, b P, b s, k s, k k k k k k k k k k k k k k k k k k k Operands Rd, Rr Rd, Rr Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd Rd Rd,K Rd,K Rd Rd Rd Rd Rd Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr k Add two Registers Description Rd ← Rd + Rr Operation Flags Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None Z,C Z,C Z,C Z,C Z,C Z,C None None None None None None None I None Z, N,V,C,H Z, N,V,C,H Z, N,V,C,H None None None None None None None None None None None None None None None None None None None None None #Clocks 1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 3 3 3 4 4 4 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 ARITHMETIC AND LOGIC INSTRUCTIONS Add with Carry two Registers Add Immediate to Word Subtract two Registers Subtract Constant from Register Subtract with Carry two Registers Subtract with Carry Constant from Reg. Subtract Immediate from Word Logical AND Registers Logical AND Register and Constant Logical OR Registers Logical OR Register and Constant Exclusive OR Registers One’s Complement Two’s Complement Set Bit(s) in Register Clear Bit(s) in Register Increment Decrement Test for Zero or Minus Clear Register Set Register Multiply Unsigned Multiply Signed Multiply Signed with Unsigned Fractional Multiply Unsigned Fractional Multiply Signed Fractional Multiply Signed with Unsigned Relative Jump Indirect Jump to (Z) Direct Jump Relative Subroutine Call Indirect Call to (Z) Direct Subroutine Call Subroutine Return Interrupt Return Compare, Skip if Equal Compare Compare with Carry Compare Register with Immediate Skip if Bit in Register Cleared Skip if Bit in Register is Set Skip if Bit in I/O Register Cleared Skip if Bit in I/O Register is Set Branch if Status Flag Set Branch if Status Flag Cleared Branch if Equal Branch if Not Equal Branch if Carry Set Branch if Carry Cleared Branch if Same or Higher Branch if Lower Branch if Minus Branch if Plus Branch if Greater or Equal, Signed Branch if Less Than Zero, Signed Branch if Half Carry Flag Set Branch if Half Carry Flag Cleared Branch if T Flag Set Branch if T Flag Cleared Branch if Overflow Flag is Set Rd ← Rd + Rr + C Rdh:Rdl ← Rdh:Rdl + K Rd ← Rd - Rr Rd ← Rd - K Rd ← Rd - Rr - C Rd ← Rd - K - C Rdh:Rdl ← Rdh:Rdl - K Rd ← Rd • Rr Rd ← Rd • K Rd ← Rd v Rr Rd ← Rd v K Rd ← Rd ⊕ Rr Rd ← 0xFF − Rd Rd ← 0x00 − Rd Rd ← Rd v K Rd ← Rd • (0xFF - K) Rd ← Rd + 1 Rd ← Rd − 1 Rd ← Rd • Rd Rd ← Rd ⊕ Rd Rd ← 0xFF R1:R0 ← Rd x Rr R1:R0 ← Rd x Rr R1:R0 ← Rd x Rr 1 R1:R0 ← (Rd x Rr)