ATMEGA6450A

Features • • High Performance, Low Power AVR® 8-Bit Microcontroller Advanced RISC Architecture – 130 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 16 MIPS Throughput at 16 MHz (ATmega165PA/645P) – Up to 20 MIPS Throughput at 20 MHz (ATmega165A/325A/325PA/645A/3250A/3250PA/6450A/6450P) – On-Chip 2-cycle Multiplier High Endurance Non-volatile Memory segments – In-System Self-programmable Flash Program Memory • 16K Bytes (ATmega165A/ATmega165PA) • 32K Bytes (ATmega325A/ATmega325PA/ATmega3250A/ATmega3250PA) • 64K Bytes (ATmega645A/ATmega645P/ATmega6450A/ATmega6450P) – EEPROM • 512 Bytes (ATmega165A/ATmega165PA) • 1K bytes (ATmega325A/ATmega325PA/ATmega3250A/ATmega3250PA) • 2K bytes (ATmega645A/ATmega645P/ATmega6450A/ATmega6450P) – Internal SRAM • 1K Bytes (ATmega165A/ATmega165PA) • 2K Bytes (ATmega325A/ATmega325PA/ATmega3250A/ATmega3250PA) • 4K Bytes (ATmega645A/ATmega645P/ATmega6450A/ATmega6450P) – Write/Erase cycles: 10,000 Flash/100,000 EEPROM – Data retention: 20 years at 85°C/100 years at 25°C(1) – Optional Boot Code Section with Independent Lock Bits • In-System Programming by On-chip Boot Program • True Read-While-Write Operation – Programming Lock for Software Security QTouch® library support – Capacitive touch buttons, sliders and wheels – QTouch and QMatrix acquisition – Up to 64 sense channels JTAG (IEEE std. 1149.1 compliant) Interface – Boundary-scan Capabilities According to the JTAG Standard – Extensive On-chip Debug Support – Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface Peripheral Features – Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode – One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode – Real Time Counter with Separate Oscillator – Four PWM Channels – 8-channel, 10-bit ADC – Programmable Serial USART – Master/Slave SPI Serial Interface – Universal Serial Interface with Start Condition Detector – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator – Interrupt and Wake-up on Pin Change Special Microcontroller Features – Power-on Reset and Programmable Brown-out Detection – Internal Calibrated Oscillator – External and Internal Interrupt Sources – Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and Standby I/O and Packages – 54/69 Programmable I/O Lines – 64/100-lead TQFP, 64-pad QFN/MLF and 64-pad DRQFN Speed Grade: – ATmega 165A/165PA/645A/645P: 0 - 16 MHz @ 1.8 - 5.5V – ATmega325A/325PA/3250A/3250PA/6450A/6450P: 0 - 20MHz @ 1.8 - 5.5V Temperature range: – -40°C to 85°C Industrial Ultra-Low Power Consumption (picoPower devices) – Active Mode: • 1 MHz, 1.8V: 215 µA • 32 kHz, 1.8V: 8 µA (including Oscillator) – Power-down Mode: 0.1 µA at 1.8V – Power-save Mode: 0.6 µA at 1.8V (Including 32 kHz RTC • 8-bit Microcontroller with 16/32/64K Bytes In-System Programmable Flash ATmega165A ATmega165PA ATmega325A ATmega325PA ATmega3250A ATmega3250PA ATmega645A ATmega645P ATmega6450A ATmega6450P Preliminary Summary • • • • • • • • Note: 1. Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. Rev 8285AS–AVR–10/10 ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P 1. Pin Configurations 1.1 Pinout - TQFP and QFN/MLF 64A (TQFP)and 64M1 (QFN/MLF) Pinout ATmega165A/ATmega165PA/ATmega325A/ATmega325PA/ATmega645A/ATmega645P 56 PF5 (ADC5/TMS) 55 PF6 (ADC6/TDO) 57 PF4 (ADC4/TCK) 54 PF7 (ADC7/TDI) Figure 1-1. 61 PF0 (ADC0) 60 PF1 (ADC1) 59 PF2 (ADC2) 58 PF3 (ADC3) AVCC AREF 53 GND GND 52 VCC 51 PA0 50 PA1 64 63 62 49 PA2 48 PA3 47 PA4 46 PA5 45 PA6 44 PA7 43 PG2 42 PC7 41 PC6 40 PC5 39 PC4 38 PC3 37 PC2 36 PC1 35 PC0 34 33 PG1 PG0 DNC (RXD/PCINT0) PE0 (TXD/PCINT1) PE1 (XCK/AIN0/PCINT2) PE2 (AIN1/PCINT3) PE3 (USCK/SCL/PCINT4) PE4 (DI/SDA/PCINT5) PE5 (DO/PCINT6) PE6 (CLKO/PCINT7) PE7 (SS/PCINT8) PB0 (SCK/PCINT9) PB1 (MOSI/PCINT10) PB2 (MISO/PCINT11) PB3 (OC0A/PCINT12) PB4 (OC1A/PCINT13) PB5 (OC1B/PCINT14) PB6 1 2 INDEX CORNER 3 4 5 6 7 8 9 10 11 12 13 14 15 16 GND 22 (TOSC2) XTAL2 23 (TOSC1) XTAL1 24 (ICP1) PD0 25 (INT0) PD1 26 PD2 27 PD3 28 (OC2A/PCINT15) PB7 17 (T1) PG3 18 (T0) PG4 19 RESET/PG5 20 VCC 21 PD4 29 PD5 30 PD6 31 Note: The large center pad underneath the QFN/MLF packages is made of metal and internally connected to GND. It should be soldered or glued to the board to ensure good mechanical stability. If the center pad is left unconnected, the package might loosen from the board. PD7 32 2 8285AS–AVR–10/10 ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P 1.2 Pinout - 100A (TQFP) Pinout ATmega3250A/ATmega3250PA/ATmega6450A/ATmega6450P Figure 1-2. TQFP PF5 (ADC5/TMS) PF6 (ADC6/TDO) PF4 (ADC4/TCK) PF7 (ADC7/TDI) PH7 (PCINT23) PH6 (PCINT22) PH5 (PCINT21) PH4 (PCINT20) PF0 (ADC0) PF1 (ADC1) PF2 (ADC2) PF3 (ADC3) AGND AVCC AREF GND DNC DNC DNC DNC DNC VCC PA0 PA1 77 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 DNC (RXD/PCINT0) PE0 (TXD/PCINT1) PE1 (XCK/AIN0/PCINT2) PE2 (AIN1/PCINT3) PE3 (USCK/SCL/PCINT4) PE4 (DI/SDA/PCINT5) PE5 (DO/PCINT6) PE6 (CLKO/PCINT7) PE7 VCC GND DNC (PCINT24) PJ0 (PCINT25) PJ1 DNC DNC DNC DNC (SS/PCINT8) PB0 (SCK/PCINT9) PB1 (MOSI/PCINT10) PB2 (MISO/PCINT11) PB3 (OC0A/PCINT12) PB4 (OC1A/PCINT13) PB5 (OC1B/PCINT14) PB6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 INDEX CORNER 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PA2 PA3 PA4 PA5 PA6 PA7 PG2 PC7 PC6 DNC PH3 (PCINT19) PH2 (PCINT18) PH1 (PCINT17) PH0 (PCINT16) DNC DNC DNC DNC PC5 PC4 PC3 PC2 PC1 PC0 PG1 PG0 (OC2A/PCINT15) PB7 RESET/PG5 (TOSC2) XTAL2 (TOSC1) XTAL1 (ICP1) PD0 (INT0) PD1 GND (T1) PG3 (T0) PG4 VCC DNC DNC (PCINT26) PJ2 (PCINT27) PJ3 (PCINT28) PJ4 (PCINT29) PJ5 (PCINT30) PJ6 DNC PD2 PD3 PD4 PD5 PD6 DNC PD7 3 8285AS–AVR–10/10 ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P 2. Overview The ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, this microcontroller achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Block Diagram Figure 2-1. GND VCC PF0 - PF7 PA0 - PA7 PC0 - PC7 PORTF DRIVERS PORTA DRIVERS PORTC DRIVERS DATA REGISTER PORTF DATA DIR. REG. PORTF DATA REGISTER PORTA DATA DIR. REG. PORTA DATA REGISTER PORTC DATA DIR. REG. PORTC 8-BIT DATA BUS AVCC AGND AREF ADC CALIB. OSC INTERNAL OSCILLATOR OSCILLATOR JTAG TAP DATA DIR. REG. PORTH PROGRAM COUNTER STACK POINTER WATCHDOG TIMER TIMING AND CONTROL PORTH DRIVERS ON-CHIP DEBUG PROGRAM FLASH SRAM MCU CONTROL REGISTER PH0 - PH7 DATA REGISTER PORTH BOUNDARYSCAN INSTRUCTION REGISTER GENERAL PURPOSE REGISTERS X Y Z TIMER/ COUNTERS PROGRAMMING LOGIC INSTRUCTION DECODER INTERRUPT UNIT RESET DATA DIR. REG. PORTD DATA REG. PORTG DATA DIR. REG. PORTG PORTD DRIVERS PORTG DRIVERS PD0 - PD7 PG0 - PG4 DATA DIR. REG. PORTJ CONTROL LINES ALU EEPROM PORTJ DRIVERS AVR CPU STATUS REGISTER PJ0 - PJ6 DATA REGISTER PORTJ USART UNIVERSAL SERIAL INTERFACE SPI ANALOG COMPARATOR DATA REGISTER PORTE DATA DIR. REG. PORTE DATA REGISTER PORTB DATA DIR. REG. PORTB DATA REGISTER PORTD + - PORTE DRIVERS PORTB DRIVERS PE0 - PE7 PB0 - PB7 The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. 4 8285AS–AVR–10/10 XTAL1 XTAL2 ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P The ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P provides the following features: 16K/32K/64K bytes of In-System Programmable Flash with Read-While-Write capabilities, 512/1K/2K bytes EEPROM, 1K/2K/4K byte SRAM, 54/69 general purpose I/O lines, 32 general purpose working registers, a JTAG interface for Boundary-scan, On-chip Debugging support and programming, three flexible Timer/Counters with compare modes, internal and external interrupts, a serial programmable USART, Universal Serial Interface with Start Condition Detector, an 8-channel, 10-bit ADC, a programmable W atchdog Timer with internal Oscillator, an SPI serial port, and five software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or hardware reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low-power consumption. Atmel offers the QTouch® library for embedding capacitive touch buttons, sliders and wheels functionality into AVR microcontrollers. The patented charge-transfer signal acquisition offers robust sensing and includes fully debounced reporting of touch keys and includes Adjacent Key Suppression® (AKSTM™) technology for unambiguous detection of key events. The easy-to-use QTouch Suite toolchain allows you to explore, develop and debug your own touch applications. The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, by a conventional non-volatile memory programmer, or by an On-chip Boot program running on the AVR core. The Boot program can use any interface to download the application program in the Application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel devise is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits. 5 8285AS–AVR–10/10 ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P 2.2 Comparison Between ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P Differences between: ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P Device ATmega165A ATmega165PA ATmega325A ATmega325PA ATmega3250A ATmega3250PA ATmega645A ATmega645P ATmega6450A ATmega6450P Flash 16 Kbyte 16 Kbyte 32 Kbyte 32 Kbyte 32K bytes 32 Kbyte 64 Kbyte 64 Kbyte 64 Kbyte 64 Kbyte EEPROM 512 Bytes 512 Bytes 1 Kbyte 1 Kbyte 1 Kbyte 1 Kbyte 2 Kbyte 2 Kbyte 2 Kbyte 2 Kbyte RAM 1 Kbyte 1 Kbyte 2 Kbyte 2 Kbyte 2 Kbyte 2 Kbyte 4 Kbyte 4 Kbyte 4 Kbyte 4 Kbyte MHz 16 16 20 20 20 20 16 16 20 20 Table 2-1. 2.3 2.3.1 Pin Descriptions VCC Digital supply voltage. 2.3.2 GND Ground. 2.3.3 Port A (PA7:PA0) Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various special features of the ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P as listed on ”Alternate Functions of Port B” on page 76. 2.3.4 Port B (PB7:PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B has better driving capabilities than the other ports. Port B also serves the functions of various special features of the ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P as listed on ”Alternate Functions of Port B” on page 76. 6 8285AS–AVR–10/10 ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P 2.3.5 Port C (PC7:PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port C also serves the functions of special features of the ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P as listed on ”Alternate Functions of Port D” on page 79. 2.3.6 Port D (PD7:PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P as listed on ”Alternate Functions of Port D” on page 79. 2.3.7 Port E (PE7:PE0) Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port E also serves the functions of various special features of the ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P as listed on ”Alternate Functions of Port E” on page 80. 2.3.8 Port F (PF7:PF0) Port F serves as the analog inputs to the A/D Converter. Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide internal pull-up resistors (selected for each bit). The Port F output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port F pins that are externally pulled low will source current if the pull-up resistors are activated. The Port F pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a reset occurs. Port F also serves the functions of the JTAG interface, see ”Alternate Functions of Port F” on page 82. 2.3.9 Port G (PG5:PG0) Port G is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port G output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port G pins that are externally pulled low will source current if the pull-up resistors are activated. The Port G pins are tri-stated when a reset condition becomes active, even if the clock is not running. 7 8285AS–AVR–10/10 ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P Port G also serves the functions of various special features of the ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P as listed on page 84. 2.3.10 Port H (PH7:PH0) Port H is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port H output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port H pins that are externally pulled low will source current if the pull-up resistors are activated. The Port H pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port H also serves the functions of various ATmega3250A/3250PA/6450A/6450P as listed on page 85. 2.3.11 Port J (PJ6:PJ0) Port J is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port J output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port J pins that are externally pulled low will source current if the pull-up resistors are activated. The Port J pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port J also serves the functions of various ATmega3250A/3250PA/6450A/6450P as listed on page 87. 2.3.12 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 27-13 on page 327. Shorter pulses are not guaranteed to generate a reset. 2.3.13 XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. 2.3.14 XTAL2 Output from the inverting Oscillator amplifier. 2.3.15 AVCC AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. 2.3.16 AREF This is the analog reference pin for the A/D Converter. special features of the special features of the 8 8285AS–AVR–10/10 ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P 3. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 4. Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. 5. About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details. These code examples assume that the part specific header file is included before compilation. For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instructions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR". 9 8285AS–AVR–10/10 ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P 6. Register Summary Note: Address (0xFF) (0xFE) (0xFD) (0xFC) (0xFB) (0xFA) (0xF9) (0xF8) (0xF7) (0xF6) (0xF5) (0xF4) (0xF3) (0xF2) (0xF1) (0xF0) (0xEF) (0xEE) (0xED) (0xEC) (0xEB) (0xEA) (0xE9) (0xE8) (0xE7) (0xE6) (0xE5) (0xE4) (0xE3) (0xE2) (0xE1) (0xE0) (0xDF) (0xDE) (0xDD) (0xDC) (0xDB) (0xDA) (0xD9) (0xD8) (0xD7) (0xD6) (0xD5) (0xD4) (0xD3) (0xD2) (0xD1) (0xD0) (0xCF) (0xCE) (0xCD) (0xCC) (0xCB) (0xCA) (0xC9) (0xC8) (0xC7) (0xC6) (0xC5) Registers with bold type only available in ATmega3250A/3250PA/6450A/6450P. Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PORTJ DDRJ PINJ PORTH DDRH PINH Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved UDR0 UBRR0H Bit 7 - - - - - - - - PORTH7 DDH7 PINH7 - PORTJ6 DDJ6 PINJ6 PORTH6 DDH6 PINH6 - PORTJ5 DDJ5 PINJ5 PORTH5 DDH5 PINH5 - PORTJ4 DDJ4 PINJ4 PORTH4 DDH4 PINH4 - PORTJ3 DDJ3 PINJ3 PORTH3 DDH3 PINH3 - PORTJ2 DDJ2 PINJ2 PORTH2 DDH2 PINH2 - PORTJ1 DDJ1 PINJ1 PORTH1 DDH1 PINH1 - PORTJ0 DDJ0 PINJ0 PORTH0 DDH0 PINH0 193 197 93 93 93 92 93 93 USART0 Data Register USART0 Baud Rate Register High 10 8285AS–AVR–10/10 ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P Address (0xC4) (0xC3) (0xC2) (0xC1) (0xC0) (0xBF) (0xBE) (0xBD) (0xBC) (0xBB) (0xBA) (0xB9) (0xB8) (0xB7) (0xB6) (0xB5) (0xB4) (0xB3) (0xB2) (0xB1) (0xB0) (0xAF) (0xAE) (0xAD) (0xAC) (0xAB) (0xAA) (0xA9) (0xA8) (0xA7) (0xA6) (0xA5) (0xA4) (0xA3) (0xA2) (0xA1) (0xA0) (0x9F) (0x9E) (0x9D) (0x9C) (0x9B) (0x9A) (0x99) (0x98) (0x97) (0x96) (0x95) (0x94) (0x93) (0x92) (0x91) (0x90) (0x8F) (0x8E) (0x8D) (0x8C) (0x8B) (0x8A) (0x89) (0x88) (0x87) (0x86) Name UBRR0L Reserved UCSR0C UCSR0B UCSR0A Reserved Reserved Reserved Reserved Reserved USIDR USISR USICR Reserved ASSR Reserved Reserved OCR2A TCNT2 Reserved TCCR2A Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved OCR1BH OCR1BL OCR1AH OCR1AL ICR1H ICR1L Bit 7 RXCIE0 RXC0 USISIF USISIE - Bit 6 UMSEL0 TXCIE0 TXC0 USIOIF USIOIE - Bit 5 UPM01 UDRIE0 UDRE0 USIPF USIWM1 - Bit 4 UPM00 RXEN0 FE0 USIDC USIWM0 EXCLK - Bit 3 USBS0 TXEN0 DOR0 USICNT3 USICS1 AS2 - Bit 2 UCSZ01 UCSZ02 UPE0 USICNT2 USICS0 TCN2UB - Bit 1 UCSZ00 RXB80 U2X0 USICNT1 USICLK OCR2UB - Bit 0 UCPOL0 TXB80 MPCM0 - Page 197 195 194 193 USART0 Baud Rate Register Low USI Data Register USICNT0 USITC TCR2UB - 206 206 207 157 Timer/Counter 2 Output Compare Register A Timer/Counter2 FOC2A WGM20 COM2A1 COM2A0 WGM21 CS22 CS21 CS20 - 156 156 154 Timer/Counter1 Output Compare Register B High Timer/Counter1 Output Compare Register B Low Timer/Counter1 Output Compare Register A High Timer/Counter1 Output Compare Register A Low Timer/Counter1 Input Capture Register High Timer/Counter1 Input Capture Register Low 134 134 134 134 135 135 11 8285AS–AVR–10/10 ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P Address (0x85) (0x84) (0x83) (0x82) (0x81) (0x80) (0x7F) (0x7E) (0x7D) (0x7C) (0x7B) (0x7A) (0x79) (0x78) (0x77) (0x76) (0x75) (0x74) (0x73) (0x72) (0x71) (0x70) (0x6F) (0x6E) (0x6D) (0x6C) (0x6B) (0x6A) (0x69) (0x68) (0x67) (0x66) (0x65) (0x64) (0x63) (0x62) (0x61) (0x60) 0x3F (0x5F) 0x3E (0x5E) 0x3D (0x5D) 0x3C (0x5C) 0x3B (0x5B) 0x3A (0x5A) 0x39 (0x59) 0x38 (0x58) 0x37 (0x57) 0x36 (0x56) 0x35 (0x55) 0x34 (0x54) 0x33 (0x53) 0x32 (0x52) 0x31 (0x51) 0x30 (0x50) 0x2F (0x4F) 0x2E (0x4E) 0x2D (0x4D) 0x2C (0x4C) 0x2B (0x4B) 0x2A (0x4A) 0x29 (0x49) 0x28 (0x48) 0x27 (0x47) Name TCNT1H TCNT1L Reserved TCCR1C TCCR1B TCCR1A DIDR1 DIDR0 Reserved ADMUX ADCSRB ADCSRA ADCH ADCL Reserved Reserved Reserved Reserved PCMSK3 Reserved Reserved TIMSK2 TIMSK1 TIMSK0 PCMSK2 PCMSK1 PCMSK0 Reserved EICRA Reserved Reserved OSCCAL Reserved PRR Reserved Reserved CLKPR WDTCR SREG SPH SPL Reserved Reserved Reserved Reserved Reserved SPMCSR Reserved MCUCR MCUSR SMCR Reserved OCDR ACSR Reserved SPDR SPSR SPCR GPIOR2 GPIOR1 Reserved Reserved OCR0A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 134 134 Timer/Counter1 High Timer/Counter1 Low – FOC1A ICNC1 COM1A1 – ADC7D – REFS1 – ADEN – FOC1B ICES1 COM1A0 – ADC6D – REFS0 ACME ADSC – – – COM1B1 – ADC5D – ADLAR – ADATE – – WGM13 COM1B0 – ADC4D – MUX4 – ADIF – – WGM12 – – ADC3D – MUX3 – ADIE – – CS12 – – ADC2D – MUX2 ADTS2 ADPS2 – – CS11 WGM11 AIN1D ADC1D – MUX1 ADTS1 ADPS1 – – CS10 WGM10 AIN0D ADC0D – MUX0 ADTS0 ADPS0 133 132 130 213 231 227 231 229 230 230 ADC Data Register High ADC Data Register Low – – – – – – – – – – PCINT23 PCINT15 PCINT7 – – – – – – – – CLKPCE – I – – – – PCINT30 – – – – PCINT22 PCINT14 PCINT6 – – – – – – – – – – T – – – – PCINT29 – – – ICIE1 – PCINT21 PCINT13 PCINT5 – – – – – – – – – – H – – – – PCINT28 – – – – – PCINT20 PCINT12 PCINT4 – – – – – – – – – WDCE S – – – – PCINT27 – – – – – PCINT19 PCINT11 PCINT3 – – – – – PRTIM1 – – CLKPS3 WDE V – – – – PCINT26 – – – OCIE1B – PCINT18 PCINT10 PCINT2 – – – – – PRSPI – – CLKPS2 WDP2 N – – – – PCINT25 – – OCIE2A OCIE1A OCIE0A PCINT17 PCINT9 PCINT1 – ISC01 – – – PSUSART0 – – CLKPS1 WDP1 Z – – – – PCINT24 – – TOIE2 TOIE1 TOIE0 PCINT16 PCINT8 PCINT0 – ISC00 – – 66 157 135 107 67 66 67 64 Oscillator Calibration Register [CAL7:0] – PRADC – – CLKPS0 WDP0 C 37 45 37 53 12 15 15 Stack Pointer High Stack Pointer Low – – – – – SPMIE – JTD – – – IDRD/OCDR7 ACD – SPIF SPIE – – – – – RWWSB – BODS – – – OCDR6 ACBG – WCOL SPE – – – – – – – BODSE – – – OCDR5 ACO – – DORD – – – – – RWWSRE – PUD JTRF – – OCDR4 ACI – – MSTR – – – – – BLBSET – – WDRF SM2 – OCDR3 ACIE – – CPOL – – – – – PGWRT – – BORF SM1 – OCDR2 ACIC – – CPHA – – – – – PGERS – IVSEL EXTRF SM0 – OCDR1 ACIS1 – – SPR1 – – – – – SPMEN – IVCE PORF SE – OCDR0 ACIS0 – 282 61/90/266 53 53 238 212 168 SPI Data Register SPI2X SPR0 167 166 27 27 General Purpose I/O Register General Purpose I/O Register – – – – – – – – – – – – – – – – Timer/Counter0 Output Compare A 107 12 8285AS–AVR–10/10 ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P Address 0x26 (0x46) 0x25 (0x45) 0x24 (0x44) 0x23 (0x43) 0x22 (0x42) 0x21 (0x41) 0x20 (0x40) 0x1F (0x3F) 0x1E (0x3E) 0x1D (0x3D) 0x1C (0x3C) 0x1B (0x3B) 0x1A (0x3A) 0x19 (0x39) 0x18 (0x38) 0x17 (0x37) 0x16 (0x36) 0x15 (0x35) 0x14 (0x34) 0x13 (0x33) 0x12 (0x32) 0x11 (0x31) 0x10 (0x30) 0x0F (0x2F) 0x0E (0x2E) 0x0D (0x2D) 0x0C (0x2C) 0x0B (0x2B) 0x0A (0x2A) 0x09 (0x29) 0x08 (0x28) 0x07 (0x27) 0x06 (0x26) 0x05 (0x25) 0x04 (0x24) 0x03 (0x23) 0x02 (0x22) 0x01 (0x21) 0x00 (0x20) Name TCNT0 Reserved TCCR0A GTCCR EEARH EEARL EEDR EECR GPIOR0 EIMSK EIFR Reserved Reserved Reserved Reserved TIFR2 TIFR1 TIFR0 PORTG DDRG PING PORTF DDRF PINF PORTE DDRE PINE PORTD DDRD PIND PORTC DDRC PINC PORTB DDRB PINB PORTA DDRA PINA Bit 7 – FOC0A TSM – Bit 6 – WGM00 – – Bit 5 – COM0A1 – – Bit 4 – COM0A0 – – Bit 3 – WGM01 – – Bit 2 – CS02 – Bit 1 – CS01 PSR2 Bit 0 – CS00 PSR10 Page 107 105 139/158 26 26 26 Timer/Counter0 EEPROM Address Register High EEPROM Address Register Low EEPROM Data Register – PCIE PCIF3 – – – – – – – – – – PORTF7 DDF7 PINF7 PORTE7 DDE7 PINE7 PORTD7 DDD7 PIND7 PORTC7 DDC7 PINC7 PORTB7 DDB7 PINB7 PORTA7 DDA7 PINA7 – PCIE2 PCIF2 – – – – – – – – – – PORTF6 DDF6 PINF6 PORTE6 DDE6 PINE6 PORTD6 DDD6 PIND6 PORTC6 DDC6 PINC6 PORTB6 DDB6 PINB6 PORTA6 DDA6 PINA6 – PCIE1 PCIF1 – – – – – ICF1 – – – PING5 PORTF5 DDF5 PINF5 PORTE5 DDE5 PINE5 PORTD5 DDD5 PIND5 PORTC5 DDC5 PINC5 PORTB5 DDB5 PINB5 PORTA5 DDA5 PINA5 – PCIE0 PCIF0 – – – – – – – PORTG4 DDG4 PING4 PORTF4 DDF4 PINF4 PORTE4 DDE4 PINE4 PORTD4 DDD4 PIND4 PORTC4 DDC4 PINC4 PORTB4 DDB4 PINB4 PORTA4 DDA4 PINA4 EERIE – – – – – – – – – PORTG3 DDG3 PING3 PORTF3 DDF3 PINF3 PORTE3 DDE3 PINE3 PORTD3 DDD3 PIND3 PORTC3 DDC3 PINC3 PORTB3 DDB3 PINB3 PORTA3 DDA3 PINA3 EEMWE – – – – – – – OCF1B – PORTG2 DDG2 PING2 PORTF2 DDF2 PINF2 PORTE2 DDE2 PINE2 PORTD2 DDD2 PIND2 PORTC2 DDC2 PINC2 PORTB2 DDB2 PINB2 PORTA2 DDA2 PINA2 EEWE – – – – – – OCF2A OCF1A OCF0A PORTG1 DDG1 PING1 PORTF1 DDF1 PINF1 PORTE1 DDE1 PINE1 PORTD1 DDD1 PIND1 PORTC1 DDC1 PINC1 PORTB1 DDB1 PINB1 PORTA1 DDA1 PINA1 EERE INT0 INTF0 – – – – TOV2 TOV1 TOV0 PORTG0 DDG0 PING0 PORTF0 DDF0 PINF0 PORTE0 DDE0 PINE0 PORTD0 DDD0 PIND0 PORTC0 DDC0 PINC0 PORTB0 DDB0 PINB0 PORTA0 DDA0 PINA0 General Purpose I/O Register 27 28 64 65 157 136 139 92 92 92 92 92 92 91 91 92 91 91 91 91 91 91 90 90 90 90 90 90 Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. 13 8285AS–AVR–10/10 ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P 7. Instruction Set Summary Mnemonics ADD ADC ADIW SUB SUBI SBC SBCI SBIW AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER MUL MULS MULSU FMUL FMULS FMULSU RJMP IJMP JMP RCALL ICALL CALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS Rd,Rr Rd,Rr Rd,Rr Rd,K Rr, b Rr, b P, b P, b s, k s, k k k k k k k k k k k k k k k k k k k Operands Rd, Rr Rd, Rr Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd Rd Rd,K Rd,K Rd Rd Rd Rd Rd Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr k Add two Registers Description Rd ← Rd + Rr Operation Flags Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None Z,C Z,C Z,C Z,C Z,C Z,C None None None None None None None I None Z, N,V,C,H Z, N,V,C,H Z, N,V,C,H None None None None None None None None None None None None None None None None None None None None None #Clocks 1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 3 3 3 4 4 4 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 ARITHMETIC AND LOGIC INSTRUCTIONS Add with Carry two Registers Add Immediate to Word Subtract two Registers Subtract Constant from Register Subtract with Carry two Registers Subtract with Carry Constant from Reg. Subtract Immediate from Word Logical AND Registers Logical AND Register and Constant Logical OR Registers Logical OR Register and Constant Exclusive OR Registers One’s Complement Two’s Complement Set Bit(s) in Register Clear Bit(s) in Register Increment Decrement Test for Zero or Minus Clear Register Set Register Multiply Unsigned Multiply Signed Multiply Signed with Unsigned Fractional Multiply Unsigned Fractional Multiply Signed Fractional Multiply Signed with Unsigned Relative Jump Indirect Jump to (Z) Direct Jump Relative Subroutine Call Indirect Call to (Z) Direct Subroutine Call Subroutine Return Interrupt Return Compare, Skip if Equal Compare Compare with Carry Compare Register with Immediate Skip if Bit in Register Cleared Skip if Bit in Register is Set Skip if Bit in I/O Register Cleared Skip if Bit in I/O Register is Set Branch if Status Flag Set Branch if Status Flag Cleared Branch if Equal Branch if Not Equal Branch if Carry Set Branch if Carry Cleared Branch if Same or Higher Branch if Lower Branch if Minus Branch if Plus Branch if Greater or Equal, Signed Branch if Less Than Zero, Signed Branch if Half Carry Flag Set Branch if Half Carry Flag Cleared Branch if T Flag Set Branch if T Flag Cleared Branch if Overflow Flag is Set Rd ← Rd + Rr + C Rdh:Rdl ← Rdh:Rdl + K Rd ← Rd - Rr Rd ← Rd - K Rd ← Rd - Rr - C Rd ← Rd - K - C Rdh:Rdl ← Rdh:Rdl - K Rd ← Rd • Rr Rd ← Rd • K Rd ← Rd v Rr Rd ← Rd v K Rd ← Rd ⊕ Rr Rd ← 0xFF − Rd Rd ← 0x00 − Rd Rd ← Rd v K Rd ← Rd • (0xFF - K) Rd ← Rd + 1 Rd ← Rd − 1 Rd ← Rd • Rd Rd ← Rd ⊕ Rd Rd ← 0xFF R1:R0 ← Rd x Rr R1:R0 ← Rd x Rr R1:R0 ← Rd x Rr R1:R0 ← (Rd x Rr)