ATMEGA6490-16AI

Features • High Performance, Low Power AVR® 8-Bit Microcontroller • Advanced RISC Architecture – 130 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 16 MIPS Throughput at 16 MHz – On-Chip 2-cycle Multiplier High Endurance Non-volatile Memory Segments – In-System Self-programmable Flash Program Memory • 32K Bytes (ATmega329/ATmega3290) • 64K Bytes (ATmega649/ATmega6490) – EEPROM • 1K bytes (ATmega329/ATmega3290) • 2K bytes (ATmega649/ATmega6490) – Internal SRAM • 2K bytes (ATmega329/ATmega3290) • 4K bytes (ATmega649/ATmega6490) – Write/Erase Cycles: 10,000 Flash/ 100,000 EEPROM – Data retention: 20 years at 85°C/100 years at 25°C(1) – Optional Boot Code Section with Independent Lock Bits • In-System Programming by On-chip Boot Program • True Read-While-Write Operation – Programming Lock for Software Security JTAG (IEEE std. 1149.1 compliant) Interface – Boundary-scan Capabilities According to the JTAG Standard – Extensive On-chip Debug Support – Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface Peripheral Features – 4 x 25 Segment LCD Driver (ATmega329/ATmega649) – 4 x 40 Segment LCD Driver (ATmega3290/ATmega6490) – Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode – One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode – Real Time Counter with Separate Oscillator – Four PWM Channels – 8-channel, 10-bit ADC – Programmable Serial USART – Master/Slave SPI Serial Interface – Universal Serial Interface with Start Condition Detector – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator – Interrupt and Wake-up on Pin Change Special Microcontroller Features – Power-on Reset and Programmable Brown-out Detection – Internal Calibrated Oscillator – External and Internal Interrupt Sources – Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and Standby I/O and Packages – 53/68 Programmable I/O Lines – 64-lead TQFP, 64-pad QFN/MLF, and 100-lead TQFP Speed Grade: – ATmega329V/ATmega3290V/ATmega649V/ATmega6490V: – 0 - 4 MHz @ 1.8 - 5.5V, 0 - 8 MHz @ 2.7 - 5.5V – ATmega329/3290/649/6490: – 0 - 8 MHz @ 2.7 - 5.5V, 0 - 16 MHz @ 4.5 - 5.5V Temperature range: – -40°C to 85°C Industrial Ultra-Low Power Consumption – Active Mode: • 1 MHz, 1.8V: 350 µA • 32 kHz, 1.8V: 20 µA (including Oscillator) • 32 kHz, 1.8V: 40 µA (including Oscillator and LCD) – Power-down Mode: • 100 nA at 1.8V • 8-bit Microcontroller with In-System Programmable Flash ATmega329/V ATmega3290/V ATmega649/V ATmega6490/V Preliminary • • • • • • • 1. Pin Configurations Figure 1-1. Pinout ATmega3290/6490 TQFP PH7 (PCINT23/SEG36) PH6 (PCINT22/SEG37) PH5 (PCINT21/SEG38) PH4 (PCINT20/SEG39) PF5 (ADC5/TMS) PF6 (ADC6/TDO) PF4 (ADC4/TCK) PF7 (ADC7/TDI) PA0 (COM0) PA1 (COM1) 77 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 LCDCAP (RXD/PCINT0) PE0 (TXD/PCINT1) PE1 (XCK/AIN0/PCINT2) PE2 (AIN1/PCINT3) PE3 (USCK/SCL/PCINT4) PE4 (DI/SDA/PCINT5) PE5 (DO/PCINT6) PE6 (CLKO/PCINT7) PE7 VCC GND DNC (PCINT24/SEG35) PJ0 (PCINT25/SEG34) PJ1 DNC DNC DNC DNC (SS/PCINT8) PB0 (SCK/PCINT9) PB1 (MOSI/PCINT10) PB2 (MISO/PCINT11) PB3 (OC0A/PCINT12) PB4 (OC1A/PCINT13) PB5 (OC1B/PCINT14) PB6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 76 PA2 (COM2) PF0 (ADC0) PF1 (ADC1) PF2 (ADC2) PF3 (ADC3) AGND AVCC AREF GND DNC DNC DNC DNC DNC VCC 75 74 INDEX CORNER 73 72 71 70 69 68 67 66 65 64 PA3 (COM3) PA4 (SEG0) PA5 (SEG1) PA6 (SEG2) PA7 (SEG3) PG2 (SEG4) PC7 (SEG5) PC6 (SEG6) DNC PH3 (PCINT19/SEG7) PH2 (PCINT18/SEG8) PH1 (PCINT17/SEG9) PH0 (PCINT16/SEG10) DNC DNC DNC DNC PC5 (SEG11) PC4 (SEG12) PC3 (SEG13) PC2 (SEG14) PC1 (SEG15) PC0 (SEG16) PG1 (SEG17) PG0 (SEG18) ATmega3290/6490 63 62 61 60 59 58 57 56 55 54 53 52 51 (TOSC2) XTAL2 (T1/SEG33) PG3 (OC2A/PCINT15) PB7 (T0/SEG32) PG4 (TOSC1) XTAL1 (PCINT26/SEG31) PJ2 (PCINT27/SEG30) PJ3 (PCINT28/SEG29) PJ4 (PCINT29/SEG28) PJ5 (PCINT30/SEG27) PJ6 (ICP1/SEG26) PD0 (INT0/SEG25) PD1 RESET/PG5 DNC GND (SEG24) PD2 (SEG23) PD3 (SEG22) PD4 (SEG21) PD5 (SEG20) PD6 2 ATmega329/3290/649/6490 2552J–AVR–08/07 (SEG19) PD7 DNC DNC DNC VCC ATmega329/3290/649/6490 Figure 1-2. Pinout ATmega329/649 PF5 (ADC5/TMS) PF6 (ADC6/TDO) PF4 (ADC4/TCK) PF7 (ADC7/TDI) PA0 (COM0) PA1 (COM1) 50 61 60 59 58 57 56 55 54 53 52 51 64 63 62 49 PA2 (COM2) PF0 (ADC0) PF1 (ADC1) PF2 (ADC2) PF3 (ADC3) AVCC AREF GND GND VCC LCDCAP (RXD/PCINT0) PE0 (TXD/PCINT1) PE1 (XCK/AIN0/PCINT2) PE2 (AIN1/PCINT3) PE3 (USCK/SCL/PCINT4) PE4 (DI/SDA/PCINT5) PE5 (DO/PCINT6) PE6 (CLKO/PCINT7) PE7 (SS/PCINT8) PB0 (SCK/PCINT9) PB1 (MOSI/PCINT10) PB2 (MISO/PCINT11) PB3 (OC0A/PCINT12) PB4 (OC1A/PCINT13) PB5 (OC1B/PCINT14) PB6 1 2 INDEX CORNER 3 4 5 6 7 8 9 10 11 12 13 14 15 16 22 23 24 25 26 27 28 (OC2A/PCINT15) PB7 17 (T1/SEG24) PG3 18 (T0/SEG23) PG4 19 RESET/PG5 20 VCC 21 29 (SEG17) PD5 30 (SEG16) PD6 31 (SEG15) PD7 32 48 PA3 (COM3) 47 PA4 (SEG0) 46 PA5 (SEG1) 45 PA6 (SEG2) 44 PA7 (SEG3) 43 PG2 (SEG4) 42 PC7 (SEG5) ATmega329/649 41 PC6 (SEG6) 40 PC5 (SEG7) 39 PC4 (SEG8) 38 PC3 (SEG9) 37 PC2 (SEG10) 36 PC1 (SEG11) 35 PC0 (SEG12) 34 PG1 (SEG13) 33 PG0 (SEG14) (INT0/SEG21) PD1 (SEG19) PD3 (TOSC2) XTAL2 (TOSC1) XTAL1 (ICP1/SEG22) PD0 Note: The large center pad underneath the QFN/MLF packages is made of metal and internally connected to GND. It should be soldered or glued to the board to ensure good mechanical stability. If the center pad is left unconnected, the package might loosen from the board. 2. Disclaimer Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized. 3. Overview The ATmega329/3290/649/6490 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega329/3290/649/6490 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. (SEG20) PD2 (SEG18) PD4 GND 3 2552J–AVR–08/07 3.1 Block Diagram Block Diagram Figure 3-1. GND VCC PF0 - PF7 PA0 - PA7 PC0 - PC7 PORTF DRIVERS PORTA DRIVERS PORTC DRIVERS DATA REGISTER PORTF DATA DIR. REG. PORTF DATA REGISTER PORTA DATA DIR. REG. PORTA DATA REGISTER PORTC DATA DIR. REG. PORTC 8-BIT DATA BUS AVCC AGND AREF ADC CALIB. OSC INTERNAL OSCILLATOR OSCILLATOR JTAG TAP PROGRAM COUNTER STACK POINTER WATCHDOG TIMER DATA DIR. REG. PORTH TIMING AND CONTROL LCD CONTROLLER/ DRIVER PORTH DRIVERS ON-CHIP DEBUG PROGRAM FLASH SRAM MCU CONTROL REGISTER PH0 - PH7 DATA REGISTER PORTH BOUNDARYSCAN INSTRUCTION REGISTER GENERAL PURPOSE REGISTERS X Y Z TIMER/ COUNTERS PROGRAMMING LOGIC INSTRUCTION DECODER INTERRUPT UNIT XTAL1 XTAL2 DATA DIR. REG. PORTJ CONTROL LINES ALU EEPROM PORTJ DRIVERS AVR CPU STATUS REGISTER PJ0 - PJ6 DATA REGISTER PORTJ USART UNIVERSAL SERIAL INTERFACE SPI ANALOG COMPARATOR DATA REGISTER PORTE DATA DIR. REG. PORTE DATA REGISTER PORTB DATA DIR. REG. PORTB DATA REGISTER PORTD DATA DIR. REG. PORTD DATA REG. PORTG DATA DIR. REG. PORTG + - PORTE DRIVERS PORTB DRIVERS PORTD DRIVERS PORTG DRIVERS PE0 - PE7 PB0 - PB7 PD0 - PD7 PG0 - PG4 4 ATmega329/3290/649/6490 2552J–AVR–08/07 RESET ATmega329/3290/649/6490 The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATmega329/3290/649/6490 provides the following features: 32/64K bytes of In-System Programmable Flash with Read-While-Write capabilities, 1/2K bytes EEPROM, 2/4K byte SRAM, 54/69 general purpose I/O lines, 32 general purpose working registers, a JTAG interface for Boundary-scan, On-chip Debugging support and programming, a complete On-chip LCD controller with internal contrast control, three flexible Timer/Counters with compare modes, internal and external interrupts, a serial programmable USART, Universal Serial Interface with Start Condition Detector, an 8-channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, an SPI serial port, and five software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or hardware reset. In Power-save mode, the asynchronous timer and the LCD controller continues to run, allowing the user to maintain a timer base and operate the LCD display while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer, LCD controller and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low-power consumption. The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip In-System re-Programmable (ISP) Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, by a conventional non-volatile memory programmer, or by an On-chip Boot program running on the AVR core. The Boot program can use any interface to download the application program in the Application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega329/3290/649/6490 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega329/3290/649/6490 AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits. 5 2552J–AVR–08/07 3.2 Comparison between ATmega329, ATmega3290, ATmega649 and ATmega6490 The ATmega329, ATmega3290, ATmega649, and ATmega6490 differs only in memory sizes, pin count and pinout. Table 3-1 on page 6 summarizes the different configurations for the four devices. Table 3-1. Device ATmega329 ATmega3290 ATmega649 ATmega6490 Configuration Summary Flash 32K bytes 32K bytes 64K bytes 64K bytes EEPROM 1K bytes 1K bytes 2K bytes 2K bytes RAM 2K bytes 2K bytes 4K bytes 4K bytes LCD Segments 4 x 25 4 x 40 4 x 25 4 x 40 General Purpose I/O Pins 54 69 54 69 3.3 Pin Descriptions The following section describes the I/O-pin special functions. 3.3.1 VCC Digital supply voltage. 3.3.2 GND Ground. 3.3.3 Port A (PA7..PA0) Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various special features of the ATmega329/3290/649/6490 as listed on page 67. 3.3.4 Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B has better driving capabilities than the other ports. Port B also serves the functions of various special features of the ATmega329/3290/649/6490 as listed on page 68. 6 ATmega329/3290/649/6490 2552J–AVR–08/07 ATmega329/3290/649/6490 3.3.5 Port C (PC7..PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port C also serves the functions of special features of the ATmega329/3290/649/6490 as listed on page 71. 3.3.6 Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATmega329/3290/649/6490 as listed on page 73. 3.3.7 Port E (PE7..PE0) Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port E also serves the functions of various special features of the ATmega329/3290/649/6490 as listed on page 75. 3.3.8 Port F (PF7..PF0) Port F serves as the analog inputs to the A/D Converter. Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide internal pull-up resistors (selected for each bit). The Port F output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port F pins that are externally pulled low will source current if the pull-up resistors are activated. The Port F pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a reset occurs. Port F also serves the functions of the JTAG interface. 7 2552J–AVR–08/07 3.3.9 Port G (PG5..PG0) Port G is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port G output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port G pins that are externally pulled low will source current if the pull-up resistors are activated. The Port G pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port G also serves the functions of various special features of the ATmega329/3290/649/6490 as listed on page 75. 3.3.10 Port H (PH7..PH0) Port H is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port H output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port H pins that are externally pulled low will source current if the pull-up resistors are activated. The Port H pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port H also serves the functions of various special features of the ATmega3290/6490 as listed on page 75. 3.3.11 Port J (PJ6..PJ0) Port J is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port J output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port J pins that are externally pulled low will source current if the pull-up resistors are activated. The Port J pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port J also serves the functions of various special features of the ATmega3290/6490 as listed on page 75. 3.3.12 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in “System and Reset Characteristics” on page 330. Shorter pulses are not guaranteed to generate a reset. 3.3.13 XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. 3.3.14 XTAL2 Output from the inverting Oscillator amplifier. 3.3.15 AVCC AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. 3.3.16 AREF This is the analog reference pin for the A/D Converter. 8 ATmega329/3290/649/6490 2552J–AVR–08/07 ATmega329/3290/649/6490 3.3.17 LCDCAP An external capacitor (typical > 470 nF) must be connected to the LCDCAP pin as shown in Figure 24-2. This capacitor acts as a reservoir for LCD power (VLCD). A large capacitance reduces ripple on VLCD but increases the time until VLCD reaches its target value. 4. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. Note: 1. 5. Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. 6. About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details. For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. 9 2552J–AVR–08/07 7. AVR CPU Core 7.1 Overview This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. 7.2 Architectural Overview Figure 7-1. Block Diagram of the AVR Architecture Data Bus 8-bit Flash Program Memory Program Counter Status and Control Instruction Register 32 x 8 General Purpose Registrers Interrupt Unit SPI Unit Watchdog Timer Indirect Addressing Instruction Decoder Direct Addressing ALU Control Lines Analog Comparator I/O Module1 Data SRAM I/O Module 2 I/O Module n EEPROM I/O Lines In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable Flash memory. 10 ATmega329/3290/649/6490 2552J–AVR–08/07 ATmega329/3290/649/6490 The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation. Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction. Program Flash memory space is divided in two sections, the Boot Program section and the Application Program section. Both sections have dedicated Lock bits for write and read/write protection. The SPM instruction that writes into the Application Flash memory section must reside in the Boot Program section. During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority. The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the ATmega329/3290/649/6490 has Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used. 7.3 ALU – Arithmetic Logic Unit The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description. 11 2552J–AVR–08/07 7.4 AVR Status Register The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. 7.4.1 SREG – AVR Status Register The AVR Status Register – SREG – is defined as: Bit 0x3F (0x5F) Read/Write Initial Value 7 I R/W 0 6 T R/W 0 5 H R/W 0 4 S R/W 0 3 V R/W 0 2 N R/W 0 1 Z R/W 0 0 C R/W 0 SREG • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference. • Bit 6 – T: Bit Copy Storage The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction. • Bit 5 – H: Half Carry Flag The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful in BCD arithmetic. See the “Instruction Set Description” for detailed information. • Bit 4 – S: Sign Bit, S = N ⊕ V The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See the “Instruction Set Description” for detailed information. • Bit 3 – V: Two’s Complement Overflow Flag The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction Set Description” for detailed information. • Bit 2 – N: Negative Flag The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 1 – Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. 12 ATmega329/3290/649/6490 2552J–AVR–08/07 ATmega329/3290/649/6490 • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. 7.5 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: • • • • One 8-bit output operand and one 8-bit result input Two 8-bit output operands and one 8-bit result input Two 8-bit output operands and one 16-bit result input One 16-bit output operand and one 16-bit result input Figure 7-2 shows the structure of the 32 general purpose working registers in the CPU. Figure 7-2. AVR CPU General Purpose Working Registers 7 R0 R1 R2 … R13 General Purpose Working Registers R14 R15 R16 R17 … R26 R27 R28 R29 R30 R31 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F X-register Low Byte X-register High Byte Y-register Low Byte Y-register High Byte Z-register Low Byte Z-register High Byte 0x0D 0x0E 0x0F 0x10 0x11 0 Addr. 0x00 0x01 0x02 Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions. As shown in Figure 7-2, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file. 13 2552J–AVR–08/07 7.5.1 The X-register, Y-register, and Z-register The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 7-3. Figure 7-3. The X-, Y-, and Z-registers 15 X-register 7 R27 (0x1B) XH 0 7 R26 (0x1A) XL 0 0 15 Y-register 7 R29 (0x1D) 15 Z-register 7 R31 (0x1F) YH 0 7 R28 (0x1C) ZH 0 7 R30 (0x1E) YL 0 0 ZL 0 0 In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 7.6 Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations to lower memory locations. This implies that a Stack PUSH command decreases the Stack Pointer. The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to point above 0x60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when the return address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when data is popped from the Stack with return from subroutine RET or return from interrupt RETI. The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present. Bit 0x3E (0x5E) 0x3D (0x5D) 15 SP15 SP7 7 Read/Write R/W R/W Initial Value 0 0 14 SP14 SP6 6 R/W R/W 0 0 13 SP13 SP5 5 R/W R/W 0 0 12 SP12 SP4 4 R/W R/W 0 0 11 SP11 SP3 3 R/W R/W 0 0 10 SP10 SP2 2 R/W R/W 0 0 9 SP9 SP1 1 R/W R/W 0 0 8 SP8 SP0 0 R/W R/W 0 0 SPH SPL 14 ATmega329/3290/649/6490 2552J–AVR–08/07 ATmega329/3290/649/6490 7.7 Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. Figure 7-4 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. Figure 7-4. The Parallel Instruction Fetches and Instruction Executions T1 T2 T3 T4 clkCPU 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch Figure 7-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. Figure 7-5. Single Cycle ALU Operation T1 T2 T3 T4 clkCPU Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back 7.8 Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt. Depending on the Program Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves software security. See the section “Memory Programming” on page 293 for details. The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 49. The list also determines the priority levels of the different interrupts. The lower the address the higher is the 15 2552J–AVR–08/07 priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL bit in the MCU Control Register (MCUCR). Refer to “Interrupts” on page 49 for more information. The Reset Vector can also be moved to the start of the Boot Flash section by programming the BOOTRST Fuse, see “Boot Loader Support – Read-While-Write Self-Programming” on page 278. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed. There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority. The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software. When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence. Assembly Code Example in r16, SREG cli sbi EECR, EEMWE sbi EECR, EEWE out SREG, r16 ; restore SREG value (I-bit) ; store SREG value ; start EEPROM write ; disable interrupts during timed sequence C Code Example char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ __disable_interrupt(); EECR |= (1