ATR0600

Features • • • • • • Very Low Power Design (≈ 50 mW) Single IF Concept 2-bit ADC on Chip Small QFN Package (28 Pins) Highly Integrated, Few External Components UHF6 Technology Electrostatic sensitive device. Observe precautions for handling. GPS Front-end IC ATR0600 Description With the growing importance of mobile communication, location awareness is a key feature for more and more products and services. Due to its small size and minimal power consumption, the GPS front-end IC ATR0600 is an ideal solution for mobile applications and navigation systems. Figure 1. Block Diagram 96.76 MHz 1575.42 MHz LC-BP VS3 LNA RFIN Preliminary Ant BP NBP BPI NBPI REF VDIG Dig. IF at 4.35 MHz SIGH SAW RFNIN VGA amp BP-Filter SIGL SC 23.104 MHz OR AGCO VCO 1478.6 MHz 64 1 1 4 Power control GC PFD XTO P2 VS1 VS2 VS5 VS7 X XTO NXTO NX P1 23.104 MHz Rev. 4536F–GPS–10/03 Pin Configuration Figure 2. Pinning QFN28 n.c. RFNIN RFIN VS3 P1 P2 n.c. BP NBP BPI NBPI VS1 n.c. n.c. 14 13 12 11 10 9 8 15 16 17 18 19 20 21 22 23 24 25 26 27 28 GC VS2 REF SIGL SIGH VDIG SC 7 6 5 4 3 2 1 X VS5 XTO NXTO VS7 NX AGCO Pin Description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Symbol AGCO NX VS7 NXTO XTO VS5 X n.c. P2 P1 VS3 RFIN RFNIN n.c. BP NBP BPI NBPI VS1 n.c. n.c. GC VS2 REF SIGL SIGH VDIG SC Type O OB P IB IB P OB – I I P IB IB – IB IB IB IB P – – I P O O O P O Function Signal level output Complementary to X ECL - blocks supply Complementary to XTO Quartz input XTO supply Quartz intermediate output Not connected Power-up quartz oscillator Power-up RF part Reference supply RF input 1.575 GHz Complementary to RFIN Not connected Open-collector output of mixer Complementary to BP IF - filter input Complementary to BPI VCO + mixer + VGA supply Not connected Not connected Gain control input Subsampling unit supply Defining low threshold voltage Digital interface subsampled output high threshold voltage refered to REF1 Digital interface subsampled output low threshold voltage refered to REF2 Digital interface supply voltage 1.8 V Digital interface clock output Protection Level ESD3 ESD3 ESD2 ESD3 ESD3 ESD2 ESD3 – ESD3 ESD3 ESD2 ESD3 ESD3 – ESD3 ESD3 ESD3 ESD3 ESD2 – – ESD3 ESD2 ESD3 ESD3 ESD3 ESD2 ESD3 2 ATR0600 [Preliminary] 4536F–GPS–10/03 ATR0600 [Preliminary] Functional Description The specification of GPS receivers for personal mobile applications strongly differs from stand-alone GPS receiver specifications. One reason is the presence of strong blocking signals from mobile transmitters which might cause unacceptable levels of degradation in the carrier-to-noise ratio of a GPS system if not sufficiently suppressed. The other reason is the requirements for very low power consumption. The ATR0600 GPS receiver IC has been especially designed for GPS applications in mobile phones. From this system point of view, it incorporates highest isolation between GPS and cellular antennas, as well as low power consumption. The ATR0600 contains a low-power single IF design and integrates a complete frequency synthesizer. It is fully functional over a supply-voltage range of 2.7 V to 3.3 V and is housed in a 28-pin QLN package. The GPS receiver's input signal is a Direct Sequence Spread Spectrum (DSSS) signal at 1575.42 MHz with a 1.023 Mbps Bi-Phase-Shift-Keying (BPSK) modulated spreading code. As the input signal power at the antenna is approximately -140 dBm, the desired signal is below the thermal noise floor. LNA/Mixer Stage The ATR0600 receives the L1 GPS signal via an external LNA. The LNA bandwidth should be as narrow as possible to avoid interferences from out-of-band signals (especially from those of the 1800 GSM band). Combined with the antenna the LNA provides a first filtering of the GPS signal. The LNA in addition should have a power shutdown feature. The shutdown signal will be generated inside the digital section of the GPS receiver. The output of the LNA drives an external SAW filter, which provides the image rejection for the mixer and the isolation of the 1800-MHz GSM band. The output of the SAW filter drives a highly linear mixer which down-converts the GPS signal to an IF of 97.76 MHz. IF Stage The mixer directly drives an external LC-bandpath filter. In order to provide the ultimate selectivity of the GPS frequency before the A/D conversion of the receiver part, the signal path of the ATR0600 combines an external filter and a second integrated filter. We recommend to design the external filter as a 2-pole filter with quality factor Q > 25. The output of the LC-filter drives an on-chip Variable Gain-Controlled amplifier (VGA) which is combined with an integrated IF-bandpath filter to perform additional filtering of GSM jamming signals. The AGC stage provides the additional gain needed to optimally load the signal range of the following analog/digital converter. The AGC control loop can be selected either on-chip close loop or open loop mode. Connecting the AGC_OUT output directly to the AGC_CNTRL input activates the internal control loop. In that case, the VGA control signal is passed to the VGA via an integrated buffer stage including all necessary filtering (low-pass filter). The external control loop is closed by the baseband IC ATR0620. VGA Amplifier Stage A/D Converter Stage The output of the VGA drives the integrated 1.5-bit analog-to-digital converter stage, which comprises two comparators and two output drivers in order to provide sign and magnitude output bits to the baseband IC ATR0620. The comparator LOW- and HIGHthresholds (in Figure 1 on page 1 for SIGH and SIGL) are adjustable via external resistor. The OR gate closes the internal AGC control loop. The integrated power-control stage is controlled by the baseband IC ATR0620 via P1 and P2. The input signals control the shutdown of the reference crystal oscillator (P2) or the shutdown of the whole RF section (P1). Power Save Setting Stage 3 4536F–GPS–10/03 . Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Supply voltage Input voltage Junction temperature Storage temperature range Symbol VS Vin Tj Tstg Value 3.7 3.7 125 -40 to +125 Unit V V °C °C Thermal Resistance Parameters Junction ambient Symbol RthJA Value 125 Unit K/W Recommended Operating Conditions Parameters Supply voltage Temperature range Input frequency Reference frequency External IF filter (see Figure 13 on page 9) Supply voltage digital interface, pin 27 VDD 1.65 to 2.0 V Symbol VS Temp fin, mixer fref Value 2.7 to 3.3 -40 to +85 1575.42 23.104 Unit V °C MHz MHz Electrical Characteristics No. 1 1.1 Parameters Common Supply current P1 = P2 = VPUon P1 = VPUoff P2 = VPUon P1 = P2 = VPUon 3, 6, 11, 19, 23 6 27 3, 6, 11, 19, 23, 27 1 IS IXTO IDD 18 mA A Test Conditions Pin Symbol Min. Typ. Max. Unit Type* 1.2 1.3 Supply current XTO Supply current digital interface Supply current (power down) 2 250 mA µA A A 1.4 P1 = P2 = VPUOFF IS, pd 20 µA A 1.5 1.6 Total gain Noise figure RFIN, RNIN matched, to 50 W, VGC = 2.2 V G NF 95 6.9 dB dB B C *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 4 ATR0600 [Preliminary] 4536F–GPS–10/03 ATR0600 [Preliminary] Electrical Characteristics (Continued) No. 2 2.1 2.2 3 3.1 3.2 3.3 3.4 3.5 3.6 4 4.1 4.2 5 5.1 5.2 5.3 5.4 5.5 6 6.1 6.2 6.3 Parameters Mixer and 1 IF-filter Output frequency Input impedance VGA and 2nd IF-filter Bandpass center frequency Minimum gain Maximum gain Control-voltage sensitivity Gain-control output cut-off frequency Gain-control output voltage Reference Oscillator XTO phase noise at 100 Hz XTO phase noise at 1 kHz Clock and Data Driver Clock driver frequency Clock output level Clock output level Data output level Data output level Cload = 10 pF Cload = 10 pF Cload = 10 pF Cload = 10 pF 28 28 28 25, 26 25, 26 fclk Vclkhigh Vclklow Vdatahigh Vdatalow 23.104 0.8 ´ VDD 0.2 ´ VDD 0.8 ´ VDD 0.2 ´ VDD MHz V V V V A B, C C C C 28 28 Pn100 Pn1k -80 -100 dBc/Hz dBc/Hz C C fref = 23.104 MHz VGC = 1.0 V VGC = 2.2 V VGC = 2.2 V VGC = 1.0 V Without external load at 50 pF load 1 fin, VGA GVGA, min GVGA, max Nvga, min Nvga, max Fagc_out Vagc_out 1.0 96.76 0 75 6.6 150 100 2.2 MHz dB dB dB/V dB/V kHz V D D D D D B fref = 23.104 MHz fref = 1575 MHz 15, 16 12, 13 fIF Zin, IF 96.76 13 - j80 MHz W B C st Test Conditions Pin Symbol Min. Typ. Max. Unit Type* Power-up, Pins P1 and P2 Power-on voltage level on Power-on voltage level off Power-on delay time 9, 10 9, 10 9, 10 VPUon VPUoff TPUon, off 0.9 0.3 6 V V µs C C C *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 5 4536F–GPS–10/03 Interface Description Figure 3. Clock Interface VDIG 20k SC SC 10p I Chip Maximum load capacitance Figure 4. SIGH Interface VDIG 20k SIGH SIGH 10p I Chip Maximum load cap. Figure 5. SIGL Interface VDIG 20k SIGL SIGL 10p Maximum load cap. I Chip Figure 6. Supply VDIGI Interface VDIG VDIG 1.8V Chip Supply Figure 7. Power Control Interface P1 20k 50k 100k Chip VDD P1 P1 Application 6 ATR0600 [Preliminary] 4536F–GPS–10/03 ATR0600 [Preliminary] Figure 8. Power Control Interface P2 20k 50k 100k Application VDD P2 P2 Chip Figure 9. Automatic Gain-control Interface VCC 32uA I 150k 44k AGCO 50p AGCO 100p GC Chip Chip, connected to AGCO Figure 10. A/D Reference Level-control Interface Ref VCC I Ref Chip Ref Application Select value on test R optional 7 4536F–GPS–10/03 Figure 11. Mixer Input Interface VCC 250uA 2.5k 2.5k RF NRF 2mA Chip RF RFx NRF NRFx Application (Matching) Figure 12. XTO Interface 100k XTO NXTO X 220 220 NX Chip XTO NXTO 47p 47p X 68p Application NX 8 ATR0600 [Preliminary] 4536F–GPS–10/03 ATR0600 [Preliminary] Figure 13. IF-filter Interface BP Imax 2mA BP 220nH 2p 300fF VCC BPI BPI 220nH 2p 60uA VCC NBPI NBPI 2p 60uA 300fF 5p 5p 220nH 68 VCC NBP NBP Imax 2mA 2p 220nH Chip Application (IF-Filter) Figure 14. Mixer Input Impedance at RF-NRF 9 4536F–GPS–10/03 Ordering Information Extended Type Number ATR0600-PJQ Package QFN28 - 5x5 Remarks Taped and reeled Package Information 10 ATR0600 [Preliminary] 4536F–GPS–10/03 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. 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