ATR0620

Features • Utilizes the ARM7TDMI™ ARM® Thumb® Processor Core – High-performance 32-bit RISC Architecture – High-density 16-bit Instruction Set – Embedded ICE (In-circuit Emulation) 128 Kbytes Internal RAM Fully Programmable External Bus Interface (EBI) – Maximum External Address Space of 64 MB – Up to Four Chip Selects – Software Programmable 8-/16-bit External Data Bus 16-channel GPS Correlator – Accuracy: TBD – Time to First Fix: TBD 8-channel Peripheral Data Controller (PDC) 8-level Priority, Individually Maskable, Vectored Interrupt Controller – Three External Interrupts 20 Programmable I/O Lines Three USARTs – Two Dedicated Peripheral Data Controller (PDC) Channels per USART Master/Slave SPI Interface – Two Dedicated Peripheral Data Controller (PDC) Channels – 8- to 16-bit Programmable Data Length – Four External Slave Chip Selects Programmable Watchdog Timer Power Management Controller (PMC) – CPU and Peripherals Can Be Deactivated Individually Clock Manager (CLM) – Geared Master Clock to Reduce Power Consumption – Sleep State with Disabled Master Clock PWM Controller – Two PWM Signals Real Time Clock (RTC) – Time in GPS Format and 15-bit Fractional Part of a Second – Programmable Interrupt – Timer with a 8-bit Fractional Part of a Second and Parallel Load 2.3V to 3.6V or 1.8V Supply Voltage Includes Power Supervisor Battery Backup Memory 9 mm × 9 mm 100-pin BGA Package • • • GPS Baseband Processor ATR0620 Summary • • • • • • • • Preliminary • • • • • • Rev. 4574CS–GPS–05/05 1. Description The GPS baseband processor ATR0620 includes a 16-channel GPS correlator and is based on the ARM7TDMI processor core. This processor has a high-performance 32-bit RISC architecture with a high-density 16-bit instruction set and very low power consumption. In addition, a large number of internally banked registers result in very fast exception handling, making the device ideal for real-time control applications. The ATR0620 has a direct connection to off-chip memory, including flash, through the External Bus Interface (EBI). The ATR0620 is manufactured using Atmel’s high-density CMOS technology. By combining the ARM7TDMI microcontroller core with on-chip SRAM, 16-channel GPS correlator and a wide range of peripheral functions on a monolithic chip, the ATR0620 provides a highly flexible and cost-effective solution for GPS applications. 2 ATR0620 [Preliminary] 4574CS–GPS–05/05 ATR0620 [Preliminary] Figure 1-1. Block Diagram GPS Accelerator nSLEEP CLK32768 RF_ON Power Management Controller SRAM nSHDN P29/GPSMODE10 P27/GPSMODE7 P26/GPSMODE5 P25/GPSMODE3 P24/GPSMODE2 P23/GPSMODE4 P20/TIMEPULSE P19/GPSMODE9 P17/GPSMODE1 P14/GPSMODE0 P13/GPSMODE11 P12/GPSMODE8 P1/GPSMODE6 GPS Correlators RTC PIO2 SIGLO SIGHI PWM Generator Clock Manager (CLM) CLK23 PIO2 Controller APB SPI USART2 Special Function P21/TXD2 P22/RXD2 PIO2 PIO2 Advanced Interrupt Controller P11/EXTINT2 P9/EXTINT0 USART1 P18/TXD1 P31/RXD1 Watchdog Interface to Off-Chip Memory (EBI) EM_A19 EM_A1 EM_DA15 EM_DA0 ARM7TDMI Embedded ICE ASB Power Supply Manager DBG_EN TEST_MODE nTRST TDI TDO TCK TMS JTAG SRAM 128K ROM 288K PDC2 P16/NWD_OVF P30/BOOT_MODE0 P28/EM_A20 P10/EM_A0/NLB P8/PDSR8 P7/NUB/NWR1 P6/NOE/NRD P5/NWE/NWR0 P4/nCS0 P3/nCS1 P2/BOOT_MODE1 USART0 P15/TXD0 P0/RXD0 B R I D G E VBAT18_O VBAT VBAT18_I LDOBAT_IN LDO_OUT LDO_IN LDO_EN nRESET Reset Controller 3 4574CS–GPS–05/05 Table 1-1. Serial Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 Pin Configuration BGA 100 B6 B10 C7 C10 D10 E7 E9 B7 B8 A9 C8 B9 D8 C9 D9 E8 K5 K9 J5 K4 H9 J4 F9 E10 J9 J10 J6 G9 G5 G4 J1 J3 J2 K2 K3 F4 H4 K6 C4 G7 A6 A5 A4 A2 A3 CPGA 144 C8 D13 B10 C15 F13 E15 F15 C9 B11 A14 B12 B13 E13 C14 D15 G14 N9 P14 Q10 Q7 N15 P8 H14 G13 N14 P15 Q11 J13 N8 P7 P2 P6 P4 Q3 N6 N1 N7 N10 B3 L14 B8 A6 A5 C3 C5 Pin Name EM_DA0 EM_DA1 EM_DA2 EM_DA3 EM_DA4 EM_DA5 EM_DA6 EM_DA7 EM_DA8 EM_DA9 EM_DA10 EM_DA11 EM_DA12 EM_DA13 EM_DA14 EM_DA15 P15 P0 P14 P18 P31 P17 SIGHI SIGLO XT_IN XT_OUT nSLEEP CLK23 P30 P2 TMS TCK TDI nTRST TDO TEST_MODE DBG_EN RF_ON nRESET nSHDN EM_A1 EM_A2 EM_A3 EM_A4 EM_A5 Firmware Label (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) TXD0 RXD0 GPSMODE4 TXD1 RXD1 GPSMODE5 (1) (1) (1) (1) (1) (1) BOOT_MODE0 BOOT_MODE1 (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) PIO Bank A I (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) RXD0 SCK0 (1) RXD1 SCK1 (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) O (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) TXD0 (1) SCK0 TXD1 (1) SCK1 (1) (1) (1) (1) (1) (1) NWD_OVF 1PPS (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) I (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) PIO Bank B O (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) MSOUT (1) GPS_MON5 NUB/NWR1 (1) GPS_MON6 (1) (1) (1) (1) (1) (1) GPS_MON0 GPS_MON1 (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) Note: 1. No selection option for PIO. 4 ATR0620 [Preliminary] 4574CS–GPS–05/05 ATR0620 [Preliminary] Table 1-1. Serial Number 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 Pin Configuration (Continued) BGA 100 B5 B4 B2 D4 C2 D6 D7 C3 C1 D5 C6 F8 B3 C5 E5 E6 F7 F6 J7 A1 A10 K1 F10 K10 H1 D1 H3 G8 J8 H7 H6 H5 A7 B1 A8 K7 D2 E4 H10 G2 E1 F1 G3 K8 F2 H8 CPGA 144 B7 A3 B1 F2 F3 A9 C10 C1 E2 A4 C7 H13 C4 C6 Q1 A1 K15 A15 P13 D3 C12 N4 J15 M13 N2 G3 P5 M15 N13 N12 Q13 P9 B9 D2 A13 P12 G1 H2 L13 L3 H3 J2 M3 Q14 K3 M14 Pin Name EM_A6 EM_A7 EM_A8 EM_A9 EM_A10 EM_A11 EM_A12 EM_A13 EM_A14 EM_A15 EM_A16 EM_A17 EM_A18 EM_A19 VDD18_R VDD18_B VDD18_L2 VDD18_L1 VBAT GND_R GND_B GND_T GND_L GND_BAT P24 P25 P23 P26 P9 LDO_EN LDO_OUT P3 (OH) P4 (OH) P5 (OH) P6 (OH) LDO_IN P7 (OH) P10 (OH) P11 P8 P16 P19 P1 LDOBAT_IN P21 P22 Firmware Label (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) GPSMODE8 GPSMODE9 GPSMODE7 GPSMODE10 GPSMODE1 (1) (1) nCS1 nCS0 NWE/NWR0 NOE/NRD (1) NUB/NWR1 EM_A0/NLB EM_A21 OUT (RFU) NWD_OVF GPSMODE6 GPSMODE0 (1) TXD2 RXD2 PIO Bank A I (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) MOSI MISO SCK NSS EXTINT0 (1) (1) (1) (1) (1) (1) (1) (1) (1) EXTINT2 (1) SIGHI2 SIGLO2 (1) (1) (1) RXD2 O (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) MOSI MISO SCK NPCS0 (1) (1) (1) nCS1 nCS0 NWE/NWR0 NOE/NRD (1) NUB/NWR1 EM_A0/NLB (1) AGCOUT0 (1) (1) AGCOUT1 (1) TXD2 (1) I (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) PIO Bank B O (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) GPS_MON2 GPS_MON3 MCLK_OUT GPS_MON4 EM_A0/NLB (1) (1) AGCOUT0 (1) (1) (1) (1) (1) MCLK_OUT EM_A21 GPS_MON10 NWD_OVF EM_A20 GPS_MON7 (1) EM_A22 EM_A23 Note: 1. No selection option for PIO. 5 4574CS–GPS–05/05 Table 1-1. Serial Number 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 Pin Configuration (Continued) BGA 100 H2 E2 G1 E3 F3 G10 G6 F5 D3 (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) CPGA 144 N3 J3 M1 K1 L1 K13 N11 Q15 G2 C13 E3 D14 E1 F14 H1 H15 K2 J14 M2 P1 Q2 B2 A2 B4 B5 Q6 Q8 Q9 P10 P11 Q12 L15 L2 J1 G15 F1 E14 D1 B15 C2 B14 C11 A12 A11 A10 A8 Pin Name P20 P27 P28 P29 P12 P13 VBAT18_O VBAT18_I TOUT1 EM_DA16 EM_DA17 EM_DA18 EM_DA19 EM_DA20 EM_DA21 EM_DA22 EM_DA23 EM_DA24 EM_DA25 EM_DA26 EM_DA27 EM_DA28 EM_DA29 EM_DA30 EM_DA31 TMON0 TMON1 TMON2 TMON3 TMON4 TMON5 TMON6 TMON7 TMON8 TMON9 TMON10 TMON11 TMON12 TMON13 TMON14 TMON15 TMON16 TMON17 TMON18 TMON19 TMON20 Firmware Label 1PPS GPSMODE11 EM_A20 GPSMODE12 GPSMODE2 GPSMODE3 (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) PIO Bank A I SCK2 (1) (1) (1) (1) EXTINT1 (1) (1) APB_SELECT (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) O SCK2 NPCS1 NPCS2 NPCS3 nCS2 nCS3 (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) I (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) PIO Bank B O 1PPS GPS_MON11 EM_A20 MSOUT GPS_MON8 GPS_MON9 (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) Note: 1. No selection option for PIO. 6 ATR0620 [Preliminary] 4574CS–GPS–05/05 ATR0620 [Preliminary] Table 1-1. Serial Number 138 139 140 141 142 143 144 Pin Configuration (Continued) BGA 100 (1) (1) (1) (1) (1) (1) (1) CPGA 144 A7 B6 Q5 Q4 N5 P3 K14 Pin Name TMON21 TMON22 TMON23 TMON24 TMON25 TMON26 POR_VEXT Firmware Label (1) (1) (1) (1) (1) (1) (1) PIO Bank A I (1) (1) (1) (1) (1) (1) (1) O (1) (1) (1) (1) (1) (1) (1) I (1) (1) (1) (1) (1) (1) (1) PIO Bank B O (1) (1) (1) (1) (1) (1) (1) Note: 1. No selection option for PIO. Table 1-2. Pin Description Function Module Name EM_A0 – 23 EM_DA0 – 31 NCS0 – NCS3 NWR0 NWR1 NRD EBI NWE NOE NUB NLB NWAIT BOOT_MODE0 BOOT_MODE1 TXD0-2 USART AIC PWM PMC RXD0-2 SCK0-2 EXTINT0-2 AGCOUT0-1 RF_ON nSleep RTC nSHDN XT_IN XT_OUT SCK SPI MOSI MISO NPCS0-3 WD PIO NWD_OVF PDSR0-31 Type Output I/O I/O I/O I/O I/O I/O I/O I/O Output I/O I/O I/O I/O I/O I/O I/O Output – Output I/O Input Output I/O I/O I/O I/O I/O I/O Active Level – – Low Low Low Low Low Low Low Low Low – – – – – High/Low – – Low Low – – – – – Low – – Comment All valid after reset – – Used in byte write option Used in byte write option Used in byte write option Used in byte select option Used in byte select option Used in byte select option Used in byte write option – PIO-controlled after reset, pull up PIO-controlled after reset, pull down PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset ATR0600 PIO-controlled after reset PIO-controlled after reset OSC OSC PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset Input after reset Address bus Data bus Chip select Lower byte 0 write signal Lower byte 0 write signal Read signal Write enable Output enable Upper byte select (16-bit SRAM) Lower byte select (16-bit SRAM) Wait signal Boot mode input Boot mode input Transmit data output Receive data input External serial clock External interrupt request Automatic gain control – Clear sleep output (AF-LDO) Clear sleep output (1.8LDO) Oscillator input Oscillator output SPI clock Master out slave in Master in slave out Slave select Watchdog timer overflow Programmable I/O port 7 4574CS–GPS–05/05 Table 1-2. Pin Description (Continued) Function Module Name GPSMODE0-12 SIGHI SIGLO GPS SIGHI2 SIGLO2 1PPS MSOUT GPS_MON0-11 TMS TDI JTAG/ ICE TDO TCK NTRST DBG_EN CLOCK RESET CLK23 MCLK_OUT nReset VDD18 POWER GND VBAT18_I LDOBAT_IN LDOBAT VBAT VBAT18_O LDO_IN LDO LDO_OUT LDO_EN TEST_MODE TEST POR_VEXT TMON0-26 Type I/O Input Input Input Input Output Output I/O Input Input Output Input Input Input Input Output Input Power Power IN Power Power Power Out Power Power Input Input Input Output Output Active Level – – – – – – – – – – – – Low – – – Low – – – – – – – – – – – – – Comment PIO-controlled after reset – – – – – – – Pull down Pull down – Pull down Pull down Pull down Schmitt trigger – – – – Backup power In – – Backup power out – – – Production test For POR18 test Debug package – GPS mode – – – – – – GPS monitor Test mode select Test data in Test data out Test clock Test reset input Debug enable Clock input Master clock output Reset input – – – – – – LDO in LDO out LDO enable Test mode select Test input Test monitor output TOUT1/APB_Select Test output 8 ATR0620 [Preliminary] 4574CS–GPS–05/05 ATR0620 [Preliminary] 2. Architecture Overview The ATR0620 architecture consists of two main buses, the Advanced System Bus (ASB) and the Advanced Peripheral Bus (APB). The ASB is designed for maximum performance. It interfaces the processor with the on-chip 32-bit memories and the external memories and devices by means of the External Bus Interface (EBI). The APB is designed for accesses to on-chip peripherals and is optimized for low power consumption. The AMBA bridge provides an interface between the ASB and the APB. An on-chip Peripheral Data Controller (PDC2) transfers data between the on-chip USARTs/SPI and the on- and off-chip memories without processor intervention. Most importantly, the PDC2 removes the processor interrupt handling overhead and significantly reduces the number of clock cycles required for a data transfer. It can transfer up to 64 K continuous bytes without reprogramming the starting address. As a result, the performance of the microcontroller is increased and the power consumption reduced. The ATR0620 peripherals are designed to be easily programmable with a minimum number of instructions. Each peripheral has a 16-Kbyte address space allocated in the upper 3 M bytes of the 4-GB address space. Except for the interrupt controller, the peripheral base address is the lowest address of its memory space. The peripheral register set is composed of control, mode, data, status and interrupt registers. To maximize the efficiency of bit manipulation, frequently-written registers are mapped into three memory locations. The first address is used to set the individual register bits, the second resets the bits and the third address reads the value stored in the register. A bit can be set or reset by writing a one to the corresponding position at the appropriate address. Writing a zero has no effect. Individual bits can thus be modified without having to use costly read-modify-write and complex bit-manipulation instructions. All of the external signals of the on-chip peripherals are under the control of the parallel I/O controller. The PIO2 controller can be programmed to insert an input filter on each pin or generate an interrupt on a signal change. After reset, the user must carefully program the PIO2 controller in order to define which peripheral signals are connected with off-chip logic. The ARM7TDMI processor operates in little-endian mode in the ATR0620 GPS baseband. The processor’s internal architecture and the ARM and Thumb instruction sets are described in the ARM7TDMI data sheet. The memory map and the on-chip peripherals are described in detail in the ATR0620 data sheet. The electrical and mechanical characteristics are also documented in the ATR0620 data sheet. The ARM standard In-Circuit Emulation (ICE) debug interface is supported via the ICE port of the ATR0620. 3. PDC2 The ATR0620 has an 8-channel PDC2 dedicated to the three on-chip USARTs and to the SPI. One PDC2 channel is connected to the receiving channel and one to the transmitting channel of each peripheral. The user interface of a PDC2 channel is integrated in the memory space of each USART channel and in the memory space of the SPI. It contains a 32-bit address pointer register and a 16-bit count register. When the programmed data is transferred, an end-of-transfer interrupt is generated by the corresponding peripheral. See the USART section and the SPI section for more details on PDC2 operation and programming. 9 4574CS–GPS–05/05 4. EBI: External Bus Interface The EBI generates the signals that control the access to the external memory or peripheral devices. The EBI is fully programmable and can address up to 64 bytes. It has four chip selects and a 20-bit address bus. The 16-bit data bus can be configured to interface with 8- or 16-bit external devices. Separate read and write control signals allow for direct memory and peripheral interfacing. The EBI supports different access protocols, allowing single clock cycle memory accesses. The main features are: • External memory mapping • 4 active low chip select lines • 8- or 16-bit data bus • Byte write or byte select lines • User interface for remap function of boot memory • Two different read protocols • Programmable wait state generation • Programmable data float time • Programmable write protection for each memory bank 5. AIC: Advanced Interrupt Controller The ATR0620 has an 8-level priority, individually maskable, vectored interrupt controller. This feature substantially reduces the software and real time overhead in handling internal and external interrupts. The interrupt controller is connected to the NFIQ (fast interrupt request) and the NIRQ (standard interrupt request) inputs of the ARM7TDMI processor. The processor’s NFIQ line can only be asserted by the external fast interrupt request input: FIQ. The NIRQ line can be asserted by the interrupts generated by the on-chip peripherals and the external interrupt request lines: IRQ0 to IRQ3. An 8-level priority encoder allows the customer to define the priority between the different NIRQ interrupt sources. Internal sources are programmed to be level sensitive or edge triggered. External sources can be programmed to be positive or negative edge triggered or high- or lowlevel sensitive. 6. PIO2: Parallel I/O Controller The ATR0620 features 32 programmable I/O lines. The I/O lines are multiplexed with on-chip peripheral I/O signals in order to optimize the use of available package pins. The PIO2 controller provides an internal interrupt signal to the Advanced Interrupt Controller (AIC). 10 ATR0620 [Preliminary] 4574CS–GPS–05/05 ATR0620 [Preliminary] 7. USART2: Universal Synchronous/ Asynchronous Receiver/Transmitter The ATR0620 provides three identical, full-duplex, universal synchronous/asynchronous receiver/transmitters that interface to the APB and are connected to the peripheral data controller. The main features are: • Programmable baud rate generator • Parity, framing and overrun error detection • Line break generation and the detection • Automatic echo, local loopback and remote loopback channel modes • Multi-drop mode: address detection and generation • Interrupt generation • Two dedicated peripheral data controller channels • 5-, 6-, 7-, 8-, and 9-bit character length • Protocol ISO 7816 T = 0 and T = 1 8. SPI: Serial Peripheral Interface The ATR0620 features an SPI, which provides communication with external devices in master or slave mode. The SPI has four external chip selects that can be connected to up to 15 devices. The data length is programmable from 8- to 16-bit. The PDC is used to move data directly between memory and SPI without CPU intervention for maximum real-time processing throughput. 9. WD: Watchdog Timer The ATR0620 features an internal watchdog timer, which can be used to guard against system lock-up if the software becomes trapped in a deadlock. The watchdog timer can be programmed to generate an interrupt or an internal reset. 10. PMC: Power Manager Controller The power management controller allows optimization of power consumption. The PMC enables/disables the clock inputs to most of the peripherals as well as to the ARM processor. When the ARM clock is disabled, the current instruction is processed before the clock is stopped. The clock can be re-enabled by any enabled interrupt or by a hardware reset. When a peripheral clock is disabled, the clock is immediately stopped. When the clock is re-enabled the peripheral resumes action where it left off. Due to the static nature of the design, the contents of the on-chip RAM and registers for which the clocks are disabled remain unchanged. 11. CLM: Clock Manager In addition to the Power Management Controller (PMC) the Clock Manager (CLM) is another possibility to reduce power consumption. The clock manager provides fixed divided clocks for the USARTs, SPI and watchdog timer and generates the master clock which can be divided. The master clock is programmable for frequencies between 175 kHz and 23.1 MHz. 11 4574CS–GPS–05/05 12. SF: Special Function The ATR0620 provides registers that implement the following special functions: • Chip identification • RESET status 13. PWM The PWM includes two PWM channels. They can be programmed separately. It is possible to generate an output voltage range from 0 to (255/256) × VDD18. 14. RTC The RTC provides the time in GPS format. The structure of the GPS system time: zero point is midnight Universal Time (UT) 5th/6th of January 1980. From the zero point weeks, time of week and the 15-bit fractional part of a second are counted. Each week has 604800 seconds (GPS system time does not count leap seconds. Therefore, compared to UT, the GPS time is shifted some seconds). Additional the RTC provides a programmable interrupt (maximum period: one week). 15. GPS Correlator The GPS correlator incorporates 16 GPS channels and provides all the functionality required for sampling, down-converting and correlating GPS signals. The GPS correlator processes GPS signal data to acquire the GPS satellite signals using a model of the satellite codes and multiply/accumulate circuits (correlators) to spread the signal to a bandwidth low enough to detect it above thermal noise. 16. GPS Accelerator The ATR0620 features an accelerator which reduces the time to identify the correct GPS signal. 12 ATR0620 [Preliminary] 4574CS–GPS–05/05 ATR0620 [Preliminary] 17. Ordering Information Extended Type Number ATR0620-100 ATR0620-144 Package CTBGA100 CPGA144 Remarks 9 mm × 9 mm, 0.80 mm pitch Debug package 18. Package Outline CTBGA100 TOP VIEW SIDE VIEW 1.10 ± 0.10 9.00 ± 0.05 0.30 ± 0.05 0.40 Dia. TYP 9.00 ± 0.05 0.60 ± 0.05 BOTTOM VIEW 0.80 ± 0.05 A1 BALL PAD CORNER 10 9 8 7 6 5 4 3 2 1 A B C D E 0.90 ± 0.05 F G H J K 0.90 ± 0.05 0.80 ± 0.05 13 4574CS–GPS–05/05 19. Package CPGA144 TOP VIEW 1.575 ± 0.16 SIDE VIEW 0.090 ± 0.009 0.018 ± 0.002 1.575 ± 0.16 BOTTOM VIEW 1.400 ± 0.012 0.100 TYP A B C D E F G H J K L M N P R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 14 ATR0620 [Preliminary] 4574CS–GPS–05/05 A tmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. 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