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ATR0622-EK1

ATR0622-EK1

  • 厂商:

    ATMEL(爱特梅尔)

  • 封装:

  • 描述:

    ATR0622-EK1 - GPS Baseband Processor - ATMEL Corporation

  • 数据手册
  • 价格&库存
ATR0622-EK1 数据手册
Features • 16 Channel GPS Correlator – 8192 Search Bins with GPS Acquisition Accelerator – Accuracy: 2.5m CEP (Stand-Alone, S/A off) – Time to First Fix: 34s (Cold Start) – Acquisition Sensitivity: –140 dBm – Tracking Sensitivity: –150 dBm Utilizes the ARM7TDMI® ARM® Thumb® Processor Core – High-performance 32-bit RISC Architecture – High-density 16-bit Instruction Set – EmbeddedICE™ (In-circuit Emulator) 128 Kbyte Internal RAM 384 Kbyte Internal ROM, Firmware Version V5.0 Position Technology Provided by u-blox Fully Programmable External Bus Interface (EBI) – Maximum External Address Space of 8 Mbytes – Up to 4 Chip Selects – Software Programmable 8-bit/16-bit External Data Bus 6-channel Peripheral Data Controller (PDC) 8-level Priority, Individually Maskable, Vectored Interrupt Controller – 2 External Interrupts 32 User-programmable I/O Lines 1 USB Device Port – Universal Serial Bus (USB) V2.0 Full-speed Device – Embedded USB V2.0 Full-speed Transceiver – Suspend/Resume Logic – Ping-pong Mode for Isochronous and Bulk Endpoints 2 USARTs – 2 Dedicated Peripheral Data Controller (PDC) Channels per USART Master/Slave SPI Interface – 2 Dedicated Peripheral Data Controller (PDC) Channels – 8-bit to 16-bit Programmable Data Length – 4 External Slave Chip Selects Programmable Watchdog Timer Advanced Power Management Controller (APMC) – Peripherals Can Be Deactivated Individually – Geared Master Clock to Reduce Power Consumption – Sleep State with Disabled Master Clock – Hibernate State with 32.768 kHz Master Clock Real Time Clock (RTC) 2.3V to 3.6V or 1.8V Core Supply Voltage Includes Power Supervisor 1.8V to 3.3V User-definable I/O Voltage for Several GPIOs with 5V Tolerance 4 Kbytes Battery Backup Memory 9 mm × 9 mm 100-pin BGA Package (LFBGA100) RoHS-compliant • • • • • GPS Baseband Processor ATR0621P1 Automotive Summary • • • • • • • • • • • • • • • NOTE: This is a summary document. The complete document is available. For more information, please contact your local Atmel sales office. 4975BS–GPS–05/08 1. Description The GPS baseband processor ATR0621P1 includes a 16-channel GPS correlator and is based on the ARM7TDMI processor core. This processor has a high-performance 32-bit RISC architecture and very low power consumption. In addition, a large number of internally banked registers result in very fast exception handling, making the device ideal for real-time control applications. The ATR0621P1 has two USART and an USB device port. This port is compliant with the Universal Serial Bus (USB) V2.0 full-speed device specification. The ATR0621P1 has a direct connection to off-chip memory, including Flash, through the External Bus Interface (EBI). The ATR0621P1 includes full GPS firmware, licensed from u-blox AG, which performs the basic GPS operation, including tracking, acquisition, navigation and position data output. For normal PVT (Position/Velocity/Time) applications, there is no need for off-chip Flash memory or ROM. The firmware supports e.g. the NMEA® protocol (2.1 and 2.3), a binary protocol for PVT data, configuration and debugging, the RTCM protocol for DGPS, SBAS (WAAS, EGNOS and MSAS) and A-GPS (aiding). It is also possible to store the configuration settings in an optional external EEPROM. The ATR0621P1 is manufactured using the Atmel® high-density CMOS technology. By combining the ARM7TDMI microcontroller core with on-chip SRAM, 16-channel GPS correlator and a wide range of peripheral functions on a monolithic chip, the ATR0621P1 provides a highly-flexible and cost-effective solution for GPS applications. 2 ATR0621P1 4975BS–GPS–05/08 ATR0621P1 Figure 1-1. Block Diagram NSHDN NSLEEP XT_IN XT_OUT GPS Accelerator GPS Correlators Advanced Power Management Controller SRAM RTC RF_ON CLK23 SIGLO0 SIGHI0 SMD Generator P0/NANTSHORT P14/NAADET1 P25/NAADET0 P20/TIMEPULSE P29/GPSMODE12 P27/GPSMODE11 P26/GPSMODE10 P24/GPSMODE8 P23/GPSMODE7 P19/GPSMODE6 P17/GPSMODE5 P13/GPSMODE3 P12/GPSMODE2 P1/GPSMODE0 P9/EXTINT0 P2/BOOT_MODE P30/AGCOUT0 P8/STATUSLED PIO2 Controller APB SPI Timer Counter P15/ANTON USART2 Special Function P21/TXD2 PIO2 P22/RXD2 PIO2 Advanced Interrupt Controller USART1 P18/TXD1 P31/RXD1 USB Transceiver Watchdog EM_A19 EM_A1 EM_DA15 EM_DA0 Interface to Off-Chip Memory (EBI) ASB ARM7TDMI Embedded ICE DBG_EN NTRST TDI TDO TCK TMS JTAG SRAM 128K ROM 384K PDC2 P16/NEEPROM P11/EM_A21 P28/EM_A20 P10/EM_A0/NLB P7/NUB/NWR1 P6/NOE/NRD P5/NWE/NWR0 P4/nCS0 P3/nCS1 USB_DP USB_DM B R I D G E USB Reset Controller Power Supply Manager VBAT18 VBAT LDOBAT_IN LDO_OUT LDO_IN LDO_EN NRESET 3 4975BS–GPS–05/08 2. Architectural Overview 2.1 Description The ATR0621P1 architecture consists of two main buses, the Advanced System Bus (ASB) and the Advanced Peripheral Bus (APB). The ASB is designed for maximum performance. It interfaces the processor with the on-chip 32-bit memories and the external memories and devices by means of the External Bus Interface (EBI). The APB is designed for accesses to on-chip peripherals and is optimized for low power consumption. The AMBA™ Bridge provides an interface between the ASB and the APB. An on-chip Peripheral Data Controller (PDC2) transfers data between the on-chip USARTs/SPI and the on-chip and off-chip memories without processor intervention. Most importantly, the PDC2 removes the processor interrupt handling overhead and significantly reduces the number of clock cycles required for a data transfer. It can transfer up to 64K contiguous bytes without reprogramming the starting address. As a result, the performance of the microcontroller is increased and the power consumption reduced. The ATR0621P1 peripherals are designed to be easily programmable with a minimum number of instructions. Each peripheral has a 16 Kbyte address space allocated in the upper 3 Mbyte of the 4 Gbyte address space. (Except for the interrupt controller, which has 4 Kbyte address space.) The peripheral base address is the lowest address of its memory space. The peripheral register set is composed of control, mode, data, status, and interrupt registers. To maximize the efficiency of bit manipulation, frequently written registers are mapped into three memory locations. The first address is used to set the individual register bits, the second resets the bits, and the third address reads the value stored in the register. A bit can be set or reset by writing a “1” to the corresponding position at the appropriate address. Writing a “0” has no effect. Individual bits can thus be modified without having to use costly read-modify-write and complex bit-manipulation instructions. All of the external signals of the on-chip peripherals are under the control of the Parallel I/O (PIO2) Controller. The PIO2 Controller can be programmed to insert an input filter on each pin or generate an interrupt on a signal change. After reset, the user must carefully program the PIO2 Controller in order to define which peripheral signals are connected with off-chip logic. The ARM7TDMI processor operates in little-endian mode on the ATR0621P1 GPS Baseband. The processor's internal architecture and the ARM and Thumb instruction sets are described in the ARM7TDMI datasheet. The ARM standard In-Circuit Emulation debug interface is supported via the JTAG/ICE port of the ATR0621P1. Features of the ROM firmware are described in software documentation available from u-blox AG, Switzerland. 4 ATR0621P1 4975BS–GPS–05/08 ATR0621P1 3. Pin Configuration 3.1 Pinout Pinout LFBGA100 (Top View) Figure 3-1. A B CDE F GH J K 10 9 8 7 6 5 4 3 2 1 Table 3-1. Pin Name CLK23 DBG_EN EM_A1 EM_A2 EM_A3 EM_A4 EM_A5 EM_A6 EM_A7 EM_A8 EM_A9 EM_A10 EM_A11 EM_A12 EM_A13 EM_A14 EM_A15 Notes: ATR0621P1 ATR0621P1 Pinout LFBGA100 G9 H4 A6 A5 A4 A2 A3 B5 B4 B2 D4 C2 D6 D7 C3 C1 D5 Pin Type IN IN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT PD Pull Resistor (Reset Value)(1) Firmware Label PIO Bank A PIO Bank B 1. PD = internal pull-down resistor, PU = internal pull-up resistor, OH = switched to Output High at reset 2. VBAT18 represent the internal power supply of the backup power domain 3. VDDIO is the supply voltage for the following GPIO pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24, P25, P26, P27 and P29 4. VDD_USB is the supply voltage for the following USB pins: USB_DM and USB_DP. For operation of the USB interface, supply of 3.0V to 3.6V is required. 5. This pin is not connected 5 4975BS–GPS–05/08 Table 3-1. Pin Name EM_A16 EM_A17 EM_A18 EM_A19 EM_DA0 EM_DA1 EM_DA2 EM_DA3 EM_DA4 EM_DA5 EM_DA6 EM_DA7 EM_DA8 EM_DA9 EM_DA10 EM_DA11 EM_DA12 EM_DA13 EM_DA14 EM_DA15 GND GND GND GND LDOBAT_IN LDO_EN LDO_IN LDO_OUT NRESET NSHDN NSLEEP NTRST P0 P1 Notes: ATR0621P1 Pinout (Continued) LFBGA100 C6 F8 B3 C5 B6 B10 C7 C10 D10 E7 E9 B7 B8 A9 C8 B9 D8 C9 D9 E8 A1 A10 K1 K10 K8 H7 K7 H6 C4 G7 J6 K2 K9 G3 Pin Type OUT OUT OUT OUT I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O IN IN IN IN IN IN IN OUT I/O OUT OUT IN I/O I/O PD PD Configurable (PD) NANTSHORT GPSMODE0 AGCOUT1 Open Drain PU PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD Pull Resistor (Reset Value)(1) Firmware Label PIO Bank A PIO Bank B 1. PD = internal pull-down resistor, PU = internal pull-up resistor, OH = switched to Output High at reset 2. VBAT18 represent the internal power supply of the backup power domain 3. VDDIO is the supply voltage for the following GPIO pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24, P25, P26, P27 and P29 4. VDD_USB is the supply voltage for the following USB pins: USB_DM and USB_DP. For operation of the USB interface, supply of 3.0V to 3.6V is required. 5. This pin is not connected 6 ATR0621P1 4975BS–GPS–05/08 ATR0621P1 Table 3-1. Pin Name P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 RF_ON SIGHI0 SIGLO0 TCK Notes: ATR0621P1 Pinout (Continued) LFBGA100 G4 H5 A7 B1 A8 D2 G2 J8 E4 H10 F3 G10 J5 K5 E1 J4 K4 F1 H2 F2 H8 H3 H1 D1 G8 E2 G1 E3 G5 H9 K6 F9 E10 J3 Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O OUT IN IN IN PU Pull Resistor (Reset Value)(1) Configurable (PD) OH OH OH OH OH Configurable (PD) PU to VBAT18 OH OH Configurable (PU) PU to VBAT18 Configurable (PD) PD Configurable (PU) Configurable (PD) Configurable (PU) Configurable (PU) Configurable (PD) Configurable (PU) PU to VBAT18 Configurable (PU) Configurable (PU) Configurable (PD) Configurable (PU) Configurable (PU) OH Configurable (PU) PD PU to VBAT18 PD Firmware Label BOOT_MODE NCS1 NCS0 NWE/NWR0 NOE/NRD NUB/NWR1 STATUSLED EXTINT0 EM_A0/NLB EM_A21 GPSMODE2 GPSMODE3 NAADET1 ANTON NEEPROM GPSMODE5 TXD1 GPSMODE6 TIMEPULSE TXD2 RXD2 GPSMODE7 GPSMODE8 NAADET0 GPSMODE10 GPSMODE11 EM_A20 GPSMODE12 AGCOUT0 RXD1 RXD1 RXD2 SCK MOSI MISO NSS SCK MOSI MISO NPCS0 NPCS1 NCS3 NPCS3 AGCOUT0 “0” EM_A20 MCLK_OUT “0” “0” “0” SIGLO1 SCK2 SCK2 TXD2 SIGHI1 SCK1 SCK1 TXD1 “0” “0” TIMEPULSE “0” NWD_OVF EXTINT1 “0” EXTINT0 EM_A0/NLB NCS2 NPCS2 “0” EM_A21 PIO Bank A “0” NCS1 NCS0 NWE/NWR0 NOE/NRD NUB/NWR1 “0” “0” “0” “0” “0” “0” PIO Bank B 1. PD = internal pull-down resistor, PU = internal pull-up resistor, OH = switched to Output High at reset 2. VBAT18 represent the internal power supply of the backup power domain 3. VDDIO is the supply voltage for the following GPIO pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24, P25, P26, P27 and P29 4. VDD_USB is the supply voltage for the following USB pins: USB_DM and USB_DP. For operation of the USB interface, supply of 3.0V to 3.6V is required. 5. This pin is not connected 7 4975BS–GPS–05/08 Table 3-1. Pin Name TDI TDO TMS USB_DM USB_DP VBAT VBAT18 (2) ATR0621P1 Pinout (Continued) LFBGA100 J2 K3 J1 F10 D3 J7 G6 E6 F7 F6 E5 F5 J9 J10 F4 Pin Type IN OUT IN I/O I/O IN OUT IN IN IN IN IN IN OUT PU Pull Resistor (Reset Value)(1) PU Firmware Label PIO Bank A PIO Bank B VDD18 VDD18 VDD18 VDDIO (3) (4) VDD_USB XT_IN XT_OUT NC(5) Notes: 1. PD = internal pull-down resistor, PU = internal pull-up resistor, OH = switched to Output High at reset 2. VBAT18 represent the internal power supply of the backup power domain 3. VDDIO is the supply voltage for the following GPIO pins: P1, P2, P8, P12, P14, P16, P17, P18, P19, P20, P21, P23, P24, P25, P26, P27 and P29 4. VDD_USB is the supply voltage for the following USB pins: USB_DM and USB_DP. For operation of the USB interface, supply of 3.0V to 3.6V is required. 5. This pin is not connected 8 ATR0621P1 4975BS–GPS–05/08 ATR0621P1 3.2 Signal Description ATR0621P1 Signal Description Name EM_A0 to EM_A21 NCS0 to NCS1 NCS2 to NCS3 NWR0 NWR1 EBI NRD NWE NOE NUB NLB BOOT_MODE TXD1-2 USART RXD1-2 SCK1-2 USB APMC AIC USB_DP USB_DM RF_ON EXTINT0-1 External interrupt request Function External memory address bus Chip select Chip select Lower byte write signal Upper byte write signal Read signal Write enable Output enable Upper byte select (16-bit SRAM) Lower byte select (16-bit SRAM) Boot mode input Transmit data output Receive data input External synchronous serial clock USB data (D+) USB data (D-) Type Output I/O Output Output Output Output Output Output Output Output Output Input Output Input I/O I/O I/O Output Input Active Level Comment – – Low Low Low Low Low Low Low Low Low – – – – – – – High/ Low/ Edge – Low Low – – – – – Low Low – – Interface to ATR0601 PIO-controlled after reset Interface to ATR0601 PIO-controlled after reset Interface to ATR0601 Connect to pin LDO_EN RTC oscillator RTC oscillator PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset Input after reset (except P3 to P7, P10, P11, P28) All valid after reset Internal pull-down resistor Output high in RESET state Output high in RESET state Output high in RESET state Output high in RESET state Output high in RESET state Output high in RESET state Output high in RESET state Output high in RESET state Output high in RESET state PIO-controlled after reset, internal pull-down resistor PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset Table 3-2. Module EM_DA0 to EM_DA15 External memory data bus AGC AGCOUT0-1 NSLEEP Automatic gain control Sleep output Shutdown output Oscillator input Oscillator output SPI clock Master out slave in Master in slave out Slave select Slave select Watchdog timer overflow Programmable I/O port Output Output Output Input Output I/O I/O I/O I/O Output Output I/O RTC NSHDN XT_IN XT_OUT SCK MOSI SPI MISO NSS/NPCS0 NPCS1-3 WD PIO Note: NWD_OVF P0-31 1. The USB transceiver is disabled if VDD_USB < 2.0V. In this case the pins USB_DM and USB_DP are connected to GND (internal pull-down resistors). The USB transceiver is enabled if VDD_USB is within 3.0V and 3.6V. 9 4975BS–GPS–05/08 Table 3-2. Module ATR0621P1 Signal Description (Continued) Name SIGHI0 SIGLO0 Function Digital IF Digital IF Digital IF Digital IF GPS synchronized time pulse GPS mode Status LED Enable EEPROM support Active antenna power on output Active antenna short circuit detection Input Active antenna detection input Test mode select Test data in Test data out Test clock Test reset input Debug enable Clock input Master clock output Reset input Type Input Input Input Input Output Input Output Input Output Input Input Input Input Output Input Input Input Input Output I/O Power Power Power Power Power Power Out LDO in LDO out LDO enable Power Power Input Active Level Comment – – – – – – – Low – Low Low – – – – Low High – – Low – – – – – – – – – – Interface to ATR0601 Interface to ATR0601 PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset Internal pull-up resistor Internal pull-up resistor Output high in RESET state Internal pull-up resistor Internal pull-down resistor Internal pull-down resistor Interface to ATR0601, Schmitt trigger input PIO-controlled after reset Open drain with internal pull-up resistor Core voltage 1.8V Variable I/O voltage 1.65V to 3.6V USB voltage 0 to 2.0V or 3.0Vto 3.6V(1) Ground 2.3V to 3.6V 1.5V to 3.6V 1.8V backup voltage 2.3V to 3.6V 1.8V core voltage, maximum 80 mA GPS SIGHI1 SIGLO1 TIMEPULSE GPSMODE0-12 STATUSLED NEEPROM CONFIG ANTON NANTSHORT NAADET0-1 TMS TDI TDO TCK NTRST DBG_EN JTAG/ICE CLOCK CLK23 MCLK_OUT RESET NRESET VDD18 VDDIO POWER VDD_USB GND LDOBAT_IN LDOBAT VBAT VBAT18 LDO_IN LDO18 LDO_OUT LDO_EN Note: 1. The USB transceiver is disabled if VDD_USB < 2.0V. In this case the pins USB_DM and USB_DP are connected to GND (internal pull-down resistors). The USB transceiver is enabled if VDD_USB is within 3.0V and 3.6V. 10 ATR0621P1 4975BS–GPS–05/08 ATR0621P1 3.3 External Connections for a Working GPS System Example of an External Connection SIGH SIGL SC PuRF PuXTO NC see Table 3-15 NC SIGHI SIGLO CLK23 RF_ON NSLEEP NRESET EM_DA0 - 15 EM_A1 - 19 Figure 3-2. ATR0601 ATR0621P1 P8 P20 USB_DM USB_DP P31 P18 P22 P21 STATUS LED TIMEPULSE Optional USB Optional USART 1 Optional USART 2 see Table 3-15 see Table 3-15 see Table 3-15 see Table 3-15 see Table 3-15 NC NC NC NC NC NC GND +3V (see Power Supply) P0 - 7 P9 - 15 P16 - 17 P19 P23 - 30 TMS TCK TDI NTRST TDO DBG_EN GND NSHDN LDO_EN LDO_OUT VDD18 LDO_IN LDOBAT_IN VBAT18 VBAT XT_IN XT_OUT 32.368 kHz (see RTC) +3V (see Power Supply) VDDIO +3V (see Power Supply) VDD_USB +3V (see Power Supply) GND NC: Not connected 11 4975BS–GPS–05/08 4. Ordering Information Extended Type Number ATR0621P1-7FQY ATR0621P1-7FHW ATR0622-EK1 ATR0622-DK1 Package LFBGA100 LFBGA100 MPQ 2000 2000 1 1 Remarks 9 mm × 9 mm, 0.80 mm pitch, ROM5, RoHS-compliant, automotive type 9 mm × 9 mm, 0.80 mm pitch, ROM5, RoHS-compliant, green, automotive type Evaluation kit/road test kit Development kit including example design information 5. Package LFBGA100 Package: R-LFBGA 100_G Dimensions in mm ∅ 0.08 M ∅ 0.15 M A1 Corner Top View 12345 A B C D E F G H J K 6 7 8 9 10 Bottom View 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K A1 Corner C BA ∅ 0.38 ... 0.48 (100x) 9±0.05 7.2 0.8 0.8 A 7.2 technical drawings according to DIN specifications 0.15 (4x) C B 9±0.05 0.53 ref. C (0.36) 4975BS–GPS–05/08 0.12 C 0.2 C 0.27 ... 0.37 1.4 max Seating plane Drawing-No.: 6.580-5003.01-4 Issue: 2; 27.10.05 Moisture sensitivity level (MSL) = 3 12 ATR0621P1 ATR0621P1 6. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, and not to this document. Revision No. 4975BS-GPS-05/08 History • Table 3-1 “ATR0621P1 Pinout” on page 5: Pin type of pin CLK23 changed. 13 4975BS–GPS–05/08 Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 International Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-en-Yvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Product Contact Web Site www.atmel.com Technical Support gps@atmel.com Sales Contact www.atmel.com/contacts Literature Requests www.atmel.com/literature Disclaimer: T he information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2008 Atmel Corporation . A ll rights reserved. A tmel®, logo and combinations thereof, and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. ARM ®, ARM Powered® logo, ARM7TDMI®, Thumb® a nd others are the registered trademarks or trademarks of ARM Ltd. Other terms and product names may be trademarks of others. 4975BS–GPS–05/08
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