ATR0797

Features • • • • Gain Control in 20-dB Steps Very Low I/Q Amplitude and Phase Errors High Input P1dB Small and Optimized Package for High Reliability and Performance Applications • Infrastructure Digital Communication Systems • GSM/Cellular Transceivers • ISM Band Transceivers Benefits • Fully Integrated Device with Reduced External Component Count 65 - 300 MHz SiGe IF Receiver/ Demodulator ATR0797 Electrostatic sensitive device. Observe precautions for handling. Description The ATR0797 is a multi-purpose demodulator RFIC. The silicon monolithic integrated circuit is designed with Atmel’s advanced SiGe technology. This demodulator is capable of both quadrature demodulation or direct IF output. Features include switchable gain control on a frequency range from 65 MHz to 300 MHz. The device performs a very low amplitude as well as phase error and allows high input P1dB. The ATR0797 targets a variety of system applications for communications including 3G wireless. Figure 1. Block Diagram GC1 5 GC2 4 2 1 BBIP BBIN IFP IFN 8 9 ϕ 16 15 13 12 BBQP BBQN LOP LON Rev. 4665D–SIGE–08/04 Pin Configuration Figure 2. Pinning BBIN BBIP VCC GC2 GC1 GND VCC IFP 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 BBQP BBQN VCC LOP LON GND VCC IFN Pin Description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Symbol BBIN BBIP VCC GC2 GC1 GND VCC IFP IFN VCC GND LON LOP VCC BBQN BBQP Function Baseband I-axis negative output, self biasing Baseband I-axis positive output, self biasing 5 V power supply Gain control input, stage 2, 5 V CMOS levels Gain control input, stage 1, 5 V CMOS levels Ground 5 V power supply IF positive input, self biasing, AC-coupled IF negative input, self biasing, AC-coupled 5 V power supply Ground Local oscillator, negative input, self biasing, AC-coupled Local oscillator, positive input, self biasing, AC-coupled 5 V power supply Baseband Q-axis negative output, self biasing Baseband Q-axis positive output, self biasing 2 ATR0797 4665D–SIGE–08/04 ATR0797 Product Description Atmel’s ATR0797 is a variable gain I-Q demodulator designed for use in receiver IF sections, that are typically existing in superheterodyne RF architectures. The ATR0797 has two gain stages that are independent of each other. These gain stages are broadband differential amplifiers each with a digital control pin to set the gain. Since the amplifiers have approximately the same gain, setting GC1 high and GC2 low results in approximately the same gain as setting GC1 low and GC2 high. Former setting offers better noise figures. The IF input is a differential input that has internal bias circuitry to set the common mode voltage. The use of blocking capacitors to facilitate AC coupling is highly recommended to avoid changing the common mode voltage. Either input may be driven single ended if the other input is connected to ground through an AC short such as a 1000 pF capacitor. This typically results in slightly lower input P1dB. The two matched mixers are configured with the quadrature LO generator to provide inphase and quadrature baseband outputs. The LO and IF ports offer a differential 50 Ω impedance. The passives at these ports (parallel L-R network) and the package itself adds inductance that tends to degrade return loss. The ATR0797 features immunity from changes in LO power. The gain features change by less than 0.6 dB over a 6 dB range of LO power. Also note the excellent I/Q balance, which typically falls within 0.1 dB and 1 degree from 65 MHz to 300 MHz, and varies less than 0.05 dB and 0.5 degree over temperature (-40°C to +85°C). The frequency response of the IF and LO ports is dominated by the L-R network on the input. When de-embedded, the gain and P1dB response is within 0.5 dB from 65 MHz to 300 MHz. The figures in the datasheet illustrate a typical ATR0797’s performance with respect to temperature. Note that these numbers include the effect of the R-L network in the IF port. Evaluation board design and equipment constraints: Please take into account that the evaluation board uses baluns on the I/Q outputs, and these baluns limit the low frequency response of the device. For true baseband operation, the baluns should be removed, and the differential signals used directly. The 27 pF capacitor on the evaluation board is appropriate for lower frequencies. 3 4665D–SIGE–08/04 Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All voltages are referred to GND. Parameters Supply voltage LO input IF input Operating temperature Storage temperature Note: Symbol VCC LOP, LON IFN, IFP TOP Tstg Value 5.5 10 10 -40 to +85 -65 to +150 Unit V dBm V °C °C The device may not survive all maximums applied simultaneously. Thermal Resistance Parameters Junction ambient Symbol RthJA Value 35 Unit K/W Electrical Characteristics Test conditions: VCC = 5 V, Tamb = 25°C, LO input: 0 dBm at 200 MHz IF input: at 200.1 MHz, GC1 = 0, GC2 = 0; 0 dBm IF input: at 200.1 MHz, GC1 = 1, GC2 = 0; -20 dBm IF input: at 200.1 MHz, GC1 = 1, GC2 = 1; -40 dBm No. 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 Notes: Parameters Test Conditions Pin Symbol Min. Typ. 120 220 20 2 32 -29 35 -27 11 12 -8 15 -6 14.5 17 38 Max. Unit Type(1) IF Input (I/Q Mixing to Baseband) Frequency range IF input return loss IF input common mode voltage Gain Input P1dB DSB Noise figure Gain Input P1dB DSB Noise figure Gain set = medium; GC1 = 1; GC2 = 0 or GC1 = 0; GC2 = 1 Gain set = high; GC1 = GC2 = 1 50 Ω nominal differential input(2) Internally generated 8-9 8-9 8, 9 2-1, 16-15 1, 2, 15, 16 2-1, 16-15 2-1, 16-15 1, 2, 15, 16 2-1, 16-15 f RL VCH G P1dB NF G P1dB NF 65 300 MHz dB V dB dBm dB dB dBm dB A C D A C D B D 1. Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 2. The parasitic inductance of the package, the board, and L5, L6 must be matched out at the center frequency with a series capacitor to achieve 20 dB of port match. 3. The parasitic inductance of the package must be matched out to reach 20 dB port match above 100 MHz. 4 ATR0797 4665D–SIGE–08/04 ATR0797 Electrical Characteristics (Continued) Test conditions: VCC = 5 V, Tamb = 25°C, LO input: 0 dBm at 200 MHz IF input: at 200.1 MHz, GC1 = 0, GC2 = 0; 0 dBm IF input: at 200.1 MHz, GC1 = 1, GC2 = 0; -20 dBm IF input: at 200.1 MHz, GC1 = 1, GC2 = 1; -40 dBm No. 1.10 1.11 1.12 2 2.1 2.2 2.3 2.4 2.5 2.6 3 3.1 3.2 3.3 4 4.1 4.2 4.3 4.4 4.5 Notes: Parameters Gain Input P1dB DSB Noise figure I/Q Output I/Q output frequency range I/Q output amplitude error I/Q phase error I/Q output common mode voltage I/Q output differential offset voltage I/Q output return loss LO input LO input level Return loss LO frequency range Miscellaneous Supply voltage Supply current GC1, GC2 logic level low GC1, GC2 logic level high GC1, GC2 input impedance 3, 7, 10, 14 3, 7, 10, 14 4, 5 4, 5 4, 5 VCC ICC VIL VIH Z 0 0.7 × VCC 40 4.75 5 195 0.3 × VCC VCC 5.25 V mA V V kΩ A A D D D 13-12 13-12 13-12 PLO RLLO RLLO 65 -3 0 20 300 +3 dBm dB MHz D D D 50 Ω nominal differential output(3) 1, 2, 15, 16 2-1, 16-15 2-1, 16-15 1, 2, 15, 16 2-1, 16-15 1, 2, 15, 16 Voffset RLI/Q -100 20 fI/Q DC -0.2 -2 2.5 +100 500 +0.2 +2 MHz dB deg V mV dB D A A A A D Gain set = low; GC1 = GC2 = 0 Test Conditions Pin 2-1, 16-15 1, 2, 15, 16 2-1, 16-15 Symbol G P1dB NF Min. -7 12 Typ. -4 14 31 Max. -2 Unit dB dBm dB Type(1) A C D 1. Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 2. The parasitic inductance of the package, the board, and L5, L6 must be matched out at the center frequency with a series capacitor to achieve 20 dB of port match. 3. The parasitic inductance of the package must be matched out to reach 20 dB port match above 100 MHz. 5 4665D–SIGE–08/04 Figure 3. Gain versus Temperature 35 30 25 High Gain Gain (dB) 20 15 10 5 0 -5 -10 -40 -20 0 20 40 60 80 100 Low Gain Med Gain Temperature (°C) Figure 4. Noise Figure versus Temperature 35 Low Gain 30 Noise Figure (dB) 25 20 Med Gain 15 10 High Gain 5 0 -40 -20 0 20 40 60 80 100 Temperature (°C) Figure 5. Amplitude Difference versus LO Frequency 0.4 Amplitude Difference (dB) 0.3 0.2 0.1 0.0 -0.1 -0.2 -0.3 -0.4 0 100 200 300 400 500 600 700 800 LO Frequency (MHz) 6 ATR0797 4665D–SIGE–08/04 ATR0797 Figure 6. Output P1dB versus Temperature 10 Output P1dB (dBm) 9 Low Gain 8 7 High Gain 6 Med Gain 5 -40 -20 0 20 40 60 80 100 Temperature (°C) Figure 7. Output P1dB versus LO Power 10 Output P1dB (dBm) 9 Low Gain 8 7 High Gain 6 Med Gain 5 -4 -3 -2 -1 0 1 2 3 4 Temperature (°C) Figure 8. Phase Difference versus LO Frequency 92.0 Phase Difference (degrees) 91.5 91.0 90.5 90.0 89.5 89.0 0 100 200 300 400 500 600 700 800 LO Frequency (MHz) 7 4665D–SIGE–08/04 Figure 9. Demo Test Board Schematic J2 BBIN C4 J1 BBIP C3 C8 C7 R3 C9 C10 C5 C6 L4 J4 BBQN L2 R4 R5 L3 J3 BBQP VCC R7 GC2 GC1 R8 VCC L1 D1 1 2 3 4 5 6 7 8 L5 C17 16 15 14 13 12 11 10 9 C18 L6 R6 VCC C12 VCC C11 C13 J5 LOin ATR0797 C14 T3 VCC C15 R9 VCC C16 R10 5V L7 C19 H2 VCC T4 J6 IFin Table 1. Bill of Materials Component IF Demodulator SMA end launch connector Transformer Supply bypass capacitor Resistor Capacitor Inductor Capacitor Resistor Capacitor Resistor Inductor Capacitor Reference D1 J1, J2, J3, J4, J5, J6 T3, T4 C19 R7, R8 C11, C12, C16 L1, L2, L3, L4, L7 C13, C14, C17, C18 R3, R4, R5, R6 C3, C4, C5, C6, C7, C8, C9, C10 R9, R10 L5, L6 C15 Würth Elektronik ® Vendor Atmel Johnson Components™ Mini-Circuits® Part Number ATR0797 742-0711-841 TC1-1 Value Size/Package PSSO16 1 µF 1 kΩ 22 pF 74476401 1 µH 68 pF 0Ω 820 pF 51 Ω 10 nH 100 pF 1206 0402 0402 1210 0402 0402 0402 0402 0402 0402 8 ATR0797 4665D–SIGE–08/04 ATR0797 Figure 10. Demo Test Board (Fully Assembled PCB) Figure 11. Recommended Package Footprint 1.25 0.25 0.74 0.4 0.74 3.0 3.0 φ0.33 via 0.7 0.9 6.9 all units are in mm - Indicates metalization - vias connect pad to underlying ground plane Remark: Heatslug must be soldered to GND. In order to avoid soldering problems, plugging of the vias under the heatslug is recommended. Only ground signal traces are allowed directly under the package. 9 4665D–SIGE–08/04 Ordering Information Extended Type Number ATR0797-6CPH Package PSSO16 Remarks Lead free Package Information 10 ATR0797 4665D–SIGE–08/04 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. 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No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. © Atmel Corporation 2004 . A ll rights reserved. A tmel ® a nd combinations thereof are the registered trademarks of Atmel Corporation or its subsidiaries. Johnson Components™ is a trademark of Emerson Electric Co., Mini-Circuits ® i s a registered trademark of Scientific Components, Würth Elektronik ® i s a registered trademark of Adolf Würth GmbH & Co. KG,. Other terms and product names may be the trademarks of others. Printed on recycled paper. 4665D–SIGE–08/04