ATR2731-ILQY

Features • • • • • • • • • • • • • • • • • • • • • • • • • • • • 8.5V Supply Voltage Voltage Regulator for Stable Operating Conditions Microprocessor-controlled Via a Simple Two-wire Bus Two Selectable Addresses Gain-controlled RF Amplifier with Two Inputs, Selectable Via a Simple Two-wire Bus Control Balanced RF Amplifier Inputs Gain-controlled RF Mixer Four-pin Voltage-controlled Oscillator SAW Filter Driver With Differential Low-impedance Output AGC Voltage Generation for RF Section, Available at Charge-pump Output (Can Also Be Used to Control a PIN Diode Attenuator) Gain-controlled IF Amplifier Balanced IF Amplifier Inputs Selectable Gain-controlled IF Mixer Single-ended IF Output AGC Voltage Generation for IF Section, Available at Charge-pump Output Separate Differential Input for the IF AGC Block All AGC Time Constants are Adjustable AGC Thresholds Programmable Via a Simple Two-wire Bus Three AGC Charge Pump Currents Selectable (Zero, Low, High) Reference Oscillator Programmable 9-bit Reference Divider Programmable 15-bit Counter 1:2048 to 1:32767 Effectively Tri-state Phase Detector with Programmable Charge Pump Superior Phase-noise Performance Programmable Deactivation of Tuning Output Three Switching Outputs (Open Collector) Three D/A Converters (Resolution: 8 Bits) Lock Status Indication (Open Collector) DAB One-chip Front End ATR2731 Rev. 4904A–DAB–03/06 1. Description The ATR2731 is a monolithically integrated Digital Audio Broadcasting one-chip front-end circuit manufactured using Atmel’s advanced UHF5S technology. Its functionality covers a gain-controlled RF amplifier with two selectable RF inputs, a gain-controlled RF mixer, a VCO which provides the LO signal for the RF mixers, either directly or after passing a frequency divider, a SAW filter driver, an AGC block for the RF section, a gain-controlled IF amplifier, an IF mixer which can also be bypassed, an AGC block for the IF section, and a fractional-N frequency synthesizer. The frequency synthesizer controls the VCO to synthesize frequencies in the range of 70 MHz to 500 MHz in a 16-kHz raster; within certain limits, the reference divider factor is fully programmable. The lock status of the phase detector is indicated at a special output pin; three switching outputs can be addressed. A reference signal, generated by an on-chip reference oscillator, is available at an output pin. This reference signal is also used to generate the LO signal for the IF mixer, either by doubling the frequency or by using the reference frequency itself. Three D/A converters at a resolution of 8 bits provide a digitally controllable output voltage. The thresholds inside the AGC blocks can be digitally controlled by means of on-chip 4-bit D/A converters. All functions of this IC are controlled via a simple two-wire bus. 2 ATR2731 4904A–DAB–03/06 ATR2731 Figure 1-1. Block Diagram SAW1 SAW2 18 19 IFIN1 24 IFIN2 23 CPIF 28 26 27 IF AGCIN2 IF AGCIN1 SLI WAGC CPRF 16 th1 th3 21 22 VAGC th2 VAGC RFA1 RFA2 RFB1 RFB2 12 13 14 15 29 IFOUT C1VCO B2VCO B1VCO C2VCO 32 33 34 33 20, 25, 38 D/A D/A D/A 10, 11, 17, 30, 31, 36, 37 VCO ÷1/÷2 x1/x2 VS GND 4-bit latch 4-bit latch 4-bit latch 4-bit latch Lock detector 42 43 Reference counter Tristate phase detector Programmable charge pump 41 39 40 PLCK PD VD OSCI OSCO FREF 5 Fractional-N control Programmable 13-bit counter ÷ N/N+1 4-bit latch 3-bit latch 8-bit latch 8-bit latch 8-bit latch 9-bit latch 15-bit latch MUX MUX Simple two-wire interface/control 44 1 2 Switches 3 6 4 D/A 7 D/A 8 D/A 9 ADR SCL SDA SWA SWC SWB CAO CCO CBO 3 4904A–DAB–03/06 2. Pin Configuration Figure 2-1. Pinning SCl SDA SWA SWB FREF SWC CAO CCO CBO 1 2 3 4 5 6 7 8 9 44 ADR 43 OSCO 42 OSCI 41 PLCK 40 VD 39 PD 38 VS 37 GND 36 VCC3 35 C2VC 34 B1VCO 33 B2VCO 32 C1VC 31 GND 30 GND 29 IFOUT 28 CPIF 27 IFAGCIN1 26 IFAGCIN2 25 VC 24 IFIN1 23 IFIN2 GND 10 GND 11 RFA1 12 RFA2 13 RFB1 14 RFB2 15 CPRF 16 GND 17 SAW1 18 SAW2 19 VC 20 SLI 21 WAGC 22 4 ATR2731 4904A–DAB–03/06 ATR2731 Table 2-1. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Pin Description Symbol SCL SDA SWA SWB FREF SWC CAO CCO CBO GND GND RFA1 RFA2 RFB1 RFB2 CPRF GND SAW1 SAW2 VS SLI WAGC IFIN2 IFIN1 VS IFAGCIN2 IFAGCIN1 CPIF IFOUT GND GND C1VC B2VCO B1VCO C2VC GND GND VS PD VD PLCK OSCI OSCO ADR Function Clock (simple two-wire bus) Data (simple two-wire bus) Switching output (open collector) Switching output (open collector) Reference frequency output (for ATR2731) Switching output (open collector) Output of D/A converter A Output of D/A converter B Output of D/A converter C Ground Ground Input 1 of RF amplifier A (differential) Input 2 of RF amplifier A (differential) Input 1 of RF amplifier B (differential) Input 2 of RF amplifier B (differential) Charge-pump output (RF AGC block) Ground SAW driver output 1 (differential) SAW driver output 2 (differential) Supply voltage RF part AGC mode selection (charge-pump current high) AGC mode selection (charge-pump current off) Input 2 of IF amplifier (differential) Input 1 of IF amplifier (differential) Supply voltage IF part Input 2 of IF AGC block (differential) Input 1 of IF AGC block (differential) Charge-pump output (IF AGC block) IF output (single ended) Ground Ground Collector 1 of VCO Base 2 of VCO Base 1 of VCO Collector 2 of VCO Ground Ground Supply voltage PLL Tri-state charge pump output Active filter output Lock-indicating output (open collector) Input of reference oscillator/buffer Output of reference oscillator/buffer Address selection (simple two-wire bus) 5 4904A–DAB–03/06 3. Functional Description The ATR2731 represents a monolithically integrated front-end IC designed for applications in DAB receivers. It covers RF and IF signal processing, the PLL section and also supporting functions such as D/A converters or switching outputs. Two RF input ports offer the possibility of handling various input signals such as a down-converted L-band signal or band II and band III RF signals. The high dynamic range of the RF inputs and the use of a gain-controlled amplifier and a gain-controlled mixer in the RF section offer the possibility of handling even strong RF input signals. The LO signal of the first mixer stage is derived from an on-chip VCO. The VCO frequency is either divided by two or directly fed to the mixer. In this way band II and band III can be covered easily. In the IF section, it can be selected if the first IF signal is down-converted to a second, lower IF or if it is simply amplified to appear at the IF output. If the down-conversion option is chosen, it can be selected if the LO signal of the IF mixer is directly derived from the reference signal of the PLL, or if it is generated by doubling its frequency. The amplifiers in the IF section are gain-controlled in similar fashion to the RF section. The RF and the IF part also contain AGC functional blocks which generate the AGC control voltages. The AGC thresholds can be defined by means of three on-chip 4-bit D/A converters. The frequency of the VCO is locked to a reference frequency by an on-chip fractional-N PLL circuit which guarantees a superior phase-noise performance. The reference frequency is generated by an on-chip crystal oscillator which can also be overdriven by an external signal. Starting from a minimum value, the reference scaling factor is freely programmable. Three switching outputs can be used for various switching tasks on the front-end board. Three 8-bit D/A converters providing an output voltage between 0V and 8.5V are used to improve the tuning voltages of the tuned preselectors which are derived from the tuning voltage of the VCO. 6 ATR2731 4904A–DAB–03/06 ATR2731 4. RF Part 4.1 RF Gain-controlled Amplifier In order to support two different channels, two identical input buffers with balanced inputs (RFA1, RFA2; RFB1, RFB2) are integrated. By setting the two-wire bus bits M0 and M1 (see “Simple Two-wire Bus Functions” on page 12), the active buffer can be selected. The buffers are followed by a gain-controlled amplifier whose output signal is fed to a gain-controlled mixer. The RF amplifiers are capable of handling input signals up to a typical power of –6 dBm without causing third-order intermodulation components stronger than –40 dBc. 4.2 RF Gain-controlled Mixer, VCO and LO Divider The purpose of the RF mixer is to down-convert the incoming signal (band II, band III) to an IF frequency, which is typically 38.912 MHz. This IF signal is fed to an AGC voltage-generation block (which is described in the following section) and an output buffer stage. This driver stage has a low output impedance and is capable of driving a SAW filter directly via its differential output pins SAW1 and SAW2. The mixer's LO signal is generated by a balanced voltage-controlled oscillator whose frequency is stabilized by a fractional-N phase-locked loop. An example circuit of the VCO is shown in Figure 13-6 on page 24. The oscillator's tank is applied to the pins B1VC, C1VC, B2VC and C2VC as shown in the application circuit in Figure 12-1 on page 20. Before the VCO’s signal is fed to the RF mixer, it has to pass an LO divider block where the VCO frequency is divided by either 1 or 2. The setting of this divider is defined by means of the two-wire bus bits M0 and M1 as indicated in “Simple Two-wire Bus Functions” on page 12. This feature offers the possibility of covering both band II and band III by tuning the VCO frequency in the range between 200 MHz to 300 MHz. 4.3 RF AGC Voltage-generation Block In this functional block, the output signal of the RF mixer is amplified, weakly band-pass filtered (transition range: X8 MHz to X80 MHz), rectified and finally low-pass filtered. The voltage derived in this power-measurement process is compared to a voltage threshold (th1) which can be digitally controlled by an on-chip 4-bit D/A converter. The setting of this converter is defined by means of the two-wire bus bits TAi (i = 1, 2, 3, 4). Depending on the result of this comparison, a charge pump feeds a positive or negative current to pin CPRF in order to charge or discharge an external capacitor. The voltage of this external capacitor can be used to control the gain of an external preamplifier or attenuator stage. Furthermore, it is also used to generate the internal control voltages of an RF amplifier and mixer. For this purpose, the voltage at pin CPRF is compared to a voltage threshold (th2) which is also controlled by an on-chip 4-bit D/A converter whose setting is fixed by the two-wire bus bits TBi (i =1, 2, 3, 4). The current of the RF AGC charge pump can be selected using the input pins WAGC and SLI (Table 4-1): Table 4-1. WAGC High Low Low Current of Charge Pump SLI X Low High Charge-pump Current [µA] Off 50 (slow mode) 190 (fast mode) The function can be seen in Figure 13-5 on page 23. 7 4904A–DAB–03/06 5. IF Part 5.1 IF Gain-controlled Amplifier The signal applied to the balanced input pins IFIN1 and IFIN2 is amplified by a gain-controlled IF amplifier. The gain-control signal is generated by an IF AGC voltage-generation block which is described in the next section. To avoid offset problems, the output of the gain-controlled amplifier is fed to an amplifier/mixer combination by AC coupling. 5.2 IF Gain-controlled Amplifier/Mixer Combination Depending on the setting of the two-wire bus bits M2, M3, the output signal of the gain-controlled IF amplifier is either mixed down to a lower, second IF or, after passing an output buffer stage, amplified before it appears at the single-ended output pin IFOUT. If the down-conversion option is chosen, this circuit still offers two possibilities concerning the synthesis of the IF mixer’s LO signal. This LO signal is derived from the PLL's on-chip reference oscillator. By means of the two-wire bus bits M2 and M3, it can be decided whether the reference frequency is doubled before it is given to the mixer's LO port, or if it is used directly. The gain-control voltage of the amplifier/mixer combination is similar to the gain-controlled IF amplifier generated by an internal gain-control circuit. 5.3 IF AGC Voltage-generation Block The purpose of this gain-control circuit in the IF part is to measure the power of the incoming signal at the balanced input pins IFAGCIN1 and IFAGCIN2, to compare it with a certain power level, and to generate a control voltage for the IF gain-controlled amplifiers and mixer. This architecture offers the possibility of ensuring an optimal use of the dynamic range of the A/D converter which transforms the output signal at pin IFOUT from the analog to the digital domain despite possible insertion losses of (anti-aliasing) filters which are arranged in front of the converter. Such a constellation is indicated in the application circuit in Figure 12-1 on page 20. The incoming signal at the balanced input pins IFAGC1 and IFAGC2 passes a power-measurement process similar to that described in “RF AGC Voltage-generation Block” on page 7. For flexibility reasons, no band-pass filtering is implemented. The voltage derived in this process is compared to a voltage threshold (th3) which is defined by an on-chip 4-bit D/A converter. The setting of this converter is defined by the two-wire bus bits TCi (i = 1, 2, 3, 4). Depending on the result of this comparison, a charge pump feeds a positive or negative current to pin CPIF in order to charge or discharge an external capacitor. The current of this charge pump can be selected using the pins WAGC and SLI (Table 5-1): Table 5-1. Current of Charge Pump SLI X Low High Charge-pump Current Off 50 µA (slow mode) 190 µA (fast mode) High Low Low WAGC The function can be seen in Figure 13-6 on page 24. 8 ATR2731 4904A–DAB–03/06 ATR2731 6. PLL Part The purpose of the PLL part is to perform a phase lock of the voltage-controlled RF oscillator to a n o n - c h i p c r y s t a l r e f e r e n c e o sc i l l a t o r . T h i s i s a c h i e v e d b y m e a n s o f a s p e c i a l phase-noise-shaping technique based on the fractional-N principle. It concentrates the phase detector's phase-noise contribution to the spectrum of the controlled VCO at frequency positions where it does not impair the quality of the received DAB signal. A special property of the transmission technique used in DAB is that the phase-noise-weighting function measuring the influence of the LO's phase noise on the phase information of the coded signal in a DAB receiver has zeros; that is, if phase noise is concentrated in the position of such zeros as discrete lines, the DAB signal is not impaired as long as these lines do not exceed a set limit. For DAB mode I, this phase-noise- weighting function is shown in Figure 6-1. Figure 6-1. Phase-noise-weighting Function 1,80 1,60 1,40 1,20 PNWF 1,00 0,80 0,60 0,40 0,20 0,00 0 1000 2000 3000 4000 5000 6000 df/Hz 7000 8000 9000 10000 It is important to realize that this function shows zeros in all distances from the center line which are multiples of the carrier spacing. The technique of concentrating the phase noise in the positions of such zeros is patent protected. 6.1 Reference Oscillator An on-chip crystal oscillator generates the reference signal which is fed to the reference divider. As already described in “IF Gain-controlled Amplifier/Mixer Combination” on page 8, the LO signal for the mixer in the IF section is derived. By applying a crystal to the pins OSCI and OSCO (Figure 13-2 on page 21), this oscillator generates a highly stable reference signal. If an external reference signal is available, the oscillator can be used as an input buffer. In such an application (Figure 13-3 on page 22), the reference signal has to be applied to the pin OSCI and the pin OSCO must be left open. 9 4904A–DAB–03/06 6.2 Reference Divider Starting from a minimum value, the scaling factor SFref of the 9-bit reference divider is freely programmable by means of the two-wire bus bits ri (i = 0, ..., 8) according to SF ref = r ∑i × 2 i If, for example, a frequency raster of 16 kHz is requested, the scaling factor of the reference divider has to be specified in such a way that the division process results in an output frequency which is four times higher than the desired frequency raster; that is, the comparison frequency of the phase detector equals four times the frequency raster. By changing the division ratio of the main divider from N to N+1 in an appropriate way (fractional-N technique), this frequency raster is interpolated to deliver a frequency spacing of 16 kHz. So, effectively, a reference scaling divide factor SF ref,eff = 4 × r ∑i × 2 i is achieved. By setting the two-wire bus bit T, a test signal representing the divided input signal can be monitored at the switching output SWA. 7. Main Divider The main divider consists of a fully programmable 13-bit divider which defines a division ratio N. The applied division ratio is either N or N + 1 according to the control of a special control unit. On average, the scaling factors SF = N + k / 4 can be selected where k = 0, 1, 2 or 3. In this way, VCO frequencies fVCO = 4 × (N + k / 4) × fref / (4 × SFref) can be synthesized starting from a reference frequency fref. If we define SFeff = 4 × N + k and SFref,eff = 4 × SFref (from the previous section), then fVCO = SFeff × fref / SFref,eff, where SFeff is defined by 15 bits. In the following, this circuit is described in terms of SF eff a nd SF ref,eff. SF eff h as to be programmed via the two-wire bus interface. An effective scaling factor from 2048 to 32767 can be selected by means of the two-wire bus bits ni (i = 0, ..., 14) according to SF eff = n ∑i × 2 i By setting the two-wire bus bit T, a test signal representing the divided input signal can be monitored at the switching output SWC. When the supply voltage is switched on, both the reference divider and the programmable divider are kept in RESET state until a complete scaling factor is written onto the chip. Changes in the setting of the programmable divider become active when the corresponding two-wire bus transmission is completed. An internal synchronization procedure ensures that such changes do not become active while the charge pump is sourcing or sinking current at its output pin. This behavior allows a smooth tuning of the output frequency without restricting the controlled VCO's frequency spectrum. 10 ATR2731 4904A–DAB–03/06 ATR2731 7.1 Phase Comparator and Charge Pump The tri-state phase detector causes the charge pump to source or to sink current at the output pin PD depending on the phase relation of its input signals provided by the reference and the main divider respectively. Four different values of this current can be selected by means of the two-wire bus bits I50 and I100. By use of this option, changes of the loop characteristics due to the variation of the VCO gain as a function of the tuning voltage can be reduced. The charge-pump current can be switched off using the two-wire bus bit TRI. A change in the setting of the charge pump current becomes active when the corresponding two-wire bus transmission is completed. As described for the setting of the scaling factor of the programmable divider, an internal synchronization procedure ensures that such changes do not become active while the charge pump is sourcing or sinking current at its output pin. This behavior allows a change in the charge pump current without restricting the controlled VCO's frequency spectrum. A high-gain amplifier (output pin: VD), which is implemented in order to construct a loop filter, as shown in the application circuit, can be switched off by means of the two-wire bus bit OS. An internal lock detector checks if the phase difference of the input signals of the phase detector is smaller than approximately 250 ns in seven subsequent comparisons. If phase lock is detected, the open collector output pin PLCK is set to H (logical value). It should be noted that the output current of this pin must be limited by external circuitry as it is not limited internally. If the two-wire bus bit TRI is set to H, the lock detector function is deactivated and the logical value of the PLCK output is undefined. 7.2 Switching Outputs Three switching outputs controlled by the two-wire bus bits SWA, SWB, and SWC can be used for any switching task on the front-end board. The currents of these outputs are not limited internally. They have to be limited by an external circuit. 7.3 D/A Converters Three D/A converters, A, B, and C, offer the possibility of generating three output voltages at a resolution of 8 bits. These voltages appear at the output pins CAO, CBO, and CCO. The converters are controlled via the two-wire bus interface by means of the control bits CA0, ..., CA7, CB0, ..., CB7 and CC0, ..., CC7, respectively, as shown in Table 8-1 on page 12. The output voltages are defined as V CAO VM = --------- × 128 7 ∑CAj × 2 j=0 7 j V CBO VM = --------- × 128 ∑CBj × 2 j=0 7 j VM V CCO = --------- × 128 ∑CCj × 2 j=0 j where VM = 4.25V nominally. Due to the rail-to-rail outputs of these converters, almost the full voltage range from 0V to 8.5V can be used. A common application of these converters is the digital synthesis of control signals for the tuning of preselectors. The output pins CAO, CBO, and CCO must be blocked externally with capacitors (100 nF) as shown in the application circuit (see Figure 12-1 on page 20). 11 4904A–DAB–03/06 8. Simple Two-wire Bus Interface Via its two-wire bus interface, various functions can be controlled by a microprocessor. These functions are outlined in Table 8-1 on page 12, and in Section 8.1 ”Simple Two-wire Bus Functions” on page 12. The programming information is stored in a set of internal registers. By means of the pin ADR, two different two-wire bus addresses can be selected, as described in “Electrical Characteristics” on page 16. Figure 8-1 on page 14 shows the two-wire bus timing parameters; Figure 8-2 on page 14 shows a typical two-wire bus pulse diagram. Table 8-1. Simple Two-wire Bus Instruction Codes MSB 1 0 X X 0 r7 r3 1 CA7 CB7 1 SWA CC7 1 0 X X 1 r6 r2 0 CA6 CB6 1 SWB CC6 0 X n11 n5 X r5 r1 X CA5 CB5 0 SWC CC5 0 X n10 n4 r8 r4 r0 X CA4 CB4 OS X CC4 0 X n9 n3 TA3 TB3 TC3 X CA3 CB3 T M3 CC3 AS1 n14 n8 n2 TA2 TB2 TC2 X CA2 CB2 TRI M2 CC2 0 n13 n7 n1 TA1 TB1 TC1 X CA1 CB1 I100 M1 CC1 LSB 0 n12 n6 n0 TA0 TB0 TC0 X CA0 CB0 I50 M0 CC0 Description Address A byte 1 A byte 2 A byte 3 B byte 1 B byte 2 B byte 3 C byte 1 C byte 2 C byte 3 D byte 1 D byte 2 D byte 3 8.1 Simple Two-wire Bus Functions AS1 ni ri TAi TBi TCi CAi, CBi, CCi OS T Defines the two-wire bus address Effective scaling factor (SFeff) of the main divider SF eff = Scaling factor (SFref,eff) of the reference divider SFref,eff = 4 × ri 2i Define the setting of a 4-bit D/A converter controlling the threshold, th1, of the RF AGC to adjust the controlled output power Define the setting of a 4-bit D/A converter controlling the threshold, th2, which determines the activation voltage for the internal RF AGC Define the setting of a 4-bit D/A converter controlling the threshold, th3, of the IF AGC to adjust the output power Define the setting of the three D/A converters A, B and C (i = 0, ..., 7) OS = High switches off the tuning output For T = High, reference signals describing the output frequencies of the reference divider and programmable divider are monitored at SWA (reference divider) and SWC (programmable divider). TRI = High switches off the charge pump n ∑i × 2 i TRI 12 ATR2731 4904A–DAB–03/06 ATR2731 I50 and I100 define the charge pump current: Table 8-2. Current of Charge Pump I50 Low High Low High I100 Low Low High High Charge-pump Current (nominal) [µA] 50 100 150 200 Mi defines the operation mode: Table 8-3. M3 Low Low High X X X Note: Mode Selection M2 Low High High X X X M1 X X X Low High High M0 X X X Low Low High Mode fLO,IFMIX = fref fLO,IFMIX = 2 × fref IF mixer switched off RF mixer A active, fLO,RFMIX = fVCO RF mixer B active, fLO,RFMIX = fVCO RF mixer B active, fLO,RFMIX = fVCO / 2 SWα = High switches on the output current (α = A, B, C) 8.2 Simple Two-wire Bus Data Transfer Format: START - ADR - ACK - - STOP The consists of a sequence of A bytes, B bytes, C bytes and D bytes each followed by ACK. A triplet of these bytes (A, B, C or D) must always be completed before a new triplet is started. If no new triplet is started the transmission can be finished before the current triplet is finished. Examples: START - ADR - ACK - DB1 - ACK - DB2 - ACK - DB3 - ACK - CB1 - ACK - CB2 - ACK - CB3 ACK - AB1 - ACK - AB2 - ACK - AB3 - ACK - BB1 - ACK - BB2 - ACK - BB3 - ACK - STOP START - ADR - ACK - CB1 - ACK - CB2 - ACK - STOP However: START - ADR - ACK - DB1 - ACK - CB1 - ACK - STOP is not allowed. Description: START STOP ACK ADR αBi Start condition Stop condition Acknowledge Address byte α byte i (α = A, B, C, D; i = 1, 2, 3) 13 4904A–DAB–03/06 8.3 Simple Two-wire Bus Timing The values of the periods shown are specified in the table “Electrical Characteristics” on page 16. Please note, that according to the two-wire bus specification, the MSB of a byte is transmitted first, the LSB last. Figure 8-1. Two-wire Bus Timing Stop Start Start Stop SDA tbuf tr tr thdstat SCL thdsta tlow thddat thigh tsudat tsusta tsustp Figure 8-2. Typical Pulse Diagram START SDA SCL ADDRESS BYTE ACK A BYTE 1 ACK A BYTE 2 ACK A BYTE 3 ACK C BYTE 1 ACK C BYTE 2 ACK STOP SDA SCL 14 ATR2731 4904A–DAB–03/06 ATR2731 9. Absolute Maximum Ratings Parameters Supply voltage Junction temperature Storage temperature Differential input RF amplifier, pins 12 and 13 Pins 14 and 15 Externally applied voltage at RF charge pump output, pin 16 Pin 28 WAGC input voltage, pin 22 SLI input voltage, pin 21 Differential base input VCO, pins 33 and 34 Differential input IF amplifier, pins 23 and 24 Differential input IF AGC block, pins 26 and 27 Reference input voltage (AC), pin 42 Two-wire bus input/output voltage, pins 1 and 2 SDA output current, pin 2 Address select voltage, pin 44 Switch output voltage; pins 3, 4 and 6 Switch output current PLCK output voltage, pin 41 PLCK output current, pin 41 Symbol VS Tj Tstg VRFA1,2 VRFB1,2 VCPRF VCPIF VWAGC VSLI VBiVC VIFIN VIFAGCIN VOSCI SCL, SDA SDA ADR SWα SWα PLCK PLCK –0.3 –0.3 –0.3 –0.3 0.5 0.5 –0.3 –0.3 –40 Min. –0.3 Max. +9.5 150 +150 500 500 6.75 6.25 5.5 5.5 500 500 500 1 5.5 5 5.5 9.5 4 5.5 0.5 Unit V °C °C mVrms mVrms V V V V mVrms mVrms mVrms Vpp V mA V V mA V mA 10. Thermal Resistance Parameters Junction ambient (soldered on application board) Symbol RthJA Value 40 Unit K/W 11. Operating Range Parameters Supply voltage Ambient temperature range Symbol VS Tamb Value 8.0 to 9.35 –40 to +85 Unit V °C 15 4904A–DAB–03/06 12. Electrical Characteristics Test conditions (unless otherwise specified): VS = 8.5V, Tamb = 25°C No. Parameters 1 1.1 Overall Characteristics Supply voltage V(CPRF) = V(CPIF) < 0.8V M3 = M2 = High M1 = M0 = Low TAi = TCi = 0000; TBi = 1000 Minimum supply current SWA = SWB = SWC = Low TRI = Low; PLCK = Low I100 = I50 = Low; V(ADR) = Open SLI = Low; WAGC = High 3.4V < V(CPRF) = V(CPIF) < 3.6V; M3 = M2 = High M1 = M0 = Low TAi = TCi = 0000; TBi = 1000 SWA = Low; SWB = Low SWC = Low; TRI = Low PLCK = Low; I100 = I50 = Low V(ADR) = Open; SLI = Low WAGC = High RFA1, RFA2; RFB1, RFB2) → SAW1, SAW2 (see Figure 13-3 on page 22) RFA1, (RFB1) →SAW1, SAW2; RFA2, RFB2 blocked Test Conditions Pin 20, 25, 38 VS 8.0 8.5 9.35 V Symbol Min. Typ. Max. Unit Type* 1.2 IS,min 74 mA B 1.3 Maximum supply current IS,max 79 mA B 2 2.1 2.2 2.3 RF Part Voltage gain AGC range RF Noise figure (double side band) Maximum input power level 12 (14) →19 NFDSB,RF 12 (14) →18, 19 GV,RF 20 23 24 27 12 26 29 dB dB dB A A D 2.4 Differential, 3rd order intermodulation distance ≥ 40 dBc, 12, 13 Pout = –19 dBm, TAi = 0000, (14, 15) RL (SAW1, SAW2) = 200Ω 12, 13 (14, 15) Single ended 12 (14) 18, 19 Pin,max,MIX –10 dBm A 2.5 2.6 2.7 Input frequency range Input impedance Output frequency range for AGC-voltage generation Output power, differential; Maximum output power RL (SAW1, SAW2) > 200Ω, level TAi = 0000 AGC threshold (th1) TAi = 1000 TAi = 1111 TAi = 0000 Output power, differential controlled by two-wire bus bits TAi; RL (SAW1, SAW2) = 200Ω fin,RF Zin,RF fout,SAW 70 1.3 38,912 ±5 260 MHz kΩ MHz B D D 2.8 18, 19 –7 dBm D 2.9 18, 19 pTH,RF 50 90 160 10 120 mVrms A B B *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. The phase detector’s phase-noise contribution to the VCO’s frequency spectrum is determined by the operating frequency of the phase detector divided by 4 according to the fractional-N technique (typically: 16 kHz). 16 ATR2731 4904A–DAB–03/06 ATR2731 12. Electrical Characteristics (Continued) Test conditions (unless otherwise specified): VS = 8.5V, Tamb = 25°C No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* AGC threshold (th2) (internal AGC) Controlled by two-wire bus bits TBi; 2.10 upper limit (TBi = 1111) PIN,MAX = –25 dBm lower limit (TBi = 0000) 2.11 Output impedance 3 3.1 3.2 4 VCO Phase noise Phase noise IF Part IFIN2 blocked (see Figure 13-3 on page 22) fLO,IFMIX = fref or FLO,IFMIX = 2 × fref IFIN2 blocked (see Figure 13-3 on page 22) IF mixer switched off 24 →29 ∆f = 10 kHz L(f) fLO 100 –88 400 dBc/Hz MHz D D Single ended; f(SAW1) = 39 MHz 16 Vint AGC,RF 1.0 Zout,SAW 5.1 1.5 30 1.8 V V Ω B A 18 (19) 4.1 Voltage gain GV,tot 42 44 48 dB A 4.2 4.3 4.4 Voltage gain AGC range IF Noise figure (double side band) 24 →29 GV,tot 45 42 47 44 11 51 48 dB dB dB A A D IFIN2 blocked IFIN2 blocked, 3rd order intermodulation distance ≥ 40 dBc; RL(IFOUT) = 1 k; TCi = 0000; R10 = 4.7 k, R11 = 1.8 k 24 →29 NFDSB 4.5 Maximum input power level 24 Pin,max –20 dBm C 4.6 4.7 4.8 Input frequency range Input impedance IFIN2 blocked, fIF,IFIN = 38.912 MHz 23, 24 23, 24 29 fin,IFIN Zin,IFIN fout,IFO Zout,IFOUT 10 600 – j1000 1 20 + j50 65 + j35 58 – j25 60 MHz Ω D D D Output frequency range Single ended Single ended fout,IFO (3 MHz) fout,IFO (20 MHz) fout,IFO (38.9 MHz) VWAGC = Low VSLI = High 45 MHz Ω Ω Ω 4.9 Output impedance 29 D 5 5.1 5.2 5.3 5.4 5.5 RF AGC Unit Positive charge pump current, fast mode 16 16 16 16 ICPRFPOS,FM 145 180 –180 40 –40 0.75 220 –145 52 –30 µA µA µA µA V A A A A C Negative charge pump VWAGC = Low VSLI = High current, fast mode Positive charge pump current, slow mode VWAGC = Low VSLI = Low ICPRFNEG,FM –220 ICPRFPOS,SM ICPRFNEG,FM VAGCmin 30 –52 Negative charge pump VWAGC = Low current, fast mode VSLI = Low Minimum gain control voltage *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. The phase detector’s phase-noise contribution to the VCO’s frequency spectrum is determined by the operating frequency of the phase detector divided by 4 according to the fractional-N technique (typically: 16 kHz). 17 4904A–DAB–03/06 12. Electrical Characteristics (Continued) Test conditions (unless otherwise specified): VS = 8.5V, Tamb = 25°C No. Parameters 5.6 6 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 7 7.1 Maximum gain control voltage IF AGC Unit Positive charge pump current, fast mode VWAGC = Low VSLI = High 28 28 28 28 28 28 28 WAGC = High WAGC = Low SLI = High SLI = Low 22 22 21 21 ICPIFPOS,FM ICPIFNEG, FM ICPIFPOS, SM ICPIFNEG, SM ICPIFWAGC VAGCIFmin VAGCIFmax VWAGCHigh VWAGCLow VSLIHigh VSLILow 2.0 0.7 2.0 0.7 145 –220 30 –52 –4 180 –180 40 –40 0 0.75 5.9 220 –145 52 –30 +4 µA µA µA µA µA V V V V V A A A A A C C A A A A Test Conditions Pin Symbol VAGCmax Min. Typ. 6.6 Max. Unit V Type* C Negative charge pump VWAGC = Low VSLI = High current, fast mode Positive charge pump current, slow mode VWAGC = Low VSLI = Low Negative charge pump VWAGC = Low current, slow mode VSLI = Low Window AGC mode charge pump current Minimum gain control voltage Maximum gain control voltage Control voltage for activated WAGC Control voltage for deactivated WAGC Control voltage for activated SLI Control voltage for deactivated SLI PLL Part Effective scaling factor of programmable divider Effective scaling factor of reference divider Tuning step REF Input Input frequency range Input sensitivity Maximum input signal Input impedance REF Output Output voltage 1.5 kΩ || 2.5 pF load Internal oscillator overdriven Internal oscillator overdriven Internal oscillator overdriven Single ended VWAGC = High SFeff SFref,eff 2048 32766 D 7.2 7.3 8 8.1 8.2 8.3 8.4 9 9.1 144 16 2047 kHz 30 50 MHz mVrms mVrms 2 || 2.5 kΩ/pF mVrms D D B A D D A 42 fref vref,min vref,max Zref 5 vout,ref 65 100 300 5 *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. The phase detector’s phase-noise contribution to the VCO’s frequency spectrum is determined by the operating frequency of the phase detector divided by 4 according to the fractional-N technique (typically: 16 kHz). 18 ATR2731 4904A–DAB–03/06 ATR2731 12. Electrical Characteristics (Continued) Test conditions (unless otherwise specified): VS = 8.5V, Tamb = 25°C No. Parameters 10 10.1 10.2 10.3 10.4 10.5 High impedance mode Charge-pump current Phase Detector I100 = High, I50 = High I100 = High, I50 = Low I100 = Low, I50 = High I100 = Low, I50 = Low TRI = High Test Conditions Pin 39 I PD4 I PD3 I PD2 I PD1 IPD,tri LPD 41 VPLCK = 5.5V IPLCK = 0.25 mA 3, 4, 6 ISW,L ISW = 0.25 mA 44 0 0.4 VS 7, 8, 9 Cα7 = High Cα0 to Cα6 = Low α = A, B, C VS = 8.00V to 9.35V Tamb = –40 to +85° C VCαn–n VM / 128 n = 24 ... 232, α = A, B, C VM ∆VM,VS ∆VM,temp ∆VCαn ICAOmax ICBOmax ICCOmax 1, 2 3 5.5 1.5 0.4 0.1 tr tf tbuf thigh 4.7 4 100 1 300 V V V kHz µs µs µs µs D D D D D D D D –70 4.05 –50 ±20 70 4.25 4.45 50 V mV mV mV A A C A 0.1 VS 0.6 VS C C VSW,sat 10 0.5 µA V A A IPLCK,L VPLCK,sat 10 0.5 µA V A A 160 120 80 35 –100 –159 200 150 100 50 240 180 120 65 100 µA µA µA µA nA dBc/ Hz A A A A A C Symbol Min. Typ. Max. Unit Type* 10.6 Effective phase noise(1) IPD = 203 mA 11 Lock indication 11.1 Leakage current 11.2 Saturation voltage 12 Switches 12.1 Leakage current 12.2 Saturation voltage 13 Address selection 13.1 AS1 = 0 13.2 AS1 = 1 14 D/A Converters 14.1 Output voltage 14.2 Variation of VM 14.3 Variation of VM 14.4 Accuracy Maximum output current Simple two-wire Bus 14.5 15 20 µA C 15.1 Input voltage SCL/SDA High 15.2 Input voltage SCL/SDA Low 15.3 Output voltage SDA (open collector) ISDA = 2 mA, SDA = Low 15.4 SCL clock frequency 15.5 Rise time (SCL, SDA) 15.6 Fall time (SCL; SDA) 15.7 Time before new transmission can start 15.8 SCL high period *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. The phase detector’s phase-noise contribution to the VCO’s frequency spectrum is determined by the operating frequency of the phase detector divided by 4 according to the fractional-N technique (typically: 16 kHz). 19 4904A–DAB–03/06 12. Electrical Characteristics (Continued) Test conditions (unless otherwise specified): VS = 8.5V, Tamb = 25°C No. Parameters 15.9 SCL low period 15.10 Hold time START 15.11 Setup time START 15.12 Setup time STOP 15.13 Hold time DATA 15.14 Setup time DATA Test Conditions Pin Symbol tlow thdsta tsusta tsustp thddat tsudat Min. 4.7 4 4.7 4.7 0 250 Typ. Max. Unit µs µs µs µs µs ns Type* D D D D D D *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. The phase detector’s phase-noise contribution to the VCO’s frequency spectrum is determined by the operating frequency of the phase detector divided by 4 according to the fractional-N technique (typically: 16 kHz). Figure 12-1. Application Circuit 8.5V 51k Microcontroller 33k BC846B 22k 2.2k 33k Miro crystal 16.384 MHz CXAT-T1 18p 33p Address select voltage 44 68p 10n 41 40 39 100p 3.3n 2.2k 4.7k 27p 8.5V 10n 47nH 100p 38 37 36 3.3n 4.7k VAGCIF BB545 2.2p 8.5V 3.3 µ Anti-aliasing filter A/D-converter 4.7k 1.2n 1.8k 100p 10n 4.7p 2.2p 2.2p 4.7p 35 34 33 32 31 30 29 10n 10n 28 27 26 25 24 10n 23 43 42 ATR2731 SAW filter 680nH S+M X6922M Microcontroller 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 SCL SDA 76k 76k 76k 1n 100n 100n 1n WAGC SLI 8.5V Switches 100n 9k 9k 9k 1n 1n 3.3µ 10n 10n 1n 220n ATR2730 Preselector 8.5V RFA RFB VAGCRF 20 ATR2731 4904A–DAB–03/06 ATR2731 13. Application Circuits of the Reference Oscillator Figure 13-1. Oscillator Operation OSCI 68p 33p OSCO 18p Reference divider Figure 13-2. Oscillator Overdriven Reference signal 50 1n OSCO OSCI Reference divider 21 4904A–DAB–03/06 Figure 13-3. Measurement Circuit for Electrical Characteristics 8.5V 100p 3.3n 51k 33k BC846B 22k 2.2k 2.2k 4.7k 1.2n 33k 27p 8.5V 10n REF IN 10n Address select voltage 10n 41 40 39 100p 47nH 4.7p 2.2p 2.2p 4.7p 10n 30 29 28 27 10n 26 100p 10n 24 23 50 2.2p 8.5V 10n IFIN 1.8k BB545 47n 3.3n 4.7k VAGCIF 3.3 µ 4.7k 1k IFAD Microcontroller 44 43 42 38 37 36 35 34 33 32 31 25 ATR2731 Microcontroller SCL SDA 1 2 3 4 76k 76k 5 6 76k 7 8 9 10 11 12 1n 13 14 1n 15 16 17 18 19 20 21 22 WAGC SLI 8.5V 100n 100n 3.3 µ 1n 100n 50 1n 50 100 51 10n 10n 1n 220n Switches 9k 9k 9k ATR2730 Preselector 8.5V RFA RFB VAGCRF O1SA 22 ATR2731 4904A–DAB–03/06 ATR2731 Figure 13-4. RFAGC Voltage-generation Block Circuit V REF VAGC,INT IDA TBI SAW1 SAW2 D/A BUF_IN AGC_BP AGC_RECT AGC_TP V REF SLI WAGC AGCRF voltage CPRF AGC_COMP R AGC_THRESH CHARGE PUMP IDA TAI D/A CAGC Figure 13-5. IFAGC Voltage-generation Block Circuit IFAMP IFMX IFAD Antialiasing filter A/D converter VAGC R1 IFAGC1 R2 IFAGC2 VREF CHARGE PUMP CPRF R AGC_THRESH IDA SLI TCI D/A WAGC AGCIF 23 4904A–DAB–03/06 Figure 13-6. VCO Circuit V Bias VS C1VC V Tune B2VC B1VC C2VC 14. Phase-noise Performance (Example: SFeff = 16899, SFref,eff = 1120, fref = 17.92 MHz, IPD = 200 mA, spectrum analysis: HP7000) Figure 14-1. Phase-noise Over Frequency 10.00 dB/DIV 10.00 dB/DIV < -70 dBc/Hz CENTER 270.384 MHz RB 100 Hz VB 100 Hz SPAN 10.00 kHz ST 3.050 sec CENTER 270.384 MHz RB 1.00 kHz VB 1.00 kHz SPAN 200.0 kHz ST 600.0 msec 24 ATR2731 4904A–DAB–03/06 ATR2731 15. Ordering Information Extended Type Number ATR2731–ILSY ATR2731–ILQY Package SSO44 SSO44 Remarks Tube, Pb-free Taped and reeled, Pb-free 16. Package Information Package SSO44 Dimensions in mm 18.05 17.80 9.15 8.65 7.50 7.30 2.35 0.3 0.8 16.8 44 23 0.25 0.10 0.25 10.50 10.20 technical drawings according to DIN specifications 1 22 25 4904A–DAB–03/06 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. 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