ATR7040

Features • • • • • • • Frequency Range 5 GHz to 6 GHz Pout 25 dBm at 5.8 GHz Gain Typically 30 dB Pin Typically 0 dBm VCC 2.7V to 3.8V Power Consumption in Power-down Mode Typically < 1 µA Package: QFN16 3 mm × 3 mm 5.8 GHz WDCT Power Amplifier ATR7040 Benefits • • • • Biasing Control Extends Battery Time Simple Input and Output Matching Only One Single Supply Required No High-side Switching Transistor Required 1. Description 1.1 Process This 5-GHz power amplifier (PA) is designed using Atmel’s Silicon-Germanium (SiGe) process and provides high efficiency. 1.2 Circuitry The PA, ATR7040, consists of a three-stage amplifier with a typical output power of 25 dBm. The output stage was implemented using an open-collector structure. Power up, power down, and output level are controlled at bias control pin 6 (Vctl). 4868C–DECT–05/06 Figure 1-1. Block Diagram VCC1 7 VCC2 6 ATR7040 RFOUT/VCC3 2 RFOUT/VCC3 3 RFIN 10 Matching Matching Bias control 13 VCTL 14 GND PADDLE GND 15 VCC_CTL 2 ATR7040 4868C–DECT–05/06 ATR7040 2. Pin Configuration Figure 2-1. Pinning QFN16 NC VCC_CTL GND VCTL NC RFOUT/VCC3 RFOUT/VCC3 NC 16 15 14 13 12 NC 1 2 ATR7040 11 NC 3 GND on the 10 RFIN 4 PADDLE 9 NC 5678 NC VCC2 VCC1 NC Table 2-1. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PADDLE Note: Pin Description Symbol NC RFOUT RFOUT NC NC VCC2 VCC1 NC NC RFIN NC NC VCTL GND VCC_CTL NC – Function Not connected(1) RF output and supply voltage for output amplifier stage RF output and supply voltage for output amplifier stage Not connected(1) Not connected(1) Supply voltage for second amplifier stage Supply voltage for first amplifier stage Not connected(1) Not connected(1) RF input Not connected(1) Not connected(1) Control voltage for power ramping Ground Supply voltage for biasing control block Not connected(1) Ground 1. Pin can be connected to paddle for increased GND area 3 4868C–DECT–05/06 3. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Supply voltage Supply current Junction temperature Storage temperature Input RF power Control voltage Note: Symbol VCC Icc Tj TStg Pin Vctl Value 5 400 150 –40 to +125 10 2.5 Unit V mA °C °C dBm V The part may not survive all maximums applied simultaneously. Electrostatic sensitive device. Observe precautions for handling. 4. Thermal Resistance Parameters Junction ambient package QFN16, 3 × 3, slug soldered on PCB Symbol RthJA Value 40 Unit K/W 5. Operating Range Parameters Supply voltage Operating frequency range Ambient temperature range Symbol VCC fin Tamb Value 2.7 to 3.8 5100 to 5900 –25 to +75 Unit V MHz °C 4 ATR7040 4868C–DECT–05/06 ATR7040 6. Electrical Characteristics Operating conditions: VCC = 3.6V, Vctl = 1.5V, input frequency = 5.8 GHz, input power 0 dBm, pulsed mode, duty cycle 10%, ton = 1 ms, Tamb = 25°C, unless otherwise specified. No. 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.10 1.11 1.12 Parameters Frequency range Supply voltage Input power Saturated power output Output power deviation Control voltage range Control input current Input return loss Isolation Power added efficiency Current consumption Current consumption in power-down mode Duty cycle of operation PA operating mode Power-down mode PA on With external matching Vctl ≤ 0.2V At power saturation, Pin = 0 dBm For 25 dBm output power Vctl ≤ 0.2V At saturated output power 5 10 ISOr PAE Icc Icc 33 Test Conditions Depends on external circuitry Vcc Pin Psat Pd Vctl Vctl Ictl 90 –7 35 35 250 1 100 –6 –2 1.0 Pin Symbol Min. 5100 2.7 3.6 0 25 +2 1.7 0.2 Typ. Max. 5900 3.8 Unit MHz V dBm dBm dB V V µA dB dB % mA µA % 7. Application Circuit Figure 7-1. Application Circuit VCC C6 slug 8 7 6 5 L1 TRL2 C3 RFOUT 9 RFIN TRL1 10 C1 11 12 4 3 2 1 C2 13 14 15 16 VCTL VCC 5 4868C–DECT–05/06 8. Diagrams Figure 8-1. Output Power, Efficiency and Supply Currents Versus Input Frequency Pin = 0 dBm, Vcc = 3.6V, Vctl = 1.4V 40 PAE (%) 35 Iges (mA) 30 Pout (dBm) 25 200 150 100 15 50 0 6000 400 350 300 250 Pout (dBm), PAE % 20 10 5600 5650 5700 5750 5800 5850 5900 5950 Frequency (MHz) Figure 8-2. Output Power, Gain, Efficiency and Supply Currents Versus Input Power Freq = 5800 MHz, Vcc = 3.6V, Vctl = 1.4V 40 400 350 300 250 10 PAE (%) 0 150 -10 Pout (dBm) -20 -30 -20 -15 -10 -5 0 5 Iges (mA) 100 50 0 200 Pout (dBm), Gain (dB), PAE (%) 30 20 Pin (dBm) Figure 8-3. Output Power, Efficiency and Supply Currents Versus Operating Voltage Freq = 5800 MHz, Pin = 0 dBm, Vctl = 1.5V 40 PAE (%) 450 400 350 30 Iges (mA) 25 200 Pout (dBm) 20 150 100 15 50 10 2.5 3.0 3.5 4.0 0 300 250 Pout (dBm), PAE (%) 35 Vcc (V) 6 ATR7040 4868C–DECT–05/06 Iges (mA) Iges (mA) Gain (dB) Iges (mA) ATR7040 9. Ordering Information Extended Type Number ATR7040-PVPG ATR7040-PVQG Package QFN16, 3 × 3 QFN16, 3 × 3 Remarks Taped and reeled, MOQ 2000, Pb-free Taped and reeled, MOQ 8000, Pb-free 10. Package Information Package: QFN 16 - 3x3 Exposed pad 1.7x1.7 (acc. JEDEC OUTLINE No. MO-220) Dimensions in mm Not indicated tolerances ±0.05 3 0.9±0.1 0.05 -0.05 68 2. +0 1.7 1 4 0.25 0.4±0.1 16 13 12 9 8 16 1 4 5 0.5 nom. Drawing-No.: 6.543-5115.01-4 Issue: 1; 07.03.05 Assembly Chip PAC 1.5 0. 15 technical drawings according to DIN specifications 7 4868C–DECT–05/06 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. 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