ATSAM3S2AA-AU

Features • Core – ARM® Cortex®-M3 revision 2.0 running at up to 64 MHz – Memory Protection Unit (MPU) – Thumb®-2 instruction set Pin-to-pin compatible with AT91SAM7S legacy products (48- and 64-pin versions) Memories – From 64 to 256 Kbytes embedded Flash, 128-bit wide access, memory accelerator, single plane – From 16 to 48 Kbytes embedded SRAM – 16 Kbytes ROM with embedded bootloader routines (UART, USB) and IAP routines – 8-bit Static Memory Controller (SMC): SRAM, PSRAM, NOR and NAND Flash support – Memory Protection Unit (MPU) System – Embedded voltage regulator for single supply operation – Power-on-Reset (POR), Brown-out Detector (BOD) and Watchdog for safe operation – Quartz or ceramic resonator oscillators: 3 to 20 MHz main power with Failure Detection and optional low power 32.768 kHz for RTC or device clock – High precision 8/12 MHz factory trimmed internal RC oscillator with 4 MHz default frequency for device startup. In-application trimming access for frequency adjustment – Slow Clock Internal RC oscillator as permanent low-power mode device clock – Two PLLs up to 130 MHz for device clock and for USB – Temperature Sensor – Up to 22 peripheral DMA (PDC) channels Low Power Modes – Sleep and Backup modes, down to 3 µA in Backup mode – Ultra low power RTC Peripherals – USB 2.0 Device: 12 Mbps, 2668 byte FIFO, up to 8 bidirectional Endpoints. On-Chip Transceiver – Up to 2 USARTs with ISO7816, IrDA®, RS-485, SPI, Manchester and Modem Mode – Two 2-wire UARTs – Up to 2 Two Wire Interface (I2C compatible), 1 SPI, 1 Serial Synchronous Controller (I2S), 1 High Speed Multimedia Card Interface (SDIO/SD Card/MMC) – Up to 6 Three-Channel 16-bit Timer/Counter with capture, waveform, compare and PWM mode. Quadrature Decoder Logic and 2-bit Gray Up/Down Counter for Stepper Motor – 4-channel 16-bit PWM with Complementary Output, Fault Input, 12-bit Dead Time Generator Counter for Motor Control – 32-bit Real-time Timer and RTC with calendar and alarm features – Up to 15-channel, 1Msps ADC with differential input mode and programmable gain stage – One 2-channel 12-bit 1Msps DAC – One Analog Comparator with flexible input selection, window mode, Selectable input hysteresis – 32-bit Cyclic Redundancy Check Calculation Unit (CRCCU) I/O – Up to 79 I/O lines with external interrupt capability (edge or level sensitivity), debouncing, glitch filtering and on-die Series Resistor Termination – Three 32-bit Parallel Input/Output Controllers, Peripheral DMA assisted Parallel Capture Mode Packages – 100-lead LQFP, 14 x 14 mm, pitch 0.5 mm / 100-ball LFBGA, 9 x 9 mm, pitch 0.8 mm – 64-lead LQFP, 12 x 12 mm, pitch 0.5 mm / 64-pad QFN 9x9 mm, pitch 0.45 mm – 48-lead LQFP, 9 x 9 mm, pitch 0.5 mm / 48-pad QFN 7x7 mm, pitch 0.45 mm • • • AT91 ARM Cortex M3-based Processor ATSAM3S Series Preliminary Summary • • • NOTE: This is a summary document. The complete document is available on the Atmel website at www.atmel.com. • 6500AS–ATARM–11-Dec-09 1. SAM3S Description Atmel's SAM3S series is a member of a family of Flash microcontrollers based on the high performance 32-bit ARM Cortex-M3 RISC processor. It operates at a maximum speed of 64 MHz and features up to 256 Kbytes of Flash and up to 48 Kbytes of SRAM. The peripheral set includes a Full Speed USB Device port with embedded transceiver, a High Speed MCI for SDIO/SD/MMC, an External Bus Interface featuring a Static Memory Controller providing connection to SRAM, PSRAM, NOR Flash, LCD Module and NAND Flash, 2x USARTs, 2x UARTs, 2x TWIs, 3x SPI, an I2S, as well as 1 PWM timer, 6x general-purpose 16-bit timers, an RTC, a ADC, a 12-bit DAC and an analog comparator. The SAM3S series is ready for capacitive touch thanks to the QTouch library, offering an easy way to implement buttons, wheels and sliders The SAM3S device is a medium range general purpose microcontroller with the best ratio in terms of reduced power consumption, processing power and peripheral set. This enables the SAM3S able to sustain a wide range of applications including consumer, industrial control, and PC peripherals. It operates from 1.62V to 3.6V and is available in 48-, 64- and 100-pin QFP, 48- and 64-pin QFN, and 100-pin BGA packages. The SAM3S series is the ideal migration path from the SAM7S series for applications that require more performance. The SAM3S series is pin-to-pin compatible with the SAM7Sseries. 1.1 Configuration Summary The SAM3S series devices differ in memory size, package and features list. Table 1-1 below summarizes the configurations of the device family Table 1-1. Configuration Summary Timer Counter Channels 6 UART/ USARTs 2/2(1) 12-bit DAC Output 2 External Bus Interface 8-bit data, 4 chip selects, 24-bit address 8-bit data, 4 chip selects, 24-bit address 8-bit data, 4 chip selects, 24-bit address - Device SAM3S4C Flash 256 Kbytes single plane 256 Kbytes single plane 256 Kbytes single plane 128 Kbytes single plane 128 Kbytes single plane 128 Kbytes single plane 64 Kbytes single plane 64 Kbytes single plane 64 Kbytes single plane SRAM 48 Kbytes GPIOs 79 ADC 16 ch. HSMCI 1 port 4 bits 1 port 4 bits 1 port 4 bits 1 port 4 bits 1 port 4 bits 1 port 4 bits - Package LQFP100 BGA100 LQFP64 QFN 64 LQFP48 QFN 48 LQFP100 BGA100 LQFP64 QFN 64 LQFP48 QFN 48 LQFP100 BGA100 LQFP64 QFN 64 LQFP48 QFN 48 SAM3S4B SAM3S4A 48 Kbytes 48 Kbytes 3 3 47 34 2/2 2/1 2/2(1) 10 ch. 8 ch. 2 - SAM3S2C 32 Kbytes 6 79 16 ch. 2 SAM3S2B SAM3S2A 32 Kbytes 32 Kbytes 3 3 47 34 2/2 2/1 2/2(1) 10 ch. 8 ch. 2 - SAM3S1C 16 Kbytes 6 79 16 ch. 2 SAM3S1B SAM3S1A 16 Kbytes 16 Kbytes 3 3 47 34 2/2 2/1 10 ch. 8 ch. 2 - Note: 1. Full Modem support on USART1. 2 SAM3S Summary 6500AS–ATARM–11-Dec-09 SAM3S Summary 2. SAM3S Block Diagram Figure 2-1. SAM3S 100-pin Version Block Diagram TD TDI TMO TC S/S K/ W SW DI CL O K SE L IN O VD D UT TT S PCK0-PCK2 System Controller Voltage Regulator PLLA PLLB RC 12/8/4 M PMC JTAG & Serial Wire Flash Unique Identifier In-Circuit Emulator XIN X OUT 3-20 MHz Osc. SUPC 24-Bit N Cortex-M3 Processor SysTick Counter V Fmax 64 MHz I C MPU I/D XIN32 X OUT32 ERASE FLASH 256 KBytes 128 KBytes 64 KBytes VD D JTA G SRAM 48 KBytes 32 KBytes 16 KBytes ROM 16 KBytes OSC 32k RC 32k S 4-layer AHB Bus Matrix Fmax 64 MHz 8 GPBREG VDDIO VDDCORE VDDPLL NRST WDT RTT RTC POR RSTC SM Peripheral Bridge 2668 USB 2.0 Bytes Full FIFO Speed Transceiver DDP DDM PIOA / PIOB / PIOC TWCK0 TWD0 TWCK1 TWD1 URXD0 UTXD0 URXD1 UTXD1 RXD0 TXD0 SCK0 RTS0 CTS0 RXD1 TXD1 SCK1 RTS1 CTS1 DSR1 DTR1 RI1 DCD1 TCLK[0:2] TIOA[0:2] TIOB[0:2] TCLK[3:5] TIOA[3:5] TIOB[3:5] PWMH[0:3] PWML[0:3] PWMFI0 ADTRG AD[0..14] ADVREF DAC0 DAC1 DATRG TWI0 TWI1 UART0 UART1 PDC PDC PDC PDC External Bus Interface NAND Flash Logic PIO USART0 PDC Static Memory Controller D[7:0] A[0:23] A21/NANDALE A22/NANDCLE NCS0 NCS1 NCS2 NCS3 NRD NWE NANDOE NANDWE NWAIT PIODC[7:0] PIODCEN1 PIODCEN2 PIODCCLK NPCS0 NPCS1 NPCS2 NPCS3 MISO MOSI SPCK TF TK TD RD RK RF MCCK MCCDA MCDA[0..3] PDC USART1 PDC Timer Counter A TC[0..2] SPI Timer Counter B TC[3..5] PWM PDC Temp. Sensor ADC DAC PDC PDC PDC PIO PDC SSC PDC High Speed MCI Analog Comparator CRC Unit ADC DAC Temp Sensor ADVREF 3 6500AS–ATARM–11-Dec-09 Figure 2-2. SAM3S 64-pin Version Block Diagram I TD O TM S/ TC SW K/ DIO SW CL K IN O UT VD D SE L JT AG TT S PCK0-PCK2 System Controller Voltage Regulator PLLA PLLB RC 12/8/4 M PMC JTAG & Serial Wire Flash Unique Identifier In-Circuit Emulator XIN XOUT 3-20 MHz Osc. SUPC 24-Bit N Cortex-M3 Processor SysTick Counter V Fmax 64 MHz I C MPU I/D XIN32 XOUT32 ERASE FLASH 256 KBytes 128 KBytes 64 KBytes VD D TD SRAM 48 KBytes 32 KBytes 16 KBytes ROM 16 KBytes OSC 32K RC 32k 8 GPBREG S 4-layer AHB Bus Matrix Fmax 64 MHz VDDIO VDDCORE VDDPLL NRST WDT RTT RTC Peripheral Bridge Transceiver POR RSTC 2668 USB 2.0 Bytes Full FIFO Speed DDP DDM SM PIOA / PIOB TWCK0 TWD0 TWCK1 TWD1 TWI0 TWI1 PDC PDC PDC PDC PDC PIO PIODC[7:0] PIODCEN1 PIODCEN2 PIODCCLK URXD0 UTXD0 URXD1 UTXD1 RXD0 TXD0 SCK0 RTS0 CTS0 RXD1 TXD1 SCK1 RTS1 CTS1 DSR1 DTR1 RI1 DCD1 TCLK[0:2] TIOA[0:2] TIOB[0:2] PWMH[0:3] PWML[0:3] PWMFI0 ADTRG AD[0..8] ADVREF DAC0 DAC1 DATRG UART0 UART1 PDC SPI USART0 PDC NPCS0 NPCS1 NPCS2 NPCS3 MISO MOSI SPCK TF TK TD RD RK RF USART1 PDC Timer Counter A TC[0..2] PDC SSC PDC High Speed MCI PDC MCCK MCCDA MCDA[0..3] PWM Temp. Sensor ADC PDC Analog Comparator ADC DAC Temp Sensor ADVREF DAC PDC CRC Unit 4 SAM3S Summary 6500AS–ATARM–11-Dec-09 SAM3S Summary Figure 2-3. SAM3S 48-pin Version Block Diagram I TD O TM S/ TC SW K/ DIO SW CL K JT AG SE L O UT VD D IN TST PCK0-PCK2 System Controller TD Voltage Regulator PLLA PLLB RC 12/8/4 M PMC JTAG & Serial Wire Flash Unique Identifier In-Circuit Emulator XIN XOUT 3-20 MHz Osc. SUPC Cortex-M3 Processor Fmax 64 MHz MPU 24-Bit SysTick Counter N V I C XIN32 XOUT32 ERASE FLASH 256 KBytes 128 KBytes 64 KBytes VD D SRAM 48 KBytes 32 KBytes 16 KBytes ROM 16 KBytes OSC32K RC 32k 8 GPBREG I/D S 4-layer AHB Bus Matrix Fmax 64 MHz VDDIO VDDCORE VDDPLL RTT RTC Peripheral Bridge Transceiver POR RSTC WDT SM 2668 USB 2.0 Bytes Full FIFO Speed DDP DDM PIOA / PIOB TWCK0 TWD0 TWI0 PDC PDC NPCS0 NPCS1 NPCS2 NPCS3 MISO MOSI SPCK TWCK1 TWD1 TWI1 PDC SPI URXD0 UTXD0 URXD1 UTXD1 RXD0 TXD0 SCK0 RTS0 CTS0 UART0 PDC UART1 PDC PDC TF TK TD RD RK RF USART0 SSC PDC TCLK[0:2] TIOA[0:2] TIOB[0:2] Timer Counter A TC[0..2] Analog Comparator ADC Temp Sensor ADVREF PWMH[0:3] PWML[0:3] PWMFI0 PWM PDC CRC Unit ADTRG AD[0..7] ADVREF Temp. Sensor ADC PDC 5 6500AS–ATARM–11-Dec-09 3. Signal Description Table 3-1 gives details on the signal names classified by peripheral. Table 3-1. Signal Name Signal Description List Function Type Power Supplies Active Level Voltage reference Comments VDDIO VDDIN VDDOUT VDDPLL VDDCORE GND Peripherals I/O Lines and USB transceiver Power Supply Voltage Regulator Input, ADC, DAC and Analog Comparator Power Supply Voltage Regulator Output Oscillator and PLL Power Supply Power the core, the embedded memories and the peripherals Ground Power Power Power Power Power Ground 1.62V to 3.6V 1.8V to 3.6V(4) 1.8V Output 1.62 V to 1.95V 1.62V to 1.95V Clocks, Oscillators and PLLs XIN XOUT XIN32 XOUT32 Main Oscillator Input Main Oscillator Output Slow Clock Oscillator Input Slow Clock Oscillator Output Input Output Input Output VDDIO Reset State: - PIO Input - Internal Pull-up disabled - Schmitt Trigger enabled(1) Reset State: - PIO Input - Internal Pull-up enabled - Schmitt Trigger enabled(1) PCK0 - PCK2 Programmable Clock Output Output Serial Wire/JTAG Debug Port - SWJ-DP TCK/SWCLK TDI TDO/TRACESWO TMS/SWDIO JTAGSEL Test Clock/Serial Wire Clock Test Data In Test Data Out / Trace Asynchronous Data Out Test Mode Select /Serial Wire Input/Output JTAG Selection Input Input Output Input / I/O Input Flash Memory Flash and NVM Configuration Bits Erase Command Reset State: - Erase Input - Internal pull-down enabled - Schmitt Trigger enabled(1) High Permanent Internal pull-down VDDIO Reset State: - SWJ-DP Mode - Internal pull-up disabled - Schmitt Trigger enabled(1) ERASE Input High VDDIO Reset/Test NRST TST Synchronous Microcontroller Reset Test Select I/O Input Low Permanent Internal pull-up Permanent Internal pull-down VDDIO 6 SAM3S Summary 6500AS–ATARM–11-Dec-09 SAM3S Summary Table 3-1. Signal Name Signal Description List (Continued) Function Type Active Level Voltage reference Comments Universal Asynchronous Receiver Transmitter - UARTx URXDx UTXDx UART Receive Data UART Transmit Data Input Output PIO Controller - PIOA - PIOB - PIOC PA0 - PA31 PB0 - PB14 PC0 - PC31 Parallel IO Controller A Parallel IO Controller B Parallel IO Controller C I/O I/O I/O VDDIO Reset State: - PIO or System IOs(2) - Internal pull-up enabled - Schmitt Trigger enabled(1) PIO Controller - Parallel Capture Mode (PIOA Only) PIODC0-PIODC7 PIODCCLK PIODCEN1-2 Parallel Capture Mode Data Parallel Capture Mode Clock Parallel Capture Mode Enable Input Input Input External Bus Interface D0 - D7 A0 - A23 NWAIT Data Bus Address Bus External Wait Signal I/O Output Input Low VDDIO Static Memory Controller - SMC NCS0 - NCS3 NRD NWE Chip Select Lines Read Signal Write Enable Output Output Output NAND Flash Logic NANDOE NANDWE NAND Flash Output Enable NAND Flash Write Enable Output Output Low Low Low Low Low High Speed Multimedia Card Interface - HSMCI MCCK MCCDA MCDA0 - MCDA3 Multimedia Card Clock Multimedia Card Slot A Command Multimedia Card Slot A Data I/O I/O I/O Universal Synchronous Asynchronous Receiver Transmitter USARTx SCKx TXDx RXDx RTSx CTSx DTR1 DSR1 DCD1 RI1 USARTx Serial Clock USARTx Transmit Data USARTx Receive Data USARTx Request To Send USARTx Clear To Send USART1 Data Terminal Ready USART1 Data Set Ready USART1 Data Carrier Detect USART1 Ring Indicator I/O I/O Input Output Input I/O Input Input Input 7 6500AS–ATARM–11-Dec-09 Table 3-1. Signal Name Signal Description List (Continued) Function Type Active Level Voltage reference Comments Synchronous Serial Controller - SSC TD RD TK RK TF RF SSC Transmit Data SSC Receive Data SSC Transmit Clock SSC Receive Clock SSC Transmit Frame Sync SSC Receive Frame Sync Output Input I/O I/O I/O I/O Timer/Counter - TC TCLKx TIOAx TIOBx TC Channel x External Clock Input TC Channel x I/O Line A TC Channel x I/O Line B Input I/O I/O Pulse Width Modulation Controller- PWMC PWMHx PWM Waveform Output High for channel x Output only output in complementary mode when dead time insertion is enabled PWMLx PWM Waveform Output Low for channel x Output PWMFI0 PWM Fault Input Input Serial Peripheral Interface - SPI MISO MOSI SPCK SPI_NPCS0 SPI_NPCS1 SPI_NPCS3 Master In Slave Out Master Out Slave In SPI Serial Clock SPI Peripheral Chip Select 0 SPI Peripheral Chip Select I/O I/O I/O I/O Output Two-Wire Interface- TWI Low Low TWDx TWCKx TWIx Two-wire Serial Data TWIx Two-wire Serial Clock Analog I/O I/O ADVREF ADC, DAC and Analog Comparator Reference Analog Analog-to-Digital Converter - ADC AD0 - AD14 ADTRG Analog Inputs ADC Trigger Analog, Digital Input 12-bit Digital-to-Analog Converter - DAC DAC0 - DAC1 DACTRG Analog output DAC Trigger Analog, Digital Input VDDIO VDDIO 8 SAM3S Summary 6500AS–ATARM–11-Dec-09 SAM3S Summary Table 3-1. Signal Name Signal Description List (Continued) Function Type Active Level Voltage reference Comments Fast Flash Programming Interface - FFPI PGMEN0-PGMEN2 PGMM0-PGMM3 PGMD0-PGMD15 PGMRDY PGMNVALID PGMNOE PGMCK PGMNCMD Programming Enabling Programming Mode Programming Data Programming Ready Data Direction Programming Read Programming Clock Programming Command Input Input I/O Output Output Input Input Input USB Full Speed Device DDM DDP Notes: USB Full Speed Data USB Full Speed Data + 1. Schmitt Triggers can be disabled through PIO registers. 2. Some PIO lines are shared with System IOs. 3. Refer to the USB sub section in the product Electrical Characteristics Section for Pull-down value in USB Mode. 4. See Section 5.3 “Typical Powering Schematics” for restriction on voltage range of Analog Cells. Analog, Digital VDDIO Reset State: - USB Mode - Internal Pull-down(3) Low High Low Low VDDIO VDDIO 9 6500AS–ATARM–11-Dec-09 4. Package and Pinout 4.1 SAM3S4/2/1C Package and Pinout Figure 4-2 shows the orientation of the 100-ball LFBGA Package The 100-ball LFBGA pinout will be specified as soon as the first layout of the device is completed. 4.1.1 100-lead LQFP Package Outline Figure 4-1. Orientation of the 100-lead LQFP Package 75 76 51 50 100 1 25 26 4.1.2 100-ball LFBGA Package Outline The 100-Ball LFBGA package has a 0.8 mm ball pitch and respects Green Standards. Its dimensions are 9 x 9 x 1.1 mm. Figure 4-2. Orientation of the 100-BALL LFBGA Package TOP VIEW 10 9 8 7 6 5 4 3 2 1 ABCDEFGHJ K BALL A1 10 SAM3S Summary 6500AS–ATARM–11-Dec-09 SAM3S Summary 4.1.3 100-Lead LQFP Pinout Table 4-1. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 100-lead LQFP SAM3S4/2/1C Pinout ADVREF GND PB0/AD4 PC29/AD13 PB1/AD5 PC30/AD14 PB2/AD6 PC31 PB3/AD7 VDDIN VDDOUT PA17/PGMD5/ AD0 PC26 PA18/PGMD6/ AD1 PA21/AD8 VDDCORE PC27 PA19/PGMD7/ AD2 PC15/AD11 PA22/AD9 PC13/AD10 PA23 PC12/AD12 PA20/AD3 PC0 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 GND VDDIO PA16/PGMD4 PC7 PA15/PGMD3 PA14/PGMD2 PC6 PA13/PGMD1 PA24 PC5 VDDCORE PC4 PA25 PA26 PC3 PA12/PGMD0 PA11/PGMM3 PC2 PA10/PGMM2 GND PA9/PGMM1 PC1 PA8/XOUT32/ PGMM0 PA7/XIN32/ PGMNVALID VDDIO 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 TDI/PB4 PA6/PGMNOE PA5/PGMRDY PC28 PA4/PGMNCMD VDDCORE PA27 PC8 PA28 NRST TST PC9 PA29 PA30 PC10 PA3 PA2/PGMEN2 PC11 VDDIO GND PC14 PA1/PGMEN1 PC16 PA0/PGMEN0 PC17 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 TDO/TRACESWO/ PB5 JTAGSEL PC18 TMS/SWDIO/PB6 PC19 PA31 PC20 TCK/SWCLK/PB7 PC21 VDDCORE PC22 ERASE/PB12 DDM/PB10 DDP/PB11 PC23 VDDIO PC24 PB13/DAC0 PC25 GND PB8/XOUT PB9/PGMCK/XIN VDDIO PB14/DAC1 VDDPLL 11 6500AS–ATARM–11-Dec-09 4.1.4 100-ball LFBGA Pinout Table 4-2. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 C1 C2 C3 C4 C5 100-ball LFBGA SAM3S4/2/1C Pinout (To be Provided) 12 SAM3S Summary 6500AS–ATARM–11-Dec-09 SAM3S Summary 4.2 SAM3S4/2/1B Package and Pinout Figure 4-3. Orientation of the 64-pad QFN Package 64 1 49 48 16 17 32 TOP VIEW 33 Figure 4-4. Orientation of the 64-lead LQFP Package 48 49 33 32 64 17 1 16 13 6500AS–ATARM–11-Dec-09 4.2.1 64-Lead LQFP and QFN Pinout 64-pin version SAM3S devices are pin-to-pin compatible with AT91SAM7S legacy products. Furthermore, SAM3S products have new functionalities shown in italic in Table 4-3. 64-pin SAM3S4/2/1B Pinout ADVREF GND PB0/AD4 PB1/AD5 PB2/AD6 PB3/AD7 VDDIN VDDOUT PA17/PGMD5/ AD0 PA18/PGMD6/ AD1 PA21/PGMD9/ AD8 VDDCORE PA19/PGMD7/ AD2 PA22/PGMD10/ AD9 PA23/PGMD11 PA20/PGMD8/ AD3 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 GND VDDIO PA16/PGMD4 PA15/PGMD3 PA14/PGMD2 PA13/PGMD1 PA24/PGMD12 VDDCORE PA25/PGMD13 PA26/PGMD14 PA12/PGMD0 PA11/PGMM3 PA10/PGMM2 PA9/PGMM1 PA8/XOUT32/ PGMM0 PA7/XIN32/ PGMNVALID 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 TDI/PB4 PA6/PGMNOE PA5/PGMRDY PA4/PGMNCMD PA27/PGMD15 PA28 NRST TST PA29 PA30 PA3 PA2/PGMEN2 VDDIO GND PA1/PGMEN1 PA0/PGMEN0 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 TDO/TRACESWO/PB5 JTAGSEL TMS/SWDIO/PB6 PA31 TCK/SWCLK/PB7 VDDCORE ERASE/PB12 DDM/PB10 DDP/PB11 VDDIO PB13/DAC0 GND XOUT/PB8 XIN/PGMCK/PB9 PB14/DAC1 VDDPLL Table 4-3. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Note: The bottom pad of the QFN package must be connected to ground. 14 SAM3S Summary 6500AS–ATARM–11-Dec-09 SAM3S Summary 4.3 SAM3S4/2/1A Package and Pinout Figure 4-5. Orientation of the 48-pad QFN Package 48 1 37 36 12 13 TOP VIEW 24 25 Figure 4-6. Orientation of the 48-lead LQFP Package 36 37 25 24 48 13 1 12 15 6500AS–ATARM–11-Dec-09 4.3.1 48-Lead LQFP and QFN Pinout Table 4-4. 1 2 3 4 5 6 7 8 9 10 11 12 Note: 48-pin SAM3S4/2/1A Pinout ADVREF GND PB0/AD4 PB1/AD5 PB2/AD6 PB3/AD7 VDDIN VDDOUT 13 14 15 16 17 18 19 20 21 22 23 24 VDDIO PA16/PGMD4 PA15/PGMD3 PA14/PGMD2 PA13/PGMD1 VDDCORE PA12/PGMD0 PA11/PGMM3 PA10/PGMM2 PA9/PGMM1 PA8/XOUT32/ PGMM0 PA7/XIN32/ PGMNVALID 25 26 27 28 29 30 31 32 33 34 35 36 TDI/PB4 PA6/PGMNOE PA5/PGMRDY PA4/PGMNCMD NRST TST PA3 PA2/PGMEN2 VDDIO GND PA1/PGMEN1 PA0/PGMEN0 37 38 39 40 41 42 43 44 45 46 47 48 TDO/TRACESWO/ PB5 JTAGSEL TMS/SWDIO/PB6 TCK/SWCLK/PB7 VDDCORE ERASE/PB12 DDM/PB10 DDP/PB11 XOUT/PB8 XIN/PB9/PGMCK VDDIO VDDPLL PA17/PGMD5/ AD0 PA18/PGMD6/ AD1 PA19/PGMD7/ AD2 PA20/AD3 The bottom pad of the QFN package must be connected to ground. 16 SAM3S Summary 6500AS–ATARM–11-Dec-09 SAM3S Summary 5. Power Considerations 5.1 Power Supplies The SAM3S product has several types of power supply pins: • VDDCORE pins: Power the core, the embedded memories and the peripherals; voltage ranges from 1.62V and 1.95V. • VDDIO pins: Power the Peripherals I/O lines (Input/Output Buffers); USB transceiver; Backup part, 32kHz crystal oscillator and oscillator pads; ranges from 1.62V and 3.6V • VDDIN pin: Voltage Regulator Input, ADC, DAC and Analog Comparator Power Supply; Voltage ranges from 1.8V to 3.6V • VDDPLL pin: Powers the PLLA, PLLB, the Fast RC and the 3 to 20 MHz oscillator; voltage ranges from 1.62V and 1.95V. 5.2 Voltage Regulator The SAM3S embeds a voltage regulator that is managed by the Supply Controller. This internal regulator is intended to supply the internal core of SAM3S. It features two different operating modes: • In Normal mode, the voltage regulator consumes less than 700 µA static current and draws 80 mA of output current. Internal adaptive biasing adjusts the regulator quiescent current depending on the required load current. In Wait Mode quiescent current is only 7 µA. • In Backup mode, the voltage regulator consumes less than 1 µA while its output (VDDOUT) is driven internally to GND. The default output voltage is 1.80V and the start-up time to reach Normal mode is inferior to 100 µs. For adequate input and output power supply decoupling/bypassing, refer to the Voltage Regulator section in the Electrical Characteristics section of the datasheet. 5.3 Typical Powering Schematics The SAM3S supports a 1.62V-3.6V single supply mode. The internal regulator input connected to the source and its output feeds VDDCORE. Figure 5-1 shows the power schematics. As VDDIN powers the voltage regulator, the ADC/DAC and the analog comparator, when the user does not want to use the embedded voltage regulator, it can be disabled by software via the SUPC (note that it is different from Backup mode). 17 6500AS–ATARM–11-Dec-09 Figure 5-1. Single Supply VDDIO Main Supply (1.8V-3.6V) VDDIN VDDOUT Voltage Regulator USB Transceivers. ADC, DAC Analog Comp. VDDCORE VDDPLL Note: Restrictions With Main Supply < 2.4 V, USB and ADC/DAC and Analog comparator are not usable. With Main Supply ≥ 2.4V and < 3V, USB is not usable. With Main Supply ≥ 3V, all peripherals are usable. Figure 5-2. Core Externally Supplied Main Supply (1.62V-3.6V) VDDIO USB Transceivers. Can be the same supply ADC, DAC Analog Comp. ADC, DAC, Analog Comparator Supply (2.4V-3.6V) VDDIN VDDOUT VDDCORE Supply (1.62V-1.95V) Voltage Regulator VDDCORE VDDPLL Note: Restrictions With Main Supply < 2.4 V, USB and ADC/DAC and Analog comparator are not usable. With Main Supply ≥ 2.4V and < 3V, USB is not usable. With Main Supply ≥ 3V, all peripherals are usable. Figure 5-3 below provides an example of the powering scheme when using a backup battery. Since the PIO state is preserved when in backup mode, any free PIO line can be used to switch off the external regulator by driving the PIO line at low level (PIO is input, pull-up enabled after backup reset). External wake-up of the system can be from a push button or any signal. See Section 5.6 “Wake-up Sources” for further details. 18 SAM3S Summary 6500AS–ATARM–11-Dec-09 SAM3S Summary Figure 5-3. Backup Battery ADC, DAC, Analog Comparator Supply (2.4V-3.6V) Backup Battery VDDIO + VDDIN USB Transceivers. ADC, DAC Analog Comp. Main Supply IN OUT VDDOUT Voltage Regulator 3.3V LDO ON/OFF VDDCORE VDDPLL PIOx (Output) WAKEUPx External wakeup signal Note: The two diodes provide a “switchover circuit” (for illustration purpose) between the backup battery and the main supply when the system is put in backup mode. 5.4 Active Mode Active mode is the normal running mode with the core clock running from the fast RC oscillator, the main crystal oscillator or the PLLA. The power management controller can be used to adapt the frequency and to disable the peripheral clocks. 5.5 Low Power Modes The various low power modes of the SAM3S are described below: 5.5.1 Backup Mode The purpose of backup mode is to achieve the lowest power consumption possible in a system which is performing periodic wake-ups to perform tasks but not requiring fast startup time (