ATSAM3U_10

Features • Core – ARM® Cortex®-M3 revision 2.0 running at up to 96 MHz – Memory Protection Unit (MPU) – Thumb®-2 instruction set Memories – From 64 to 256 Kbytes embedded Flash, 128-bit wide access, memory accelerator, dual bank – From 16 to 48 Kbytes embedded SRAM with dual banks – 16 Kbytes ROM with embedded bootloader routines (UART, USB) and IAP routines – Static Memory Controller (SMC): SRAM, NOR, NAND support. NAND Flash controller with 4 Kbytes RAM buffer and ECC System – Embedded voltage regulator for single supply operation – POR, BOD and Watchdog for safe reset – Quartz or resonator oscillators: 3 to 20 MHz main and optional low power 32.768 kHz for RTC or device clock. – High precision 8/12 MHz factory trimmed internal RC oscillator with 4 MHz Default Frequency for fast device startup – Slow Clock Internal RC oscillator as permanent clock for device clock in low power mode – One PLL for device clock and one dedicated PLL for USB 2.0 High Speed Device – Up to 17 peripheral DMA (PDC) channels and 4-channel central DMA Low Power Modes – Sleep and Backup modes, down to 2.5 µA in Backup mode – Backup domain: VDDBU pin, RTC, 32 backup registers – Ultra low power RTC: 0.6 µA Peripherals – USB 2.0 Device: 480 Mbps, 4-kbyte FIFO, up to 7 bidirectional Endpoints, dedicated DMA – Up to 4 USARTs (ISO7816, IrDA®, Flow Control, SPI, Manchester support) and one UART – Up to 2 TWI (I2C compatible), 1 SPI, 1 SSC (I2S), 1 HSMCI (SDIO/SD/MMC) – 3-Channel 16-bit Timer/Counter (TC) for capture, compare and PWM – 4-channel 16-bit PWM (PWMC) – 32-bit Real Time Timer (RTT) and RTC with calendar and alarm features – 8-channel 12-bit 1MSPS ADC with differential input mode and programmable gain stage, 8-channel 10-bit ADC I/O – Up to 96 I/O lines with external interrupt capability (edge or level sensitivity), debouncing, glitch filtering and on-die Series Resistor Termination – Three 32-bit Parallel Input/Outputs (PIO) Packages – 100-lead LQFP, 14 x 14 mm, pitch 0.5 mm – 100-ball LFBGA, 9 x 9 mm, pitch 0.8 mm – 144-lead LQFP, 20 x 20 mm, pitch 0.5 mm – 144-ball LFBGA, 10 x 10 mm, pitch 0.8 mm • • AT91ARM Cortex M3-based Microcontrollers ATSAM3U Series Preliminary Summary • • • • NOTE: This is a summary document. The complete document is available on the Atmel website at www.atmel.com. 6430CS–ATARM–09-Apr-10 1. SAM3U Description Atmel's SAM3U series is a member of a family of Flash microcontrollers based on the high performance 32-bit ARM Cortex-M3 RISC processor. It operates at a maximum speed of 96 MHz and features up to 256 Kbytes of Flash and up to 52 Kbytes of SRAM. The peripheral set includes a High Speed USB Device port with embedded transceiver, a High Speed MCI for SDIO/SD/MMC, an External Bus Interface with NAND Flash controller, up to 4xUSARTs (SAM3U1C/2C/4C have 3), up to 2xTWIs (SAM3U1C/2C/4C have 1), up to 5xSPIs SAM3U1C/2C/4C have 4), as well as 4xPWM timers, 3xgeneral purpose 16-bit timers, an RTC, a 12-bit ADC and a 10-bit ADC. The SAM3U architecture is specifically designed to sustain high speed data transfers. It includes a multi-layer bus matrix as well as multiple SRAM banks, PDC and DMA channels that enable it to run tasks in parallel and maximize data throughput. It can operate from 1.62V to 3.6V and comes in 100-pin and 144-pin LQFP and BGA packages. The SAM3U device is particularly well suited for USB applications: data loggers, PC peripherals and any high speed bridge (USB to SDIO, USB to SPI, USB to External Bus Interface). 1.1 Configuration Summary The SAM3U series differ in memory sizes, package and features list. Table 1-1 summarizes the configurations of the six devices. Table 1-1. Configuration Summary Flash Organization SRAM dual plane 52 Kbytes 36 Kbytes 20 Kbytes 52 Kbytes 36 Kbytes 20 Kbytes Number of PIOs 96 Number of USARTs 4 Number of TWI 2 FWUP, SHDN pins Yes External Bus Interface 8 or 16 bits, 4 chip selects, 24-bit address 8 or 16 bits, 4 chip selects 24-bit address 8 or 16 bits, 4 chip selects, 24-bit address 8 bits, 2 chip selects, 8-bit address HSMCI data size 8 bits Device SAM3U4E Flash 2x128 Kbytes 128 Kbytes 64 Kbytes 2 x 128 Kbytes 128 Kbytes 64 Kbytes Package LQFP144 BGA144 LQFP144 BGA144 LQFP144 BGA144 LQFP100 BGA100 LQFP100 BGA100 LQFP100 BGA100 ADC 2 (8+ 8 channels) 2 (8+ 8 channels) 2 (8+ 8 channels) 2 (4+ 4 channels) 2 (4+ 4 channels) 2 (4+ 4 channels) SAM3U2E single plane 96 4 2 Yes 8 bits SAM3U1E single plane 96 4 2 Yes 8 bits SAM3U4C dual plane 57 3 1 FWUP 4 bits SAM3U2C single plane 57 3 1 FWUP 8 bits, 2 chip selects, 8- 4 bits bit address 8 bits 2 chip selects, 8-bit address 4 bits SAM3U1C single plane 57 3 1 FWUP Note: 1. The SRAM size takes into account the 4-Kbyte RAM buffer of the NAND Flash Controller (NFC) which can be used by the core if not used by the NFC. 2 SAM3U Series 6430CS–ATARM–09-Apr-10 SAM3U Series 2. SAM3U Block Diagram Figure 2-1. 144-pin SAM3U4/2/1E Block Diagram TD TDI TMO/T R TC S/S AC K/ WD ES SW IO W O CL K D VB U T D G MII FS D DP F D SD HM D SD HP SD M L SE JT AG DI MASTER SLAVE System Controller TST PCK0 -PCK2 JTAG & Serial Wire HS UTMI Transceiver USB Device HS VD VD VD DO N UT PLLA UPLL In-Circuit Emulator SysTick Counter N V Cortex-M3 Processor I Fmax 96 MHz C MPU I/D Flash Unique Identifier S Voltage Regulator EBI XIN XOUT OSC 3-20 M RC Osc. 12/8/4 M WDT PMC NAND Flash Controller & ECC DMA NANDRDY D0-D15 A0/NBS0 A1 A2-A20 NCS0 NCS1 NRD NWR0/NWE NWR1/NBS1 Static Memory Controller NWAIT A23 A21/ NANDALE A22/ NANDCLE NCS3 SPI SSC HSMCI NCS2 NANDOE, NANDWE 5-layer AHB Bus Matrix NAND Flash SRAM (4KBytes) VDDUTMI VDDCORE SM BOD RC 32K 8 GPBREG RTT RTC XIN32 XOUT32 SHDN FWUP VDDBU NRSTB ERASE NRST OSC 32K SUPC POR FLASH 2x128 KBytes 1x128 KBytes 1x64 KBytes SRAM0 32 KBytes 16 KBytes 8 KBytes SRAM1 16 KBytes 16 KBytes ROM 16 KBytes APB Peripheral DMA Controller Peripheral Bridge 4-Channel DMA PDC 8-channel 12-bit ADC 10-bit ADC PDC TWI0 TWI1 PDC PDC USART0 USART1 USART2 USART3 PDC PWM TC0 TC1 TC2 RSTC PIOA PIOC PIOB UART AD VR AD 2B V VD RE -A DA F D1 NA AD 2 12 A BT B0 D0 RG -A -A D T D1 7 TW WD 2B C 0- 7 K0 TW -T D W1 C K U1 R C U XD TS T X R 0-C D SCTSO TS R K0 -RT 3 D-S TXX0 SC 3 D -RDK3 0- X TX 3 D D3 C D 0 PW D RI0 SR M PW H D 0 0 T M -P R0 L0 W TC -P MH L WM 3 TI K0- L3 OT TI A0 CL O -T K2 N B0- IOA PC T 2 S0 IOB -N 2 PC SP S3 C MK O M SI IS O TK TF TD R D R F R DA K 0DA C7 DA C K TR G EF -A D1 3 6430CS–ATARM–09-Apr-10 Figure 2-2. 100-pin SAM3U4/2/1C Block Diagram TD I TD O TM / T S RA TC / S C E K/ WD SW SW IO O CL K JT AG SE L D VB U T D G MII FS D DP FS D DM H D SD HP SD M N VD MASTER SLAVE System Controller TST PCK0 -PCK2 JTAG & Serial Wire HS UTMI Transceiver USB Device HS VD VD DO DI UT PLLA UPLL In-Circuit Emulator SysTick Counter N V I C Voltage Regulator EBI XIN XOUT OSC 3-20 M RC Osc. 12/8/4 M WDT PMC Cortex-M3 Processor Fmax 96 MHz MPU I/D Flash Unique Identifier NAND Flash Controller & ECC DMA NANDRDY D0-D7 A0 A1 A2-A7 NCS0 NCS1 NRD NWE Static Memory Controller S 5-layer AHB Bus Matrix NAND Flash SRAM (4KBytes) VDDUTMI VDDCORE SM BOD RC 32K 8 GPBREG RTT RTC XIN32 XOUT32 SHDN FWUP VDDBU NRSTB ERASE NRST OSC 32K SUPC POR FLASH 2x128 KBytes 1x128 KBytes 1x64 KBytes SRAM0 32 KBytes 16 KBytes 8 KBytes SRAM1 16 KBytes 16 KBytes ROM 16 KBytes APB Peripheral DMA Controller Peripheral Bridge 4-Channel DMA NANDALE NANDCLE PDC 4-channel 12-bit ADC 10-bit ADC PDC PDC PDC USART0 USART1 USART2 PDC PWM TC0 TC1 TC2 SPI SSC HSMCI NANDOE, NANDWE RSTC PIOA PIOB TWI UART AD VR 4 SAM3U Series 6430CS–ATARM–09-Apr-10 AD 2B V VD RE -A DA F D1 NA AD 2 12 A BT B0 D0 RG -A -A D T D1 3 TW WD 2B C 0- 3 K0 TW -T D W1 C K U1 R C U XD TS T X R 0-C D SCTSO TS R K0 -RT 2 D-S TXX0 SC 2 D -RDK2 0- X TX 2 D D2 C D 0 PW D RI0 SR M PW H D 0 0- T M P R0 L0 W TC -P MH LK WM 3 TI 0- L3 OT TI A0 CL O -T K2 N B0- IOA PC T 2 S0 IOB -N 2 PC SP S3 C MK O M SI IS O TK TF TD R D R F DA RK 0DA 3 C DA C K TR G EF -A D1 SAM3U Series 3. Signal Description Table 3-1 gives details on the signal names classified by peripheral. Table 3-1. Signal Name Signal Description List Function Type Power Supplies Active Level Voltage Reference Comments VDDIO VDDIN VDDOUT VDDUTMII GNDUTMII VDDBU GNDBU VDDPLL GNDPLL VDDANA GNDANA VDDCORE GND Peripherals I/O Lines Power Supply Voltage Regulator Input Voltage Regulator Output USB UTMI+ Interface Power Supply USB UTMI+ Interface Ground Backup I/O Lines Power Supply Backup Ground PLL A, UPLL and OSC 3-20 MHz Power Supply PLL A, UPLL and OSC 3-20 MHz Ground ADC Analog Power Supply ADC Analog Ground Core, Memories and Peripherals Chip Power Supply Ground Power Power Power Power Ground Power Ground Power Ground Power Ground Power Ground 1.62V to 3.6V 1.8V to 3.6V 1.8V 3.0V to 3.6V 1.62V to 3.6V 1.62 V to 1.95V 2.0V to 3.6V 1.62V to 1.95V Clocks, Oscillators and PLLs XIN XOUT XIN32 XOUT32 VBG PCK0 - PCK2 Main Oscillator Input Main Oscillator Output Slow Clock Oscillator Input Slow Clock Oscillator Output Bias Voltage Reference Programmable Clock Output Input Output Input Output Analog Output Shutdown, Wakeup Logic push/pull 0: The device is in backup mode 1: The device is running (not in backup mode) Needs external pull-up VDDIO VDDBU VDDPLL SHDN Shut-Down Control Output VDDBU FWUP Force Wake-Up Input Input Low Serial Wire/JTAG Debug Port (SWJ-DP) TCK/SWCLK TDI TDO/TRACESWO TMS/SWDIO JTAGSEL Test Clock/Serial Wire Clock Test Data In Test Data Out/Trace Asynchronous Data Out Test Mode Select/Serial Wire Input/Output JTAG Selection Input Input Output Input Input High VDDBU VDDIO No pull-up resistor No pull-up resistor No pull-up resistor Internal permanent pull-down 5 6430CS–ATARM–09-Apr-10 Table 3-1. Signal Name Signal Description List (Continued) Function Type Flash Memory Active Level Voltage Reference Comments ERASE Flash and NVM Configuration Bits Erase Command Input High VDDBU Internal permanent 15K pulldown Reset/Test NRST NRSTB TST Microcontroller Reset Asynchronous Microcontroller Reset Test Select I/O Input Input Universal Asynchronous Receiver Transceiver - UART URXD UTXD UART Receive Data UART Transmit Data Input Output PIO Controller - PIOA - PIOB - PIOC •Schmitt Trigger (1) Reset State: •PIO Input •Internal pullup enabled •Schmitt Trigger (2) Reset State: •PIO Input •Internal pullup enabled •Schmitt Trigger(3) Reset State: •PIO Input •Internal pullup enabled Low Low VDDBU VDDIO Internal permanent pullup Internal permanent pullup Internal permanent pulldown PA0 - PA31 Parallel IO Controller A I/O PB0 - PB31 Parallel IO Controller B I/O VDDIO PC0 - PC31 Parallel IO Controller C I/O External Bus Interface D0 - D15 A0 - A23 NWAIT Data Bus Address Bus External Wait Signal I/O Output Input Static Memory Controller - SMC NCS0 - NCS3 NWR0 - NWR1 NRD NWE NBS0 - NBS1 Chip Select Lines Write Signal Read Signal Write Enable Byte Mask Signal Output Output Output Output Output NAND Flash Controller - NFC NANDOE NANDWE NANDRDY NAND Flash Output Enable NAND Flash Write Enable NAND Ready Output Output Input Low Low Low Low Low Low Low Low 6 SAM3U Series 6430CS–ATARM–09-Apr-10 SAM3U Series Table 3-1. Signal Name Signal Description List (Continued) Function Type Active Level Voltage Reference Comments High Speed Multimedia Card Interface - HSMCI CK CDA DA0 - DA7 Multimedia Card Clock Multimedia Card Slot A Command Multimedia Card Slot A Data I/O I/O I/O Universal Synchronous Asynchronous Receiver Transmitter - USARTx SCKx TXDx RXDx RTSx CTSx DTR0 DSR0 DCD0 RI0 USARTx Serial Clock USARTx Transmit Data USARTx Receive Data USARTx Request To Send USARTx Clear To Send USART0 Data Terminal Ready USART0 Data Set Ready USART0 Data Carrier Detect USART0 Ring Indicator I/O I/O Input Output Input I/O Input Input Input Synchronous Serial Controller - SSC TD RD TK RK TF RF SSC Transmit Data SSC Receive Data SSC Transmit Clock SSC Receive Clock SSC Transmit Frame Sync SSC Receive Frame Sync Output Input I/O I/O I/O I/O Timer/Counter - TC TCLKx TIOAx TIOBx TC Channel x External Clock Input TC Channel x I/O Line A TC Channel x I/O Line B Input I/O I/O Pulse Width Modulation Controller- PWMC PWMHx PWM Waveform Output High for channel x PWM Waveform Output Low for channel x PWMLx Output Output only output in complementary mode when dead time insertion is enabled PWMFI0-2 PWM Fault Input Input Serial Peripheral Interface - SPI MISO MOSI SPCK NPCS0 NPCS1 - NPCS3 Master In Slave Out Master Out Slave In SPI Serial Clock SPI Peripheral Chip Select 0 SPI Peripheral Chip Select I/O I/O I/O I/O Output Low Low 7 6430CS–ATARM–09-Apr-10 Table 3-1. Signal Name Signal Description List (Continued) Function Type Two-Wire Interface - TWI Active Level Voltage Reference Comments TWDx TWCKx TWIx Two-wire Serial Data TWIx Two-wire Serial Clock I/O I/O 12-bit Analog-to-Digital Converter - ADC12B AD12Bx AD12BTRG AD12BVREF Analog Inputs ADC Trigger ADC Reference Analog Input Analog 10-bit Analog-to-Digital Converter - ADC ADx ADTRG ADVREF Analog Inputs ADC Trigger ADC Reference Analog Input Analog Fast Flash Programming Interface - FFPI PGMEN0-PGMEN2 Programming Enabling PGMM0-PGMM3 PGMD0-PGMD15 PGMRDY PGMNVALID PGMNOE PGMCK PGMNCMD Programming Mode Programming Data Programming Ready Data Direction Programming Read Programming Clock Programming Command Input Input I/O Output Output Input Input Input USB High Speed Device - UDPHS DFSDM DFSDP DHSDM DHSDP Notes: USB Device Full Speed Data USB Device Full Speed Data + USB Device High Speed Data USB Device High Speed Data + Analog Analog Analog Analog VDDUTMII Low High Low Low VDDIO 1. PIOA: Schmitt Trigger on all except PA14 on 100 and 144 packages. 2. PIOB: Schmitt Trigger on all except PB9 to PB16, PB25 to PB31 on 100 and 144 packages. 3. PIOC: Schmitt Trigger on all except PC20 to PC27 on 144 package. 3.1 Design Considerations In order to facilitate schematic capture when using a SAM3U design, Atmel provides a “Schematics Checklist” Application note. Please visit http://www.atmel.com/products/AT91/ for additional documentation. 8 SAM3U Series 6430CS–ATARM–09-Apr-10 SAM3U Series 4. Package and Pinout The SAM3U4/2/1E is available in 144-lead LQFP and 144-ball LFBGA packages. The SAM3U4/2/1C is available in 100-lead LQFP and 100-ball LFBGA packages. 4.1 4.1.1 SAM3U4/2/1E Package and Pinout 144-ball LFBGA Package Outline The 144-Ball LFBGA package has a 0.8 mm ball pitch and respects Green Standards. Its dimensions are 10 x 10 x 1.4 mm. Figure 4-1. Orientation of the 144-ball LFBGA Package TOP VIEW 12 11 10 9 8 7 6 5 4 3 2 1 ABCDEF GHJ BALL A1 KLM 4.1.2 144-lead LQFP Package Outline Figure 4-2. Orientation of the 144-lead LQFP Package 108 109 73 72 144 1 36 37 9 6430CS–ATARM–09-Apr-10 4.1.3 Table 4-1. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 144-lead LQFP Pinout 144-pin SAM3U4/2/1E Pinout TDI VDDOUT VDDIN TDO/TRACESWO PB31 PB30 TMS/SWDIO PB29 TCK/SWCLK PB28 NRST PB27 PB26 PB25 PB24 VDDCORE VDDIO GND PB23 PB22 PB21 PC21 PB20 PB19 PB18 PB17 VDDCORE PC14 PB14 PB10 PB9 PC19 GNDPLL VDDPLL XOUT XIN 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 DHSDP DHSDM VBG VDDUTMI DFSDM DFSDP GNDUTMI VDDCORE PA28 PA29 PC22 PA31 PC23 VDDCORE VDDIO GND PB0 PC24 PB1 PC25 PB2 PC26 PB11 GND PB12 PB13 PC27 PA27 PB5 PB6 PB7 PB8 PC28 PC29 PC30 PC31 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 VDDANA ADVREF GNDANA AD12BVREF PA22/PGMD14 PA30 PB3 PB4 PC15 PC16 PC17 PC18 VDDIO VDDCORE PA13/PGMD5 PA14/PGMD6 PC10 GND PA15/PGMD7 PC11 PA16/PGMD8 PC12 PA17/PGMD9 PB16 PB15 PC13 PA18/PGMD10 PA19/PGMD11 PA20/PGMD12 PA21/PGMD13 PA23/PGMD15 VDDIO PA24 PA25 PA26 PC20 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 PA0/PGMNCMD PC0 PA1/PGMRDY PC1 PA2/PGMNOE PC2 PA3/PGMNVALID PC3 PA4/PGMM0 PC4 PA5/PGMM1 PC5 PA6/PGMM2 PC6 PA7/PGMM3 PC7 VDDCORE GND VDDIO PA8/PGMD0 PC8 PA9/PGMD1 PC9 PA10/PGMD2 PA11/PGMD3 PA12/PGMD4 FWUP SHDN ERASE TST VDDBU GNDBU NRSTB JTAGSEL XOUT32 XIN32 10 SAM3U Series 6430CS–ATARM–09-Apr-10 SAM3U Series 4.1.4 Table 4-2. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 144-ball LFBGA Pinout 144-ball SAM3U4/2/1E Pinout VBG VDDUTMI PB9 PB10 PB19 PC21 PB26 TCK/SWCLK PB30 TDO/TRACESWO XIN32 XOUT32 VDDCORE GNDUTMI XOUT PB14 PB17 PB22 PB25 PB29 VDDIN JTAGSEL ERASE SHDN DFSDP DHSDP XIN VDDPLL PB18 PB20 PB27 TMS/SWDIO VDDOUT NRSTB TST FWUP D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 DFSDM DHSDM GNDPLL PC14 PB21 PB23 PB24 PB28 TDI VDDBU PA10/PGMD2 PA11/PGMD3 PC22 PA28 PC19 VDDCORE GND VDDIO GNDBU NRST PB31 PA12/PGMD4 PA8/PGMD0 PC8 PA31 PA29 PC23 VDDCORE VDDIO GND GND VDDIO PC9 PA9/PGMD1 VDDCORE PC7 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 PB0 PC26 PB2 PC25 PB1 GND GND VDDCORE PC4 PA6/PGMM2 PA7/PGMM3 PC6 PC24 PC27 PA27 PB12 PB11 GND VDDCORE PB16 PB15 PC3 PA5/PGMM1 PC5 PB5 PB6 PC28 PB8 PB13 VDDIO PA13/PGMD5 PA17/PGMD9 PC13 PA2/PGMNOE PA3/PGMNVALID PA4/PGMM0 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 PB7 PC31 PC29 PB3 PB4 PA14/PGMD6 PA16/PGMD8 PA18/PGMD10 PC20 PA1/PGMRDY PC1 PC2 PC30 ADVREF AD12BVREF PA22/PGMD14 PC17 PC10 PC12 PA19/PGMD11 PA23/PGMD15 PA0/PGMNCMD PA26 PC0 VDDANA GNDANA PA30 PC15 PC16 PC18 PA15/PGMD7 PC11 PA20/PGMD12 PA21/PGMD13 PA24 PA25 11 6430CS–ATARM–09-Apr-10 4.2 4.2.1 SAM3U4/2/1C Package and Pinout 100-lead LQFP Package Outline Figure 4-3. Orientation of the 100-lead LQFP Package 75 76 51 50 100 1 25 26 4.2.2 100-ball LFBGA Package Outline Figure 4-4. Orientation of the 100-ball LFBGA Package TOP VIEW 1 2 3 4 5 6 7 8 9 10 A B C D E F G H J K 12 SAM3U Series 6430CS–ATARM–09-Apr-10 SAM3U Series 4.2.3 Table 4-3. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 100-lead LQFP Pinout 100-pin SAM3U4/2/1C1 Pinout VDDANA ADVREF GNDANA AD12BVREF PA22/PGMD14 PA30 PB3 PB4 VDDCORE PA13/PGMD5 PA14/PGMD6 PA15/PGMD7 PA16/PGMD8 PA17/PGMD9 PB16 PB15 PA18/PGMD10 PA19/PGMD11 PA20/PGMD12 PA21/PGMD13 PA23/PGMD15 VDDIO PA24 PA25 PA26 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PA0/PGMNCMD PA1/PGMRDY PA2/PGMNOE PA3/PGMNVALID PA4/PGMM0 PA5/PGMM1 PA6/PGMM2 PA7/PGMM3 VDDCORE GND VDDIO PA8/PGMD0 PA9/PGMD1 PA10/PGMD2 PA11/PGMD3 PA12/PGMD4 FWUP ERASE TST VDDBU GNDBU NRSTB JTAGSEL XOUT32 XIN32 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 TDI VDDOUT VDDIN TDO/TRACESWO TMS/SWDIO TCK/SWCLK NRST PB24 VDDCORE VDDIO GND PB23 PB22 PB21 PB20 PB19 PB18 PB17 PB14 PB10 PB9 GNDPLL VDDPLL XOUT XIN 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 DHSDP DHSDM VBG VDDUTMI DFSDM DFSDP GNDUTMI VDDCORE PA28 PA29 PA31 VDDCORE VDDIO GND PB0 PB1 PB2 PB11 PB12 PB13 PA27 PB5 PB6 PB7 PB8 13 6430CS–ATARM–09-Apr-10 4.2.4 100-ball LFBGA Pinout Table 4-4. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 C1 C2 C3 C4 C5 100-ball SAM3U4/2/1C Pinout VBG XIN XOUT PB17 PB21 PB23 TCK/SWCLK VDDIN VDDOUT XIN32 VDDCORE GNDUTMI VDDUTMI PB10 PB18 PB24 NRST C6 C7 C8 C9 C10 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 PB22 TMS/SWDIO NRSTB JTAGSEL VDDBU DFSDM DHSDM VDDPLL VDDCORE PB20 ERASE TST FWUP PA11/PGMD3 PA12/PGMD4 PA29 GND PA28 PB9 GNDBU VDDIO VDDCORE PA10/PGMD2 PA9/PGMD1 PA8/PGMD0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 H1 H2 H3 H4 H5 PB1 PB12 VDDIO PA31 VDDIO GND PB16 PA6/PGMM2 VDDCORE PA7/PGMM3 PB11 PB2 PB0 PB13 VDDCORE GND PB15 PA3/PGMNVALID PA5/PGMM1 PA4/PGMM0 VDDCORE PB5 PA27 PA22/PGMD14 PA13/PGMD5 H6 H7 H8 H9 H10 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 PA15/PGMD7 PA18/PGMD10 PA24 PA1/PGMRDY PA2/PGMNOE PB6 PB8 ADVREF PA30 PB3 PA16/PGMD8 PA19/PGMD11 PA21/PGMD13 PA26 PA0/PGMNCMD PB7 VDDANA GNDANA AD12BVREF PB4 PA14/PGMD6 PA17/PGMD9 PA20/PGMD12 PA23/PGMD15 PA25 TDO/TRACESWO TDI XOUT32 DFSDP DHSDP GNDPLL PB14 PB19 14 SAM3U Series 6430CS–ATARM–09-Apr-10 SAM3U Series 5. Power Considerations 5.1 Power Supplies The SAM3U product has several types of power supply pins: • VDDCORE pins: Power the core, the embedded memories and the peripherals; voltage ranges from 1.62V to 1.95V. • VDDIO pins: Power the Peripherals I/O lines; voltage ranges from 1.62V to 3.6V. • VDDIN pin: Powers the Voltage regulator • VDDOUT pin: It is the output of the voltage regulator. • VDDBU pin: Powers the Slow Clock oscillator and a part of the System Controller; voltage ranges from 1.62V to 3.6V. VDDBU must be supplied before or at the same time than VDDIO and VDDCORE. • VDDPLL pin: Powers the PLL A, UPLL and 3-20 MHz Oscillator; voltage ranges from 1.62V to 1.95V. • VDDUTMI pin: Powers the UTMI+ interface; voltage ranges from 3.0V to 3.6V, 3.3V nominal. • VDDANA pin: Powers the ADC cells; voltage ranges from 2.0V to 3.6V. Ground pins GND are common to VDDCORE and VDDIO pins power supplies. Separated ground pins are provided for VDDBU, VDDPLL, VDDUTMI and VDDANA. These ground pins are respectively GNDBU, GNDPLL, GNDUTMI and GNDANA. 5.2 Voltage Regulator The SAM3U embeds a voltage regulator that is managed by the Supply Controller. This internal regulator is intended to supply the internal core of SAM3U but can be used to supply other parts in the application. It features two different operating modes: • In Normal mode, the voltage regulator consumes less than 700 µA static current and draws 150 mA of output current. Internal adaptive biasing adjusts the regulator quiescent current depending on the required load current. In Wait Mode or when the output current is low, quiescent current is only 7µA. • In Shutdown mode, the voltage regulator consumes less than 1 µA while its output is driven internally to GND. The default output voltage is 1.80V and the start-up time to reach Normal mode is inferior to 400 µs. For adequate input and output power supply decoupling/bypassing, refer to “Voltage Regulator” in the “Electrical Characteristics” section of the product datasheet. 5.3 Typical Powering Schematics The SAM3U supports a 1.8V-3.6V single supply mode. The internal regulator input connected to the source and its output feed VDDCORE. Figure 5-1, Figure 5-2, Figure 5-3 show the power schematics. 15 6430CS–ATARM–09-Apr-10 Figure 5-1. Single Supply VDDBU VDDUTMI VDDANA VDDIO Main Supply (1.8V-3.6V) VDDIN Voltage Regulator VDDOUT VDDCORE VDDPLL Note: Restrictions With Main Supply < 2.0 V, USB and ADC are not usable. With Main Supply ≥ 2.4V and < 3V, USB is not usable. With Main Supply ≥ 3V, all peripherals are usable. 16 SAM3U Series 6430CS–ATARM–09-Apr-10 SAM3U Series Figure 5-2. Core Externally Supplied VDDBU VDDUTMI VDDANA Main Supply (1.62V-3.6V) VDDIO VDDIN Voltage Regulator VDDOUT VDDCORE Supply (1.62V-1.95V) VDDCORE VDDPLL Note: Restrictions With Main Supply < 2.0 V, USB and ADC are not usable. With Main Supply ≥ 2.4V and < 3V, USB is not usable. With Main Supply ≥ 3V, all peripherals are usable. 17 6430CS–ATARM–09-Apr-10 Figure 5-3. Backup Batteries Used FWUP SHDN Backup Batteries VDDBU VDDUTMI VDDANA VDDIO VDDIN Main Supply (1.62V-3.6V) VDDOUT Voltage Regulator VDDCORE VDDPLL Note: Restrictions With Main Supply < 2.0 V, USB and ADC are not usable. With Main Supply ≥ 2.4V and < 3V, USB is not usable. With Main Supply ≥ 3V, all peripherals are usable. 18 SAM3U Series 6430CS–ATARM–09-Apr-10 SAM3U Series 5.4 Active Mode Active mode is the normal running mode with the core clock running from the fast RC oscillator, the main crystal oscillator or the PLLA. The power management controller can be used to adapt the frequency and to disable the peripheral clocks. 5.5 Low Power Modes The various low power modes of the SAM3U are described below: 5.5.1 Backup Mode The purpose of backup mode is to achieve the lowest power consumption possible in a system which is performing periodic wake-ups to perform tasks but not requiring fast startup time (