ATTINY13_10

Features • High Performance, Low Power AVR® 8-Bit Microcontroller • Advanced RISC Architecture – 120 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 20 MIPS Througput at 20 MHz High Endurance Non-volatile Memory segments – 1K Bytes of In-System Self-programmable Flash program memory – 64 Bytes EEPROM – 64 Bytes Internal SRAM – Write/Erase cyles: 10,000 Flash/100,000 EEPROM – Data retention: 20 years at 85°C/100 years at 25°C (see page 6) – Programming Lock for Self-Programming Flash & EEPROM Data Security Peripheral Features – One 8-bit Timer/Counter with Prescaler and Two PWM Channels – 4-channel, 10-bit ADC with Internal Voltage Reference – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator Special Microcontroller Features – debugWIRE On-chip Debug System – In-System Programmable via SPI Port – External and Internal Interrupt Sources – Low Power Idle, ADC Noise Reduction, and Power-down Modes – Enhanced Power-on Reset Circuit – Programmable Brown-out Detection Circuit – Internal Calibrated Oscillator I/O and Packages – 8-pin PDIP/SOIC: Six Programmable I/O Lines – 20-pad MLF: Six Programmable I/O Lines Operating Voltage: – 1.8 - 5.5V for ATtiny13V – 2.7 - 5.5V for ATtiny13 Speed Grade – ATtiny13V: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V – ATtiny13: 0 - 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V Industrial Temperature Range Low Power Consumption – Active Mode: • 1 MHz, 1.8V: 240 µA – Power-down Mode: • < 0.1 µA at 1.8V • • • 8-bit Microcontroller with 1K Bytes In-System Programmable Flash ATtiny13 ATtiny13V Summary • • • • • Rev. 2535JS–AVR–08/10 1. Pin Configurations Figure 1-1. Pinout ATtiny13/ATtiny13V 8-PDIP/SOIC (PCINT5/RESET/ADC0/dW) PB5 (PCINT3/CLKI/ADC3) PB3 (PCINT4/ADC2) PB4 GND 1 2 3 4 8 7 6 5 VCC PB2 (SCK/ADC1/T0/PCINT2) PB1 (MISO/AIN1/OC0B/INT0/PCINT1) PB0 (MOSI/AIN0/OC0A/PCINT0) 20-QFN/MLF DNC DNC DNC DNC DNC (PCINT5/RESET/ADC0/dW) PB5 (PCINT3/CLKI/ADC3) PB3 DNC DNC (PCINT4/ADC2) PB4 1 2 3 4 5 20 19 18 17 16 15 14 13 12 11 NOTE: Bottom pad should be soldered to ground. DNC: Do Not Connect 10-QFN/MLF (PCINT5/RESET/ADC0/dW) PB5 (PCINT3/CLKI/ADC3) PB3 DNC (PCINT4/ADC2) PB4 GND 1 2 3 4 5 10 9 8 7 6 VCC PB2 (SCK/ADC1/T0/PCINT2) DNC PB1 (MISO/AIN1/OC0B/INT0/PCINT1) PB0 (MOSI/AIN0/OC0A/PCINT0) NOTE: Bottom pad should be soldered to ground. DNC: Do Not Connect 2 ATtiny13 2535JS–AVR–08/10 DNC DNC GND DNC DNC 6 7 8 9 10 VCC PB2 (SCK/ADC1/T0/PCINT2) DNC PB1 (MISO/AIN1/OC0B/INT0/PCINT1) PB0 (MOSI/AIN0/OC0A/PCINT0) ATtiny13 1.1 1.1.1 Pin Descriptions VCC Digital supply voltage. 1.1.2 GND Ground. 1.1.3 Port B (PB5:PB0) Port B is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATtiny13 as listed on page 54. 1.1.4 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 18-1 on page 115. Shorter pulses are not guaranteed to generate a reset. The reset pin can also be used as a (weak) I/O pin. 3 2535JS–AVR–08/10 2. Overview The ATtiny13 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny13 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Figure 2-1. Block Diagram 8-BIT DATABUS STACK POINTER WATCHDOG OSCILLATOR CALIBRATED INTERNAL OSCILLATOR SRAM VCC WATCHDOG TIMER MCU CONTROL REGISTER MCU STATUS REGISTER TIMER/ COUNTER0 TIMING AND CONTROL PROGRAM COUNTER GND PROGRAM FLASH INSTRUCTION REGISTER GENERAL PURPOSE REGISTERS INTERRUPT UNIT PROGRAMMING LOGIC INSTRUCTION DECODER X Y Z CONTROL LINES ALU DATA EEPROM STATUS REGISTER ADC / ANALOG COMPARATOR DATA REGISTER PORT B DATA DIR. REG.PORT B PORT B DRIVERS RESET CLKI PB0-PB5 4 ATtiny13 2535JS–AVR–08/10 ATtiny13 The AVR core combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATtiny13 provides the following features: 1K byte of In-System Programmable Flash, 64 bytes EEPROM, 64 bytes SRAM, 6 general purpose I/O lines, 32 general purpose working registers, one 8-bit Timer/Counter with compare modes, Internal and External Interrupts, a 4channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, and three software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counter, ADC, Analog Comparator, and Interrupt system to continue functioning. The Power-down mode saves the register contents, disabling all chip functions until the next Interrupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize switching noise during ADC conversions. The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI serial interface, by a conventional non-volatile memory programmer or by an On-chip boot code running on the AVR core. The ATtiny13 AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, and Evaluation kits. 5 2535JS–AVR–08/10 3. General Information 3.1 Resources A comprehensive set of drivers, application notes, data sheets and descriptions on development tools are available for download at http://www.atmel.com/avr. 3.2 Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details. 3.3 Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. 6 ATtiny13 2535JS–AVR–08/10 ATtiny13 4. Register Summary Address 0x3F 0x3E 0x3D 0x3C 0x3B 0x3A 0x39 0x38 0x37 0x36 0x35 0x34 0x33 0x32 0x31 0x30 0x2F 0x2E 0x2D 0x2C 0x2B 0x2A 0x29 0x28 0x27 0x26 0x25 0x24 0x23 0x22 0x21 0x20 0x1F 0x1E 0x1D 0x1C 0x1B 0x1A 0x19 0x18 0x17 0x16 0x15 0x14 0x13 0x12 0x11 0x10 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 0x00 Name SREG Reserved SPL Reserved GIMSK GIFR TIMSK0 TIFR0 SPMCSR OCR0A MCUCR MCUSR TCCR0B TCNT0 OSCCAL Reserved TCCR0A DWDR Reserved Reserved Reserved Reserved OCR0B GTCCR Reserved CLKPR Reserved Reserved Reserved Reserved WDTCR Reserved Reserved EEARL EEDR EECR Reserved Reserved Reserved PORTB DDRB PINB PCMSK DIDR0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved ACSR ADMUX ADCSRA ADCH ADCL ADCSRB Reserved Reserved Reserved Bit 7 I – Bit 6 T – Bit 5 H – Bit 4 S – SP[7:0] – Bit 3 V – Bit 2 N – Bit 1 Z – Bit 0 C – Page page 9 page 11 – – – – – – – FOC0A INT0 INTF0 – – – PUD – FOC0B PCIE PCIF – – – SE – – – – – – CTPB SM1 – – – – OCIE0B OCF0B RFLB SM0 WDRF WGM02 – – OCIE0A OCF0A PGWRT – BORF CS02 – – TOIE0 TOV0 PGERS ISC01 EXTRF CS01 – – – – SELFPRISC00 PORF CS00 page 46 page 47 page 74 page 75 page 97 page 74 page 32 page 41 page 72 page 73 page 27 Timer/Counter – Output Compare Register A Timer/Counter (8-bit) Oscillator Calibration Register – COM0A1 COM0A0 COM0B1 COM0B0 DWDR[7:0] – – – – Timer/Counter – Output Compare Register B TSM CLKPCE – – – – – – – – – – – WDTIF WDTIE WDP3 WDCE – – – – – – EEPM1 EEPM0 – – – – – – – – – – – – – PORTB5 DDB5 PINB5 PCINT5 ADC0D PORTB4 DDB4 PINB4 PCINT4 ADC2D – – – – – – – – – – – ACD – ADEN ACBG REFS0 ADSC ACO ADLAR ADATE ACI – ADIF ACIE – ADIE – – ADPS2 ACIS1 MUX1 ADPS1 ACIS0 MUX0 ADPS0 PORTB3 DDB3 PINB3 PCINT3 ADC3D PORTB2 DDB2 PINB2 PCINT2 ADC1D PORTB1 DDB1 PINB1 PCINT1 AIN1D PORTB0 DDB0 PINB0 PCINT0 AIN0D EEPROM Address Register EEPROM Data Register EERIE EEMPE EEPE EERE WDE WDP2 WDP1 WDP0 CLKPS3 CLKPS2 CLKPS1 CLKPS0 – – – PSR10 – – WGM01 WGM00 page 69 page 96 page 74 page 77 page 28 page 41 page 20 page 20 page 21 page 56 page 56 page 57 page 47 page 80, page 94 page 79 page 91 page 92 page 93 page 93 ADC Data Register High Byte ADC Data Register Low Byte – ACME – – – – – – ADTS2 ADTS1 ADTS0 page 94 7 2535JS–AVR–08/10 Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions.ome of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operation the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 8 ATtiny13 2535JS–AVR–08/10 ATtiny13 5. Instruction Set Summary Mnemonics ADD ADC ADIW SUB SUBI SBC SBCI SBIW AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER RJMP IJMP RCALL ICALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC BRIE BRID SBI CBI LSL LSR ROL Rd,Rr Rd,Rr Rd,Rr Rd,K Rr, b Rr, b P, b P, b s, k s, k k k k k k k k k k k k k k k k k k k P,b P,b Rd Rd Rd k Operands Rd, Rr Rd, Rr Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd Rd Rd,K Rd,K Rd Rd Rd Rd Rd BRANCH INSTRUCTIONS k Description Add two Registers Add with Carry two Registers Add Immediate to Word Subtract two Registers Subtract Constant from Register Subtract with Carry two Registers Subtract with Carry Constant from Reg. Subtract Immediate from Word Logical AND Registers Logical AND Register and Constant Logical OR Registers Logical OR Register and Constant Exclusive OR Registers One’s Complement Two’s Complement Set Bit(s) in Register Clear Bit(s) in Register Increment Decrement Test for Zero or Minus Clear Register Set Register Relative Jump Indirect Jump to (Z) Relative Subroutine Call Indirect Call to (Z) Subroutine Return Interrupt Return Compare, Skip if Equal Compare Compare with Carry Compare Register with Immediate Skip if Bit in Register Cleared Skip if Bit in Register is Set Skip if Bit in I/O Register Cleared Skip if Bit in I/O Register is Set Branch if Status Flag Set Branch if Status Flag Cleared Branch if Equal Branch if Not Equal Branch if Carry Set Branch if Carry Cleared Branch if Same or Higher Branch if Lower Branch if Minus Branch if Plus Branch if Greater or Equal, Signed Branch if Less Than Zero, Signed Branch if Half Carry Flag Set Branch if Half Carry Flag Cleared Branch if T Flag Set Branch if T Flag Cleared Branch if Overflow Flag is Set Branch if Overflow Flag is Cleared Branch if Interrupt Enabled Branch if Interrupt Disabled Operation Rd ← Rd + Rr Rd ← Rd + Rr + C Rdh:Rdl ← Rdh:Rdl + K Rd ← Rd - Rr Rd ← Rd - K Rd ← Rd - Rr - C Rd ← Rd - K - C Rdh:Rdl ← Rdh:Rdl - K Rd ← Rd • Rr Rd ← Rd • K Rd ← Rd v Rr Rd ← Rd v K Rd ← Rd ⊕ Rr Rd ← 0xFF − Rd Rd ← 0x00 − Rd Rd ← Rd v K Rd ← Rd • (0xFF - K) Rd ← Rd + 1 Rd ← Rd − 1 Rd ← Rd • Rd Rd ← Rd ⊕ Rd Rd ← 0xFF PC ← PC + k + 1 PC ← Z PC ← PC + k + 1 PC ← Z PC ← STACK PC ← STACK if (Rd = Rr) PC ← PC + 2 or 3 Rd − Rr Rd − Rr − C Rd − K if (Rr(b)=0) PC ← PC + 2 or 3 if (Rr(b)=1) PC ← PC + 2 or 3 if (P(b)=0) PC ← PC + 2 or 3 if (P(b)=1) PC ← PC + 2 or 3 if (SREG(s) = 1) then PC←PC+k + 1 if (SREG(s) = 0) then PC←PC+k + 1 if (Z = 1) then PC ← PC + k + 1 if (Z = 0) then PC ← PC + k + 1 if (C = 1) then PC ← PC + k + 1 if (C = 0) then PC ← PC + k + 1 if (C = 0) then PC ← PC + k + 1 if (C = 1) then PC ← PC + k + 1 if (N = 1) then PC ← PC + k + 1 if (N = 0) then PC ← PC + k + 1 if (N ⊕ V= 0) then PC ← PC + k + 1 if (N ⊕ V= 1) then PC ← PC + k + 1 if (H = 1) then PC ← PC + k + 1 if (H = 0) then PC ← PC + k + 1 if (T = 1) then PC ← PC + k + 1 if (T = 0) then PC ← PC + k + 1 if (V = 1) then PC ← PC + k + 1 if (V = 0) then PC ← PC + k + 1 if ( I = 1) then PC ← PC + k + 1 if ( I = 0) then PC ← PC + k + 1 I/O(P,b) ← 1 I/O(P,b) ← 0 Rd(n+1) ← Rd(n), Rd(0) ← 0 Rd(n) ← Rd(n+1), Rd(7) ← 0 Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7) Flags Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None None None None None None I None Z, N,V,C,H Z, N,V,C,H Z, N,V,C,H None None None None None None None None None None None None None None None None None None None None None None None None None None Z,C,N,V Z,C,N,V Z,C,N,V #Clocks 1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 3 3 4 4 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 2 2 1 1 1 ARITHMETIC AND LOGIC INSTRUCTIONS BIT AND BIT-TEST INSTRUCTIONS Set Bit in I/O Register Clear Bit in I/O Register Logical Shift Left Logical Shift Right Rotate Left Through Carry 9 2535JS–AVR–08/10 Mnemonics ROR ASR SWAP BSET BCLR BST BLD SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH CLH MOV MOVW LDI LD LD LD LD LD LD LDD LD LD LD LDD LDS ST ST ST ST ST ST STD ST ST ST STD STS LPM LPM LPM SPM IN OUT PUSH POP NOP SLEEP WDR BREAK Operands Rd Rd Rd s s Rr, b Rd, b Description Rotate Right Through Carry Arithmetic Shift Right Swap Nibbles Flag Set Flag Clear Bit Store from Register to T Bit load from T to Register Set Carry Clear Carry Set Negative Flag Clear Negative Flag Set Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Set Signed Test Flag Clear Signed Test Flag Set Twos Complement Overflow. Clear Twos Complement Overflow Set T in SREG Clear T in SREG Set Half Carry Flag in SREG Clear Half Carry Flag in SREG Operation Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Rd(n) ← Rd(n+1), n=0..6 Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0) SREG(s) ← 1 SREG(s) ← 0 T ← Rr(b) Rd(b) ← T C←1 C←0 N←1 N←0 Z←1 Z←0 I←1 I←0 S←1 S←0 V←1 V←0 T←1 T←0 H←1 H←0 Rd ← Rr Rd+1:Rd ← Rr+1:Rr Rd ← K Rd ← (X) Rd ← (X), X ← X + 1 X ← X - 1, Rd ← (X) Rd ← (Y) Rd ← (Y), Y ← Y + 1 Y ← Y - 1, Rd ← (Y) Rd ← (Y + q) Rd ← (Z) Rd ← (Z), Z ← Z+1 Z ← Z - 1, Rd ← (Z) Rd ← (Z + q) Rd ← (k) (X) ← Rr (X) ← Rr, X ← X + 1 X ← X - 1, (X) ← Rr (Y) ← Rr (Y) ← Rr, Y ← Y + 1 Y ← Y - 1, (Y) ← Rr (Y + q) ← Rr (Z) ← Rr (Z) ← Rr, Z ← Z + 1 Z ← Z - 1, (Z) ← Rr (Z + q) ← Rr (k) ← Rr R0 ← (Z) Rd ← (Z) Rd ← (Z), Z ← Z+1 (z) ← R1:R0 Rd ← P P ← Rr STACK ← Rr Rd ← STACK Flags Z,C,N,V Z,C,N,V None SREG(s) SREG(s) T None C C N N Z Z I I S S V V T T H H None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None #Clocks 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 1 1 2 2 1 1 1 N/A DATA TRANSFER INSTRUCTIONS Rd, Rr Rd, Rr Rd, K Rd, X Rd, X+ Rd, - X Rd, Y Rd, Y+ Rd, - Y Rd,Y+q Rd, Z Rd, Z+ Rd, -Z Rd, Z+q Rd, k X, Rr X+, Rr - X, Rr Y, Rr Y+, Rr - Y, Rr Y+q,Rr Z, Rr Z+, Rr -Z, Rr Z+q,Rr k, Rr Rd, Z Rd, Z+ Rd, P P, Rr Rr Rd Move Between Registers Copy Register Word Load Immediate Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Direct from SRAM Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Direct to SRAM Load Program Memory Load Program Memory Load Program Memory and Post-Inc Store Program Memory In Port Out Port Push Register on Stack Pop Register from Stack MCU CONTROL INSTRUCTIONS No Operation Sleep Watchdog Reset Break (see specific descr. for Sleep function) (see specific descr. for WDR/Timer) For On-chip Debug Only None None None 10 ATtiny13 2535JS–AVR–08/10 ATtiny13 6. Ordering Information Speed (MHz) (3) Power Supply (V) Ordering Code (4) ATtiny13V-10PU ATtiny13V-10SU ATtiny13V-10SUR ATtiny13V-10SSU ATtiny13V-10SSUR ATtiny13V-10MU ATtiny13V-10MUR ATtiny13V-10MMU ATtiny13V-10MMUR ATtiny13-20PU ATtiny13-20SU ATtiny13-20SUR ATtiny13-20SSU ATtiny13-20SSUR ATtiny13-20MU ATtiny13-20MUR ATtiny13-20MMU ATtiny13-20MMUR Package (2) 8P3 8S2 8S2 S8S1 S8S1 20M1 20M1 10M1 10M1 8P3 8S2 8S2 S8S1 S8S1 20M1 20M1 10M1 10M1 Operation Range 10 1.8 - 5.5 Industrial (-40°C to +85°C)(1) 20 2.7 - 5.5 Industrial (-40°C to +85°C)(1) Notes: 1. These devices can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazardous Substances (RoHS). 3. For Speed vs. VCC, see “Speed Grades” on page 117. 4. Code indicators: – U: matte tin – R: tape & reel Package Type 8P3 8S2 S8S1 20M1 10M1 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8-lead, 0.209" Wide, Plastic Small Outline Package (EIAJ SOIC) 8-lead, 0.150" Wide, Plastic Gull-Wing Small Outline (JEDEC SOIC) 20-pad, 4 x 4 x 0.8 mm Body, Lead Pitch 0.50 mm, Micro Lead Frame Package (MLF) 10-pad, 3 x 3 x 1 mm Body, Lead Pitch 0.50 mm, Micro Lead Frame Package (MLF) 11 2535JS–AVR–08/10 7. Packaging Information 7.1 8P3 1 E E1 N Top View c eA End View D e D1 A2 A SYMBOL COMMON DIMENSIONS (Unit of Measure = inches) MIN NOM MAX NOTE A A2 b b2 b3 c D 0.115 0.014 0.045 0.030 0.008 0.355 0.005 0.300 0.240 0.310 0.250 0.100 BSC 0.300 BSC 0.115 0.130 0.130 0.018 0.060 0.039 0.010 0.365 0.210 0.195 0.022 0.070 0.045 0.014 0.400 2 5 6 6 3 3 b2 b3 4 PLCS L D1 E E1 e eA L b 0.325 0.280 4 3 Side View 4 0.150 2 Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information. 2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3. 3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch. 4. E and eA measured with the leads constrained to be perpendicular to datum. 5. Pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm). 01/09/02 2325 Orchard Parkway San Jose, CA 95131 TITLE 8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP) DRAWING NO. 8P3 REV. B R 12 ATtiny13 2535JS–AVR–08/10 ATtiny13 7.2 8S2 C 1 E E1 L N TOP VIEW e A SYMBOL θ END VIEW b COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX NOTE A1 A A1 b C 1.70 0.05 0.35 0.15 5.13 5.18 7.70 0.51 0° 1.27 BSC 2.16 0.25 0.48 0.35 5.35 5.40 8.26 0.85 8° 3 2 4 4 D D E1 E SIDE VIEW Notes: 1. 2. 3. 4. L θ e This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. Mismatch of the upper and lower dies and resin burrs aren't included. Determines the true geometric position. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm. Package Drawing Contact: packagedrawings@atmel.com TITLE 8S2, 8-lead, 0.208” Body, Plastic Small Outline Package (EIAJ) GPC STN 4/15/08 DRAWING NO. REV. 8S2 F 13 2535JS–AVR–08/10 7.3 S8S1 3 2 1 H N Top View e B A D Side View SYMBOL A COMMON DIMENSIONS (Unit of Measure = mm) MIN – – – – – NOM – – – – – 1.27 BSC – – – – 6.20 1.27 MAX 1.75 0.51 0.25 5.00 4.00 NOTE A2 B C C D E L E e H L End View Note: This drawing is for general information only. Refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums, etc. 10/10/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) DRAWING NO. 8S1 REV. A R 14 ATtiny13 2535JS–AVR–08/10 ATtiny13 7.4 20M1 D 1 Pin 1 ID 2 3 E SIDE VIEW TOP VIEW A2 D2 A1 A 1 Pin #1 Notch (0.20 R) 2 3 0.08 C E2 SYMBOL A A1 COMMON DIMENSIONS (Unit of Measure = mm) MIN 0.70 – NOM 0.75 0.01 0.20 REF 0.18 0.23 4.00 BSC 2.45 2.60 4.00 BSC 2.45 2.60 0.50 BSC 0.35 0.40 0.55 2.75 2.75 0.30 MAX 0.80 0.05 NOTE b L e BOTTOM VIEW A2 b D D2 E E2 e Note: Reference JEDEC Standard MO-220, Fig. 1 (SAW Singulation) WGGD-5. L 10/27/04 2325 Orchard Parkway San Jose, CA 95131 TITLE 20M1, 20-pad, 4 x 4 x 0.8 mm Body, Lead Pitch 0.50 mm, 2.6 mm Exposed Pad, Micro Lead Frame Package (MLF) DRAWING NO. 20M1 REV. A R 15 2535JS–AVR–08/10 7.5 10M1 D Pin 1 ID y E SIDE VIEW TOP VIEW A A1 D1 K 1 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN 0.80 0.00 0.18 2.90 1.40 2.90 2.20 NOM 0.90 0.02 0.25 3.00 – 3.00 – 0.50 0.30 – 0.20 – – – 0.50 0.08 – MAX 1.00 0.05 0.30 3.10 1.75 3.10 2.70 NOTE 2 A A1 b E1 b D D1 e E E1 e L BOTTOM VIEW L y K Notes: 1. This package conforms to JEDEC reference MO-229C, Variation VEED-5. 2. The terminal #1 ID is a Lasser-marked Feature. 7/7/06 DRAWING NO. 10M1 REV. A R TITLE 2325 Orchard Parkway 10M1, 10-pad, 3 x 3 x 1.0 mm Body, Lead Pitch 0.50 mm, San Jose, CA 95131 1.64 x 2.60 mm Exposed Pad, Micro Lead Frame Package 16 ATtiny13 2535JS–AVR–08/10 ATtiny13 8. Errata The revision letter in this section refers to the revision of the ATtiny13 device. 8.1 ATtiny13 Rev. D • EEPROM can not be written below 1.9 Volt 1. EEPROM can not be written below 1.9 Volt Writing the EEPROM at VCC below 1.9 volts might fail. Problem Fix/Workaround Do not write the EEPROM when VCC is below 1.9 volts. 8.2 8.3 ATtiny13 Rev. C Revision C has not been sampled. ATtiny13 Rev. B • • • • • • Wrong values read after Erase Only operation High Voltage Serial Programming Flash, EEPROM, Fuse and Lock Bits may fail Device may lock for further programming debugWIRE communication not blocked by lock-bits Watchdog Timer Interrupt disabled EEPROM can not be written below 1.9 Volt 8.3.1 Wrong values read after Erase Only operation At supply voltages below 2.7 V, an EEPROM location that is erased by the Erase Only operation may read as programmed (0x00). Problem Fix/Workaround If it is necessary to read an EEPROM location after Erase Only, use an Atomic Write operation with 0xFF as data in order to erase a location. In any case, the Write Only operation can be used as intended. Thus no special considerations are needed as long as the erased location is not read before it is programmed. 8.3.2 High Voltage Serial Programming Flash, EEPROM, Fuse and Lock Bits may fail Writing to any of these locations and bits may in some occasions fail. Problem Fix/Workaround After a writing has been initiated, always observe the RDY/BSY signal. If the writing should fail, rewrite until the RDY/BSY verifies a correct writing. This will be fixed in revision D. 8.3.3 Device may lock for further programming Special combinations of fuse bits will lock the device for further programming effectively turning it into an OTP device. The following combinations of settings/fuse bits will cause this effect: – 128 kHz internal oscillator (CKSEL[1..0] = 11), shortest start-up time (SUT[1..0] = 00), Debugwire enabled (DWEN = 0) or Reset disabled RSTDISBL = 0. – 9.6 MHz internal oscillator (CKSEL[1..0] = 10), shortest start-up time (SUT[1..0] = 00), Debugwire enabled (DWEN = 0) or Reset disabled RSTDISBL = 0. 17 2535JS–AVR–08/10 – 4.8 MHz internal oscillator (CKSEL[1..0] = 01), shortest start-up time (SUT[1..0] = 00), Debugwire enabled (DWEN = 0) or Reset disabled RSTDISBL = 0. Problem fix/ Workaround Avoid the above fuse combinations. Selecting longer start-up time will eliminate the problem. 8.3.4 debugWIRE communication not blocked by lock-bits When debugWIRE on-chip debug is enabled (DWEN = 0), the contents of program memory and EEPROM data memory can be read even if the lock-bits are set to block further reading of the device. Problem fix/ Workaround Do not ship products with on-chip debug of the tiny13 enabled. 8.3.5 Watchdog Timer Interrupt disabled If the watchdog timer interrupt flag is not cleared before a new timeout occurs, the watchdog will be disabled, and the interrupt flag will automatically be cleared. This is only applicable in interrupt only mode. If the Watchdog is configured to reset the device in the watchdog timeout following an interrupt, the device works correctly. Problem fix / Workaround Make sure there is enough time to always service the first timeout event before a new watchdog timeout occurs. This is done by selecting a long enough time-out period. 8.3.6 EEPROM can not be written below 1.9 Volt Writing the EEPROM at VCC below 1.9 volts might fail. Problem Fix/Workaround Do not write the EEPROM when VCC is below 1.9 volts. 8.4 ATtiny13 Rev. A Revision A has not been sampled. 18 ATtiny13 2535JS–AVR–08/10 ATtiny13 9. Datasheet Revision History Please note that the referring page numbers in this section refer to the complete document. 9.1 Rev. 2535J-08/10 Added tape and reel part numbers in “Ordering Information” on page 160. Removed text “Not recommended for new design” from cover page. Updated last page. 9.2 Rev. 2535I-05/08 1. Updated document template, layout and paragraph formats. 2. Updated “Features” on page 1. 3. Created Sections: – “Calibrated Internal RC Oscillator Accuracy” on page 118 – “Analog Comparator Characteristics” on page 119 4. Updated Sections: – “System Clock and Clock Options” on page 23 – “Calibrated Internal 4.8/9.6 MHz Oscillator” on page 25 – “External Interrupts” on page 45 – “Analog Noise Canceling Techniques” on page 88 – “Limitations of debugWIRE” on page 96 – “Reading Fuse and Lock Bits from Firmware” on page 99 – “Fuse Bytes” on page 103 – “Calibration Bytes” on page 104 – “High-Voltage Serial Programming” on page 108 – “Ordering Information” on page 160 5. Updated Figure: – “Analog Input Circuitry” on page 87 – “High-voltage Serial Programming Timing” on page 122 6. Moved Figures: – “Serial Programming Timing” on page 121 – “Serial Programming Waveform” on page 121 – “High-voltage Serial Programming Timing” on page 122 7. Updated Tables: – “DC Characteristics, TA = -40°C to +85°C” on page 115 – “Serial Programming Characteristics, TA = -40°C to +85°C, VCC = 1.8 - 5.5V (Unless Otherwise Noted)” on page 121 8. Moved Tables: – “Serial Programming Instruction Set” on page 107 – “Serial Programming Characteristics, TA = -40°C to +85°C, VCC = 1.8 - 5.5V (Unless Otherwise Noted)” on page 121 – “High-voltage Serial Programming Characteristics TA = 25°C, VCC = 5.0V ± 10% (Unless otherwise noted)” on page 122 9. Updated Register Description for Sections: 19 2535JS–AVR–08/10 – “TCCR0A – Timer/Counter Control Register A” on page 69 – “DIDR0 – Digital Input Disable Register 0” on page 94 10. Updated description in Step 1. on page 106. 11. Changed device status to “Not Recommended for New Designs”. 9.3 Rev. 2535H-10/07 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. Updated “Features” on page 1. Updated “Pin Configurations” on page 2. Added “Data Retention” on page 6. Updated “Assembly Code Example(1)” on page 39. Updated Table 21 in “Alternate Functions of Port B” on page 54. Updated Bit 5 description in “GIMSK – General Interrupt Mask Register” on page 46. Updated “ADC Voltage Reference” on page 87. Updated “Calibration Bytes” on page 104. Updated “Read Calibration Byte” on page 108. Updated Table 51 in “Serial Programming Characteristics” on page 121. Updated Algorithm in “High-Voltage Serial Programming Algorithm” on page 109. Updated “Read Calibration Byte” on page 112. Updated values in “External Clock Drive” on page 118. Updated “Ordering Information” on page 160. Updated “Packaging Information” on page 161. 9.4 Rev. 2535G-01/07 1. 2. 3. 4. 5. 6. 7. 8. 9. Removed Preliminary. Updated Table 7-1 on page 30, Table 8-1 on page 42,Table 18-8 on page 121. Removed Note from Table 7-1 on page 30. Updated “Bit 6 – ACBG: Analog Comparator Bandgap Select” on page 79. Updated “Prescaling and Conversion Timing” on page 83. Updated Figure 18-4 on page 121. Updated “DC Characteristics” on page 115. Updated “Ordering Information” on page 160. Updated “Packaging Information” on page 161. 9.5 Rev. 2535F-04/06 1. Revision not published. 9.6 Rev. 2535E-10/04 1. 2. 3. 2. 4. 5. 6. 7. Bits EEMWE/EEWE changed to EEMPE/EEPE in document. Updated “Pinout ATtiny13/ATtiny13V” on page 2. Updated “Write Fuse Low Bits” in Table 17-13 on page 110, Table 18-3 on page 118. Added “Pin Change Interrupt Timing” on page 45. Updated “GIMSK – General Interrupt Mask Register” on page 46. Updated “PCMSK – Pin Change Mask Register” on page 47. Updated item 4 in “Serial Programming Algorithm” on page 106. Updated “High-Voltage Serial Programming Algorithm” on page 109. 20 ATtiny13 2535JS–AVR–08/10 ATtiny13 8. 9. 10. 11. 12. Updated “DC Characteristics” on page 115. Updated “Typical Characteristics” on page 122. Updated “Ordering Information” on page 160. Updated “Packaging Information” on page 161. Updated “Errata” on page 166. 9.7 Rev. 2535D-04/04 1. 2. 3. 4. Maximum Speed Grades changed: 12MHz to 10MHz, 24MHz to 20MHz Updated “Serial Programming Instruction Set” on page 107. Updated “Speed Grades” on page 117 Updated “Ordering Information” on page 160 9.8 Rev. 2535C-02/04 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. C-code examples updated to use legal IAR syntax. Replaced occurrences of WDIF with WDTIF and WDIE with WDTIE. Updated “Stack Pointer” on page 11. Updated “Calibrated Internal 4.8/9.6 MHz Oscillator” on page 25. Updated “OSCCAL – Oscillator Calibration Register” on page 27. Updated typo in introduction on “Watchdog Timer” on page 37. Updated “ADC Conversion Time” on page 86. Updated “Serial Programming” on page 105. Updated “Electrical Characteristics” on page 115. Updated “Ordering Information” on page 160. Removed rev. C from “Errata” on page 166. 9.9 Rev. 2535B-01/04 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. Updated Figure 2-1 on page 4. Updated Table 7-1, Table 8-1, Table 14-2 and Table 18-3. Updated “Calibrated Internal 4.8/9.6 MHz Oscillator” on page 25. Updated the whole “Watchdog Timer” on page 37. Updated Figure 17-1 on page 105 and Figure 17-2 on page 108. Updated registers “MCUCR – MCU Control Register”, “TCCR0B – Timer/Counter Control Register B” and “DIDR0 – Digital Input Disable Register 0”. Updated Absolute Maximum Ratings and DC Characteristics in “Electrical Characteristics” on page 115. Added “Speed Grades” on page 117 Updated “” on page 120. Updated “Typical Characteristics” on page 123. Updated “Ordering Information” on page 160. Updated “Packaging Information” on page 161. Updated “Errata” on page 166. Changed instances of EEAR to EEARL. 9.10 Rev. 2535A-06/03 1. Initial Revision. 21 2535JS–AVR–08/10 Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 International Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Product Contact Web Site www.atmel.com Technical Support Enter Product Line E-mail Sales Contact www.atmel.com/contacts Literature Requests www.atmel.com/literature Disclaimer: T he information in this document is provided in connection with Atmel products. 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