ATTINY22L-1SI

Features • Utilizes the AVR® RISC Architecture • AVR - High-performance and Low-power RISC Architecture – 118 Powerful Instructions - Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Up to 1MIPS Throughput at 1MHz Data and Nonvolatile Program Memory – 2K Bytes of In-System Programmable Flash Endurance 1,000 Write/Erase Cycles – 128 Bytes of internal SRAM – 128 Bytes of In-System Programmable EEPROM Endurance: 100,000 Write/Erase Cycles – Programming Lock for Flash Program and EEPROM Data Security Peripheral Features – One 8-bit Timer/Counter with Separate Prescaler – Programmable Watchdog Timer with On-chip Oscillator – SPI Serial Interface for In-System Programming Special Microcontroller Features – Low-power Idle and Power Down Modes – External and Internal Interrupt Sources – Power-on Reset Circuit – On-chip RC Oscillator Specifications – Low-power, High-speed CMOS Process Technology – Fully Static Operation Power Consumption at 3V, 25°C – Active: 1.5 mA – Idle Mode: 100 µA – Power Down Mode: 2 MCU clock cycles High: > 2 MCU clock cycles 38 ATtiny22L ATtiny22L Low-Voltage Serial Programming Algorithm When writing serial data to the ATtiny22L, data is clocked on the rising edge of SCK. When reading data from the ATtiny22L, data is clocked on the falling edge of SCK. See Figure 33, Figure 34 and Table 18 for timing details. To program and verify the ATtiny22L in the Low-Voltage Serial Programming mode, the following sequence is recommended (see four byte instruction formats in Table 17 ): 1. Power-up sequence: Apply power between VCC and GND while RESET and SCK are set to “0” (if the programmer can not guarantee that SCK is held low during power-up, RESET must be given a positive pulse after SCK has been set to “0”). 2. Wait for at least 20 ms and enable serial programming by sending the Programming Enable serial instruction to the MOSI (PB0) pin. Refer to the above section for minimum low and high periods for the serial clock input, SCK. 3. The serial programming instructions will not work if the communication is out of synchronization. When in sync, the second byte ($53) will echo back when issuing the third byte of the Programming Enable instruction. Whether the echo is correct or not, all 4 bytes of the instruction must be transmitted. If the $53 did not echo back, give SCK a positive pulse and issue a new Programming Enable instruction. If the $53 is not seen within 32 attempts, there is no functional device connected. 4. If a Chip Erase is performed (must be done to erase the Flash), wait tWD_ERASE after the instruction, give RESET a positive pulse, and start over from Step 2. See Table 19 on page 42 for tWD_ERASE value. 5. The Flash or EEPROM array is programmed one byte at a time by supplying the address and data together with the appropriate Write instruction. An EEPROM memory location is first automatically erased before new data is written. Use Data Polling to detect when the next byte in the Flash or EEPROM can be written. If polling is not used, wait tWD_PROG before transmitting the next instruction. See Table 20 on page 42 for tWD_PROG value. In an erased device, no $FFs in the data file(s) needs to be programmed. 6. Any memory location can be verified by using the Read instruction which returns the content at the selected address at the serial output MISO (PB1) pin. 7. At the end of the programming session, RESET can be set high to commence normal operation. 8. Power-off sequence (if needed): Set RESET to “0”. Turn VCC power off. 39 Data Polling EEPROM When a byte is being programmed into the EEPROM, reading the address location being programmed will give the value P1 until the auto-erase is finished, and then the value P2. See Table 16 for P1 and P2 values. At the time the device is ready for a new EEPROM byte, the programmed value will read correctly. This is used to determine when the next byte can be written. This will not work for the values P1 and P2, so when programming these values, the user will have to wait for at least the prescribed time tWD_PROG before programming the next byte. See Table 19 for tWD_PROG value. As a chip-erased device contains $FF in all locations, programming of addresses that are meant to contain $FF, can be skipped. This does not apply if the EEPROM is reprogrammed without first chip-erasing the device. Table 16. Read back value during EEPROM polling Part P1 $00 P2 $FF ATtiny22L Data Polling Flash When a byte is being programmed into the Flash, reading the address location being programmed will give the value $FF. At the time the device is ready for a new byte, the programmed value will read correctly. This is used to determine when the next byte can be written. This will not work for the value $FF, so when programming this value, the user will have to wait for at least tWD_PROG before programming the next byte. As a chip-erased device contains $FF in all locations, programming of addresses that are meant to contain $FF, can be skipped. Figure 33. Low-Voltage Serial Downloading Waveforms SERIAL DATA INPUT PB0(MOSI) SERIAL DATA OUTPUT PB1(MISO) SERIAL CLOCK INPUT PB2(SCK) MSB LSB MSB LSB 40 ATtiny22L ATtiny22L Table 17. Low-Voltage Serial Programming Instruction Set ATtiny22L Instruction Format Instruction Programming Enable Chip Erase Read Program Memory Write Program Memory Read EEPROM Memory Write EEPROM Memory Read Lock and Fuse Bit Write Lock Bits Read Signature Bytes Note: Byte 1 1010 1100 1010 1100 0010 H000 Byte 2 0101 0011 100x xxxx 0000 00aa Byte 3 xxxx xxxx xxxx xxxx bbbb bbbb Byte 4 xxxx xxxx xxxx xxxx oooo oooo Operation Enable Serial Programming while RESET is low. Chip erase both Flash and EEPROM memory arrays. Read H (high or low) data o from Program memory at word address a:b. Write H (high or low) data i to Program memory at word address a:b. Read data o from EEPROM memory at address b. Write data i to EEPROM memory at address b. Read Lock and Fuse bit. ‘0’ = programmed, ‘1’ = unprogrammed. Write Lock bits. Set bits 1,2 = ‘0’ to program Lock bits. Read Signature byte o from address b(1) 0100 H000 0000 00aa bbbb bbbb iiii iiii 1010 0000 1100 0000 0101 1000 1010 1100 0011 0000 0000 0000 0000 0000 xxxx xxxx 1111 1211 xxxx xxxx xbbb bbbb xbbb bbbb xxxx xxxx xxxx xxxx xxxx xxbb oooo oooo iiii iiii 12Sx xxx0 xxxx xxxx oooo oooo a = address high bits b = address low bits H = 0 - Low byte, 1- High byte o = data out i = data in x = don’t care 1 = lock bit 1 2 = lock bit 2 S = SPIEN Fuse 1. The signature bytes are not readable in Lock mode 3, i.e. both Lock bits programmed. Notes: 41 Low-Voltage Serial Programming Characteristics Figure 34. Low-voltage Serial Programming Timing MOSI tOVSH SCK MISO tSLIV tSHSL tSHOX tSLSH Table 18. Low-voltage Serial Programming Characteristics TA = -40°C to 85°C, VCC = 2.7 - 6.0V (Unless otherwise noted) The period of the internal RC oscillator - tCLCL is voltage dependend as shown in “Typical characteristics” on page 44. Symbol tSHSL tSLSH tOVSH tSHOX tSLIV Parameter SCK Pulse Width High SCK Pulse Width Low MOSI Setup to SCK High MOSI Hold after SCK High SCK Low to MISO Valid Min 2 tCLCL 2 tCLCL tCLCL 2 tCLCL 10 16 32 Typ Max Units ns ns ns ns ns Table 19. Minimum wait delay after the Chip Erase instruction Symbol tWD_ERASE 3.2V 18 3.6V 14 4.0V 12 5.0V 8 Units ms Table 20. Minimum wait delay after writing a Flash or EEPROM location Symbol tWD_PROG 3.2V 9 3.6V 7 4.0V 6 5.0V 4 Units ms 42 ATtiny22L ATtiny22L Electrical Characteristics Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-1.0V to VCC+0.5V Voltage on RESET with respect to Ground......-1.0V to +13.0V Maximum Operating Voltage ............................................ 6.6V DC Current per I/O Pin ............................................... 40.0 mA DC Current VCC and GND Pins................................ 200.0 mA *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Characteristics TA = -40°C to 85°C, VCC = 2.7V to 6.0V (unless otherwise noted) Symbol VIL VIH VIH2 VOL VOH IIL IIH RRST RI/O ICC Parameter Input Low Voltage Input High Voltage Input High Voltage Output Low Voltage Ports B Output High Voltage Ports B Input Leakage Current I/O Pin Input Leakage Current I/O Pin Reset Pullup I/O Pin Pullup Power Supply Current Active, VCC = 3V Idle, VCC = 3V Power Down, VCC = 3V WDT Enabled Power Down, VCC = 3V WDT Disabled Notes: 1. “Max” means the highest value where the pin is guaranteed to be read as low 2. “Min” means the lowest value where the pin is guaranteed to be read as high 3. Minimum VCC for Power Down is 2V. (Except RESET) RESET IOL = 20 mA, VCC = 5V IOL = 10 mA, VCC = 3V IOH = -3 mA, VCC = 5V IOH = -1.5 mA, VCC = 3V VCC = 6V, Pin Low (Absolute value) VCC = 6V, Pin High (Absolute value) 100 30 4.2 2.4 8.0 8.0 500 150 1.5 100 25.0 20.0 Condition Min -0.5 0.6 VCC (2) Typ Max 0.3 VCC (1) Units V V V V V V V µA µA kΩ kΩ mA µA µA µA VCC + 0.5 VCC + 0.5 0.5 0.4 0.85 VCC(2) 43 Typical characteristics The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. The current consumption is a function of several factors such as: operating voltage, operating frequency, loading of I/O pins, switching rate of I/O pins, code executed and ambient temperature. The dominating factor is the operating voltage, as the frequency of ATtiny22L is also a function of the operationg voltage. The current drawn from capacitive loaded pins may be estimated (for one pin) as CL x VCC x f where CL = load capacitance, VCC = operating voltage and f = average switching frequency of I/O pin. Figure 35. Active Supply Current vs. VCC ACTIVE SUPPLY CURRENT vs. Vcc 7 6 TA = 25˚C 5 TA = 85˚C I cc(mA) 4 3 2 1 0 2 2.5 3 3.5 4 Vcc(V) 4.5 5 5.5 6 44 ATtiny22L ATtiny22L Figure 36. Idle Supply Current vs. VCC IDLE SUPPLY CURRENT vs. Vcc 0.8 0.7 TA = 25˚C 0.6 0.5 I cc(mA) TA = 85˚C 0.4 0.3 0.2 0.1 0 2 2.5 3 3.5 4 Vcc(V) 4.5 5 5.5 6 Figure 37. Power Down Supply Current vs. VCC POWER DOWN SUPPLY CURRENT vs. Vcc WATCHDOG TIMER DISABLED 25 TA = 85˚C 20 15 I cc(µΑ) TA = 70˚C 10 5 TA = 45˚C TA = 25˚C 0 2 2.5 3 3.5 Vcc(V) 4 4.5 5 5.5 6 45 Figure 38. Power Down Supply Current vs. VCC POWER DOWN SUPPLY CURRENT vs. Vcc WATCHDOG TIMER ENABLED 180 160 TA = 85˚C 140 120 I cc(µΑ) TA = 25˚C 100 80 60 40 20 0 2 2.5 3 3.5 4 Vcc(V) 4.5 5 5.5 6 Figure 39. Oscillator Frequency vs. VCC RC OSCILLATOR FREQUENCY vs. Vcc 1600 TA = 25˚C 1400 1200 1000 800 600 400 200 0 2 2.5 3 3.5 4 Vcc (V) TA = 85˚C F RC (KHz) 4.5 5 5.5 6 Note: The frequency of the RC-oscillator may be ±10% off the typical value for a given temperature and VCC. 46 ATtiny22L ATtiny22L Sink and source capabilities of I/O ports are measured on one pin at a time. Figure 40. Pull-Up Resistor Current vs. Input Voltage PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 5V 120 TA = 25˚C 100 TA = 85˚C 80 OP (µA) I 60 40 20 0 0 0.5 1 1.5 2 2.5 VOP (V) 3 3.5 4 4.5 5 Figure 41. Pull-Up Resistor Current vs. Input Voltage PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE Vcc = 2.7V 30 TA = 25˚C 25 TA = 85˚C 20 OP (µA) 15 I 10 5 0 0 0.5 1 1.5 VOP (V) 2 2.5 3 47 Figure 42. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 5V 70 60 TA = 85˚C TA = 25˚C 50 40 OL (mA) 30 20 10 0 0 0.5 1 1.5 VOL (V) 2 2.5 3 Figure 43. I/O PIn Source Current vs. Output Voltage I I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 5V 20 18 16 14 12 OH (mA) TA = 25˚C TA = 85˚C 10 8 6 4 2 0 0 0.5 1 1.5 2 2.5 VOH (V) 3 3.5 4 4.5 5 I 48 ATtiny22L ATtiny22L Figure 44. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7V 25 TA = 25˚C 20 TA = 85˚C 15 OL (mA) 10 I 5 0 0 0.5 1 VOL (V) 1.5 2 Figure 45. I/O Pin Source Current vs. Output voltage I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE Vcc = 2.7V 6 TA = 25˚C 5 TA = 85˚C 4 OH (mA) 3 I 2 1 0 0 0.5 1 1.5 VOH (V) 2 2.5 3 49 Figure 46. I/O Pin Input Threshold Voltage vs. VCC I/O PIN INPUT THRESHOLD VOLTAGE vs. Vcc TA = 25˚C 2.5 2 Threshold Voltage (V) 1.5 1 0.5 0 2.7 4.0 Vcc 5.0 Figure 47. I/O Pin Input Hysteresis vs. VCC I/O PIN INPUT HYSTERESIS vs. Vcc TA = 25˚C 0.18 0.16 0.14 Input hysteresis (V) 0.12 0.1 0.08 0.06 0.04 0.02 0 2.7 4.0 Vcc 5.0 50 ATtiny22L ATtiny22L Register Summary Address $3F ($5F) $3E ($5E) $3D ($5D) $3C ($5C) $3B ($5B) $3A ($5A) $39 ($59) $38 ($58) $37 ($57) $36 ($56) $35 ($55) $34 ($54) $33 ($53) $32 ($52) $31 ($51) $30 ($50) $2F ($4F) $2E ($4E) $2D ($4D) $2C ($4C) $2B ($4B) $2A ($4A) $29 ($49) $28 ($48) $27 ($47) $26 ($46) $25 ($45) $24 ($44) $23 ($43) $22 ($42) $21 ($41) $20 ($40) $1F ($3F) $1E ($3E) $1D ($3D) $1C ($3C) $1B ($3B) $1A ($3A) $19 ($39) $18 ($38) $17 ($37) $16 ($36) $15 ($35) … $00 ($20) Name SREG Reserved SPL Reserved GIMSK GIFR TIMSK TIFR Reserved Reserved MCUCR MCUSR TCCR0 TCNT0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved WDTCR Reserved Reserved EEAR EEDR EECR Reserved Reserved Reserved PORTB DDRB PINB Reserved Reserved Reserved Bit 7 I SP7 - Bit 6 T SP6 INT0 INTF0 - Bit 5 H SP5 - Bit 4 S SP4 - Bit 3 V SP3 - Bit 2 N SP2 - Bit 1 Z SP1 TOIE0 TOV0 Bit 0 C SP0 - Page page 16 page 17 page 23 page 23 page 23 page 24 Timer/Counter0 (8 Bit) SE - SM - - CS02 ISC01 EXTRF CS01 ISC00 PORF CS00 page 24 page 22 page 27 page 28 - - - WDTOE WDE WDP2 WDP1 WDP0 page 28 EEPROM Address Register EEPROM Data register - - EEMW EEWE EERE page 30 page 30 page 30 - - - PORTB DDB4 PINB4 PORTB DDB3 PINB3 PORTB DDB2 PINB2 PORTB DDB1 PINB1 PORTB DDB0 PINB0 page 32 page 32 page 32 Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only. 51 Instruction Set Summary Mnemonics Operands Description Operation Rd ← Rd + Rr Rd ← Rd + Rr + C Rdh:Rdl ← Rdh:Rdl + K Rd ← Rd − Rr Rd ← Rd − K Rdh:Rdl ← Rdh:Rdl − K Rd ← Rd − Rr − C Rd ← Rd − K − C Rd ← Rd • Rr Rd ← Rd • K Rd ← Rd v Rr Rd ← Rd v K Rd ← Rd ⊕ Rr Rd ← $FF − Rd Rd ← $00 − Rd Rd ← Rd v K Rd ← Rd • ($FF − K) Rd ← Rd + 1 Rd ← Rd − 1 Rd ← Rd • Rd Rd ← Rd ⊕ Rd Rd ← $FF PC ← PC + k + 1 PC ← Z PC ← PC + k + 1 PC ← Z PC ← STACK PC ← STACK if (Rd = Rr) PC ← PC + 2 or 3 Rd − Rr Rd − Rr − C Rd − K if (Rr(b)=0) PC ← PC + 2 or 3 if (Rr(b)=1) PC ← PC + 2 or 3 if (P(b)=0) PC ← PC + 2 or 3 if (R(b)=1) PC ← PC + 2 or 3 if (SREG(s) = 1) then PC←PC + k + 1 if (SREG(s) = 0) then PC←PC + k + 1 if (Z = 1) then PC ← PC + k + 1 if (Z = 0) then PC ← PC + k + 1 if (C = 1) then PC ← PC + k + 1 if (C = 0) then PC ← PC + k + 1 if (C = 0) then PC ← PC + k + 1 if (C = 1) then PC ← PC + k + 1 if (N = 1) then PC ← PC + k + 1 if (N = 0) then PC ← PC + k + 1 if (N ⊕ V= 0) then PC ← PC + k + 1 if (N ⊕ V= 1) then PC ← PC + k + 1 if (H = 1) then PC ← PC + k + 1 if (H = 0) then PC ← PC + k + 1 if (T = 1) then PC ← PC + k + 1 if (T = 0) then PC ← PC + k + 1 if (V = 1) then PC ← PC + k + 1 if (V = 0) then PC ← PC + k + 1 if (I = 1) then PC ← PC + k + 1 if (I = 0) then PC ← PC + k + 1 Flags Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None None None None None None I None Z, N,V,C,H Z, N,V,C,H Z, N,V,C,H None None None None None None None None None None None None None None None None None None None None None None None None #Clock 1 1 2 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 3 3 4 4 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers ADC Rd, Rr Add with Carry two Registers ADIW Rdl,K Add Immediate to Word SUB Rd, Rr Subtract two Registers SUBI Rd, K Subtract Constant from Register SBIW Rdl,K Subtract Immediate from Word SBC Rd, Rr Subtract with Carry two Registers SBCI Rd, K Subtract with Carry Constant from Reg. AND Rd, Rr Logical AND Registers ANDI Rd, K Logical AND Register and Constant OR Rd, Rr Logical OR Registers ORI Rd, K Logical OR Register and Constant EOR Rd, Rr Exclusive OR Registers COM Rd One’s Complement NEG Rd Two’s Complement SBR Rd,K Set Bit(s) in Register CBR Rd,K Clear Bit(s) in Register INC Rd Increment DEC Rd Decrement TST Rd Test for Zero or Minus CLR Rd Clear Register SER Rd Set Register BRANCH INSTRUCTIONS RJMP k Relative Jump IJMP Indirect Jump to (Z) RCALL k Relative Subroutine Call ICALL Indirect Call to (Z) RET Subroutine Return RETI Interrupt Return CPSE Rd,Rr Compare, Skip if Equal CP Rd,Rr Compare CPC Rd,Rr Compare with Carry CPI Rd,K Compare Register with Immediate SBRC Rr, b Skip if Bit in Register Cleared SBRS Rr, b Skip if Bit in Register is Set SBIC P, b Skip if Bit in I/O Register Cleared SBIS P, b Skip if Bit in I/O Register is Set BRBS s, k Branch if Status Flag Set BRBC s, k Branch if Status Flag Cleared BREQ k Branch if Equal BRNE k Branch if Not Equal BRCS k Branch if Carry Set BRCC k Branch if Carry Cleared BRSH k Branch if Same or Higher BRLO k Branch if Lower BRMI k Branch if Minus BRPL k Branch if Plus BRGE k Branch if Greater or Equal, Signed BRLT k Branch if Less Than Zero, Signed BRHS k Branch if Half Carry Flag Set BRHC k Branch if Half Carry Flag Cleared BRTS k Branch if T Flag Set BRTC k Branch if T Flag Cleared BRVS k Branch if Overflow Flag is Set BRVC k Branch if Overflow Flag is Cleared BRIE k Branch if Interrupt Enabled BRID k Branch if Interrupt Disabled 52 ATtiny22L ATtiny22L Instruction Set Summary (Continued) Mnemonics Operands Description Move Between Registers Load Immediate Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Direct from SRAM Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Direct to SRAM Load Program Memory In Port Out Port Push Register on Stack Pop Register from Stack Set Bit in I/O Register Clear Bit in I/O Register Logical Shift Left Logical Shift Right Rotate Left Through Carry Rotate Right Through Carry Arithmetic Shift Right Swap Nibbles Flag Set Flag Clear Bit Store from Register to T Bit load from T to Register Set Carry Clear Carry Set Negative Flag Clear Negative Flag Set Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Set Signed Test Flag Clear Signed Test Flag Set Twos Complement Overflow Clear Twos Complement Overflow Set T in SREG Clear T in SREG Set Half Carry Flag in SREG Clear Half Carry Flag in SREG No Operation Sleep Watchdog Reset Operation Rd ← Rr Rd ← K Rd ← (X) Rd ← (X), X ← X + 1 X ← X − 1, Rd ← (X) Rd ← (Y) Rd ← (Y), Y ← Y + 1 Y ← Y − 1, Rd ← (Y) Rd ← (Y + q) Rd ← (Z) Rd ← (Z), Z ← Z+1 Z ← Z - 1, Rd ← (Z) Rd ← (Z + q) Rd ← (k) (X) ← Rr (X) ← Rr, X ← X + 1 X ← X - 1, (X) ← Rr (Y) ← Rr (Y) ← Rr, Y ← Y + 1 Y ← Y - 1, (Y) ← Rr (Y + q) ← Rr (Z) ← Rr (Z) ← Rr, Z ← Z + 1 Z ← Z - 1, (Z) ← Rr (Z + q) ← Rr (k) ← Rr R0 ← (Z) Rd ← P P ← Rr STACK ← Rr Rd ← STACK I/O(P,b) ← 1 I/O(P,b) ← 0 Rd(n+1) ← Rd(n), Rd(0) ← 0 Rd(n) ← Rd(n+1), Rd(7) ← 0 Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7) Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Rd(n) ← Rd(n+1), n=0..6 Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0) SREG(s) ← 1 SREG(s) ← 0 T ← Rr(b) Rd(b) ← T C←1 C←0 N←1 N←0 Z←1 Z←0 I←1 I←0 S←1 S←0 V←1 V←0 T←1 T←0 H←1 H←0 (see specific descr. for Sleep (see specific descr. for WDR/timer) Flags None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V None SREG(s) SREG(s) T None C C N N Z Z I I S S V V T T H H None None None #Clock 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 1 1 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 1 DATA TRANSFER INSTRUCTIONS MOV Rd, Rr LDI Rd, K LD Rd, X LD Rd, X+ LD Rd, - X LD Rd, Y LD Rd, Y+ LD Rd, - Y LDD Rd,Y+q LD Rd, Z LD Rd, Z+ LD Rd, -Z LDD Rd, Z+q LDS Rd, k ST X, Rr ST X+, Rr ST - X, Rr ST Y, Rr ST Y+, Rr ST - Y, Rr STD Y+q,Rr ST Z, Rr ST Z+, Rr ST -Z, Rr STD Z+q,Rr STS k, Rr LPM IN Rd, P OUT P, Rr PUSH Rr POP Rd BIT AND BIT-TEST INSTRUCTIONS SBI P,b CBI P,b LSL Rd LSR Rd ROL Rd ROR Rd ASR Rd SWAP Rd BSET s BCLR s BST Rr, b BLD Rd, b SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH CLH NOP SLEEP WDR 53 Ordering Information Power Supply 2.7 - 6.0V Speed (MHz) Internal Osc ~1MHz@5.0V Ordering Code ATtiny22L-1PC ATtiny22L-1SC ATtiny22L-1PI ATtiny22L-1SI Package 8P3 8S2 8P3 8S2 Operation Range Commercial (0°C to 70°C) Industrial (-40°C to 85°C) Package Type 8P3 8S2 8-pin, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8-lead, 0.200" Wide, Plastic Gull-Wing Small Outline (EIAJ SOIC) 54 ATtiny22L Packaging Information 8P3, 8-pin, 0.300" Wide, Plastic Dual Inline Package (PDIP) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-001 BA .400 (10.16) .355 (9.02) PIN 1 .280 (7.11) .240 (6.10) .037 (.940) .027 (.690) 8S2, 8-lead, 0.200" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC) Dimensions in Inches and (Millimeters) .020 (.508) .012 (.305) PIN 1 .213 (5.41) .205 (5.21) .330 (8.38) .300 (7.62) .300 (7.62) REF .050 (1.27) BSC .210 (5.33) MAX SEATING PLANE .150 (3.81) .115 (2.92) .070 (1.78) .045 (1.14) .100 (2.54) BSC .212 (5.38) .203 (5.16) .015 (.380) MIN .022 (.559) .014 (.356) .080 (2.03) .070 (1.78) .013 (.330) .004 (.102) .325 (8.26) .300 (7.62) .012 (.305) .008 (.203) 0 REF 15 .430 (10.9) MAX 0 REF 8 .035 (.889) .020 (.508) .010 (.254) .007 (.178) 55 ATtiny22L Atmel Headquarters Corporate Headquarters 2325 Orchard Parkway San Jose, CA 95131 TEL (408) 441-0311 FAX (408) 487-2600 Atmel Operations Atmel Colorado Springs 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL (719) 576-3300 FAX (719) 540-1759 Europe Atmel U.K., Ltd. Coliseum Business Centre Riverside Way Camberley, Surrey GU15 3YL England TEL (44) 1276-686-677 FAX (44) 1276-686-697 Atmel Rousset Zone Industrielle 13106 Rousset Cedex France TEL (33) 4-4253-6000 FAX (33) 4-4253-6001 Asia Atmel Asia, Ltd. Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 Japan Atmel Japan K.K. 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 Fax-on-Demand North America: 1-(800) 292-8635 International: 1-(408) 441-0732 e-mail literature@atmel.com Web Site http://www.atmel.com BBS 1-(408) 436-4309 © A tmel Corporation 2000. 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