ATTINY25-20SU

Features • High Performance, Low Power AVR® 8-Bit Microcontroller • Advanced RISC Architecture – 120 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation Non-volatile Program and Data Memories – 2/4/8K Byte of In-System Programmable Program Memory Flash (ATtiny25/45/85) Endurance: 10,000 Write/Erase Cycles – 128/256/512 Bytes In-System Programmable EEPROM (ATtiny25/45/85) Endurance: 100,000 Write/Erase Cycles – 128/256/512 Bytes Internal SRAM (ATtiny25/45/85) – Programming Lock for Self-Programming Flash Program and EEPROM Data Security Peripheral Features – 8-bit Timer/Counter with Prescaler and Two PWM Channels – 8-bit High Speed Timer/Counter with Separate Prescaler 2 High Frequency PWM Outputs with Separate Output Compare Registers Programmable Dead Time Generator – USI – Universal Serial Interface with Start Condition Detector – 10-bit ADC 4 Single Ended Channels 2 Differential ADC Channel Pairs with Programmable Gain (1x, 20x) Temperature Measurement – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator Special Microcontroller Features – debugWIRE On-chip Debug System – In-System Programmable via SPI Port – External and Internal Interrupt Sources – Low Power Idle, ADC Noise Reduction, and Power-down Modes – Enhanced Power-on Reset Circuit – Programmable Brown-out Detection Circuit – Internal Calibrated Oscillator I/O and Packages – Six Programmable I/O Lines – 8-pin PDIP, 8-pin SOIC and 20-pad QFN/MLF Operating Voltage – 1.8 - 5.5V for ATtiny25/45/85V – 2.7 - 5.5V for ATtiny25/45/85 Speed Grade – ATtiny25/45/85V: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V – ATtiny25/45/85: 0 - 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V Industrial Temperature Range Low Power Consumption – Active Mode: 1 MHz, 1.8V: 300 μA – Power-down Mode: 0.1μA at 1.8V • • 8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash ATtiny25/V* ATtiny45/V ATtiny85/V* Summary *Preliminary • • • • • • 2586JS–AVR–12/06 1. Pin Configurations Figure 1-1. Pinout ATtiny25/45/85 PDIP/SOIC (PCINT5/RESET/ADC0/dW) PB5 (PCINT3/XTAL1/CLKI/OC1B/ADC3) PB3 (PCINT4/XTAL2/CLKO/OC1B/ADC2) PB4 GND 1 2 3 4 8 7 6 5 VCC PB2 (SCK/USCK/SCL/ADC1/T0/INT0/PCINT2) PB1 (MISO/DO/AIN1/OC0B/OC1A/PCINT1) PB0 (MOSI/DI/SDA/AIN0/OC0A/OC1A/AREF/PCINT0) QFN/MLF DNC DNC DNC DNC DNC NOTE: Bottom pad should be soldered to ground. DNC: Do Not Connect 2 ATtiny25/45/85 2586JS–AVR–12/06 DNC DNC GND DNC DNC 6 7 8 9 10 (PCINT5/RESET/ADC0/dW) PB5 (PCINT3/XTAL1/CLKI/OC1B/ADC3) PB3 DNC DNC (PCINT4/XTAL2/CLKO/OC1B/ADC2) PB4 1 2 3 4 5 20 19 18 17 16 15 14 13 12 11 VCC PB2 (SCK/USCK/SCL/ADC1/T0/INT0/PCINT2) DNC PB1 (MISO/DO/AIN1/OC0B/OC1A/PCINT1) PB0 (MOSI/DI/SDA/AIN0/OC0A/OC1A/AREF/PCINT0) ATtiny25/45/85 2. Overview The ATtiny25/45/85 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny25/45/85 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Figure 2-1. Block Diagram 8-BIT DATABUS CALIBRATED INTERNAL OSCILLATOR PROGRAM COUNTER VCC PROGRAM FLASH STACK POINTER WATCHDOG TIMER MCU CONTROL REGISTER TIMING AND CONTROL SRAM MCU STATUS REGISTER GND INSTRUCTION REGISTER GENERAL PURPOSE REGISTERS INSTRUCTION DECODER X Y Z TIMER/ COUNTER0 TIMER/ COUNTER1 UNIVERSAL SERIAL INTERFACE CONTROL LINES ALU STATUS REGISTER INTERRUPT UNIT PROGRAMMING LOGIC DATA EEPROM OSCILLATORS DATA REGISTER PORT B DATA DIR. REG.PORT B ADC / ANALOG COMPARATOR PORT B DRIVERS RESET PB0-PB5 The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent 3 2586JS–AVR–12/06 registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATtiny25/45/85 provides the following features: 2/4/8K byte of In-System Programmable Flash, 128/256/512 bytes EEPROM, 128/256/256 bytes SRAM, 6 general purpose I/O lines, 32 general purpose working registers, one 8-bit Timer/Counter with compare modes, one 8-bit high speed Timer/Counter, Universal Serial Interface, Internal and External Interrupts, a 4-channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, and three software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counter, ADC, Analog Comparator, and Interrupt system to continue functioning. The Power-down mode saves the register contents, disabling all chip functions until the next Interrupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize switching noise during ADC conversions. The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI serial interface, by a conventional non-volatile memory programmer or by an On-chip boot code running on the AVR core. The ATtiny25/45/85 AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits. 2.2 2.2.1 Pin Descriptions VCC Supply voltage. 2.2.2 GND Ground. 2.2.3 Port B (PB5..PB0) Port B is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATtiny25/45/85 as listed on page 61. On the ATtiny25 device the programmable I/O ports PB3 and PB4 (pins 2 and 3) are exchanged in the ATtiny15 compatibility mode for supporting the backward compatibility with ATtiny15. 2.2.4 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 23-3 on page 170. Shorter pulses are not guaranteed to generate a reset. 4 ATtiny25/45/85 2586JS–AVR–12/06 ATtiny25/45/85 3. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 5 2586JS–AVR–12/06 4. Register Summary Address 0x3F 0x3E 0x3D 0x3C 0x3B 0x3A 0x39 0x38 0x37 0x36 0x35 0x34 0x33 0x32 0x31 0x30 0x2F 0x2E 0x2D 0x2C 0x2B 0x2A 0x29 0x28 0x27 0x26 0x25 0x24 0x23 0x22 0x21 0x20 0x1F 0x1E 0x1D 0x1C 0x1B 0x1A 0x19 0x18 0x17 0x16 0x15 0x14 0x13 0x12 0x11 0x10 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 0x00 Name SREG SPH SPL Reserved GIMSK GIFR TIMSK TIFR SPMCSR Reserved MCUCR MCUSR TCCR0B TCNT0 OSCCAL TCCR1 TCNT1 OCR1A OCR1C GTCCR OCR1B TCCR0A OCR0A OCR0B PLLCSR CLKPR DT1A DT1B DTPS1 DWDR WDTCR PRR EEARH EEARL EEDR EECR Reserved Reserved Reserved PORTB DDRB PINB PCMSK DIDR0 GPIOR2 GPIOR1 GPIOR0 USIBR USIDR USISR USICR Reserved Reserved Reserved Reserved ACSR ADMUX ADCSRA ADCH ADCL ADCSRB Reserved Reserved Reserved Bit 7 I – SP7 – – – – – BODS – FOC0A Bit 6 T – SP6 INT0 INTF0 OCIE1A OCF1A – PUD – FOC0B Bit 5 H – SP5 PCIE PCIF OCIE1B OCF1B – SE – – Bit 4 S – SP4 – – – OCIE0A OCF0A CTPB – SM1 – – Bit 3 V – SP3 – – OCIE0B OCF0B RFLB SM0 WDRF WGM02 Bit 2 N – SP2 – – TOIE1 TOV1 PGWRT BODSE BORF CS02 Bit 1 Z SP9 SP1 – – TOIE0 TOV0 PGERS ISC01 EXTRF CS01 Bit 0 C SP8 SP0 – – – – SPMEN ISC00 PORF CS00 Page page 7 page 10 page 10 page 51 page 52 page 84/page 106 page 84 page 148 page 37,page 51, page 65, page 44, page 82 page 83 page 31 Timer/Counter0 Oscillator Calibration Register CTC1 PWM1A COM1A1 COM1A0 CS13 CS12 CS11 CS10 Timer/Counter1 Timer/Counter1 Output Compare Register A Timer/Counter1 Output Compare Register C TSM COM0A1 PWM1B COM0A0 COM1B1 COM0B1 COM1B0 COM0B0 FOC1B – FOC1A PSR1 WGM01 PSR0 WGM00 Timer/Counter1 Output Compare Register B Timer/Counter0 – Output Compare Register A Timer/Counter0 – Output Compare Register B LSM CLKPCE DT1AH3 DT1BH3 WDIF – EEAR7 – EEAR6 – EEAR5 EEPM1 EEAR4 EEPM0 – – – – – – – – – – – – – PORTB5 DDB5 PINB5 PCINT5 ADC0D PORTB4 DDB4 PINB4 PCINT4 ADC2D PORTB3 DDB3 PINB3 PCINT3 ADC3D PORTB2 DDB2 PINB2 PCINT2 ADC1D PORTB1 DDB1 PINB1 PCINT1 AIN1D PORTB0 DDB0 PINB0 PCINT0 AIN0D – – DT1AH2 DT1BH2 WDIE – – DT1AH1 DT1BH1 WDP3 – – DT1AH0 DT1BH0 DWDR[7:0] WDCE WDE PRTIM1 EEAR3 EERIE WDP2 PRTIM0 EEAR2 EEMPE WDP1 PRUSI EEAR1 EEPE WDP0 PRADC EEAR8 EEAR0 EERE EEPROM Data Register – CLKPS3 DT1AL3 DT1BL3 PCKE CLKPS2 DT1AL2 DT1BL2 PLLE CLKPS1 DT1AL1 DT1BL1 DTPS11 PLOCK CLKPS0 DT1AL0 DT1BL0 DTPS10 page 92, page 103 page 94, page 105 page 94, page 105 page 95, page 106 page 79, page 93, page page 95 page 79 page 83 page 84 page 97, page 107 page 32 page 109 page 110 page 109 page 145 page 44 page 36 page 19 page 19 page 19 page 20 page 65 page 65 page 65 page 52 page 125, page 143 page 9 page 9 page 9 page 119 page 118 General Purpose I/O Register 2 General Purpose I/O Register 1 General Purpose I/O Register 0 USI Buffer Register USI Data Register USISIF USISIE USIOIF USIOIE USIPF USIWM1 USIDC USIWM0 – – – – ACD REFS1 ADEN ACBG REFS0 ADSC ACO ADLAR ADATE ACI REFS2 ADIF ACIE MUX3 ADIE – MUX2 ADPS2 ACIS1 MUX1 ADPS1 ACIS0 MUX0 ADPS0 USICNT3 USICS1 USICNT2 USICS0 USICNT1 USICLK USICNT0 USITC page 119 page 120 page 124 page 138 page 140 page 141 page 141 ADC Data Register High Byte ADC Data Register Low Byte BIN ACME IPR – – – – – ADTS2 ADTS1 ADTS0 page 124, page 142 6 ATtiny25/45/85 2586JS–AVR–12/06 ATtiny25/45/85 Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operation the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 7 2586JS–AVR–12/06 5. Instruction Set Summary Mnemonics ADD ADC ADIW SUB SUBI SBC SBCI SBIW AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER RJMP IJMP RCALL ICALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC BRIE BRID SBI CBI LSL LSR ROL Rd,Rr Rd,Rr Rd,Rr Rd,K Rr, b Rr, b P, b P, b s, k s, k k k k k k k k k k k k k k k k k k k P,b P,b Rd Rd Rd k Operands Rd, Rr Rd, Rr Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd Rd Rd,K Rd,K Rd Rd Rd Rd Rd k Add two Registers Description Rd ← Rd + Rr Operation Flags Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None None None None None None I None Z, N,V,C,H Z, N,V,C,H Z, N,V,C,H None None None None None None None None None None None None None None None None None None None None None None None None None None Z,C,N,V Z,C,N,V Z,C,N,V #Clocks 1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 3 3 4 4 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 2 2 1 1 1 ARITHMETIC AND LOGIC INSTRUCTIONS Add with Carry two Registers Add Immediate to Word Subtract two Registers Subtract Constant from Register Subtract with Carry two Registers Subtract with Carry Constant from Reg. Subtract Immediate from Word Logical AND Registers Logical AND Register and Constant Logical OR Registers Logical OR Register and Constant Exclusive OR Registers One’s Complement Two’s Complement Set Bit(s) in Register Clear Bit(s) in Register Increment Decrement Test for Zero or Minus Clear Register Set Register Relative Jump Indirect Jump to (Z) Relative Subroutine Call Indirect Call to (Z) Subroutine Return Interrupt Return Compare, Skip if Equal Compare Compare with Carry Compare Register with Immediate Skip if Bit in Register Cleared Skip if Bit in Register is Set Skip if Bit in I/O Register Cleared Skip if Bit in I/O Register is Set Branch if Status Flag Set Branch if Status Flag Cleared Branch if Equal Branch if Not Equal Branch if Carry Set Branch if Carry Cleared Branch if Same or Higher Branch if Lower Branch if Minus Branch if Plus Branch if Greater or Equal, Signed Branch if Less Than Zero, Signed Branch if Half Carry Flag Set Branch if Half Carry Flag Cleared Branch if T Flag Set Branch if T Flag Cleared Branch if Overflow Flag is Set Branch if Overflow Flag is Cleared Branch if Interrupt Enabled Branch if Interrupt Disabled Set Bit in I/O Register Clear Bit in I/O Register Logical Shift Left Logical Shift Right Rotate Left Through Carry Rd ← Rd + Rr + C Rdh:Rdl ← Rdh:Rdl + K Rd ← Rd - Rr Rd ← Rd - K Rd ← Rd - Rr - C Rd ← Rd - K - C Rdh:Rdl ← Rdh:Rdl - K Rd ← Rd • Rr Rd ← Rd • K Rd ← Rd v Rr Rd ← Rd v K Rd ← Rd ⊕ Rr Rd ← 0xFF − Rd Rd ← 0x00 − Rd Rd ← Rd v K Rd ← Rd • (0xFF - K) Rd ← Rd + 1 Rd ← Rd − 1 Rd ← Rd • Rd Rd ← Rd ⊕ Rd Rd ← 0xFF PC ← PC + k + 1 PC ← Z PC ← PC + k + 1 PC ← Z PC ← STACK PC ← STACK if (Rd = Rr) PC ← PC + 2 or 3 Rd − Rr Rd − Rr − C Rd − K if (Rr(b)=0) PC ← PC + 2 or 3 if (Rr(b)=1) PC ← PC + 2 or 3 if (P(b)=0) PC ← PC + 2 or 3 if (P(b)=1) PC ← PC + 2 or 3 if (SREG(s) = 1) then PC←PC+k + 1 if (SREG(s) = 0) then PC←PC+k + 1 if (Z = 1) then PC ← PC + k + 1 if (Z = 0) then PC ← PC + k + 1 if (C = 1) then PC ← PC + k + 1 if (C = 0) then PC ← PC + k + 1 if (C = 0) then PC ← PC + k + 1 if (C = 1) then PC ← PC + k + 1 if (N = 1) then PC ← PC + k + 1 if (N = 0) then PC ← PC + k + 1 if (N ⊕ V= 0) then PC ← PC + k + 1 if (N ⊕ V= 1) then PC ← PC + k + 1 if (H = 1) then PC ← PC + k + 1 if (H = 0) then PC ← PC + k + 1 if (T = 1) then PC ← PC + k + 1 if (T = 0) then PC ← PC + k + 1 if (V = 1) then PC ← PC + k + 1 if (V = 0) then PC ← PC + k + 1 if ( I = 1) then PC ← PC + k + 1 if ( I = 0) then PC ← PC + k + 1 I/O(P,b) ← 1 I/O(P,b) ← 0 Rd(n+1) ← Rd(n), Rd(0) ← 0 Rd(n) ← Rd(n+1), Rd(7) ← 0 Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7) BRANCH INSTRUCTIONS BIT AND BIT-TEST INSTRUCTIONS 8 ATtiny25/45/85 2586JS–AVR–12/06 ATtiny25/45/85 Mnemonics ROR ASR SWAP BSET BCLR BST BLD SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH CLH DATA TRANSFER INSTRUCTIONS MOV MOVW LDI LD LD LD LD LD LD LDD LD LD LD LDD LDS ST ST ST ST ST ST STD ST ST ST STD STS LPM LPM LPM SPM IN OUT PUSH POP NOP SLEEP WDR BREAK Rd, P P, Rr Rr Rd Rd, Z Rd, Z+ Rd, Rr Rd, Rr Rd, K Rd, X Rd, X+ Rd, - X Rd, Y Rd, Y+ Rd, - Y Rd,Y+q Rd, Z Rd, Z+ Rd, -Z Rd, Z+q Rd, k X, Rr X+, Rr - X, Rr Y, Rr Y+, Rr - Y, Rr Y+q,Rr Z, Rr Z+, Rr -Z, Rr Z+q,Rr k, Rr Move Between Registers Copy Register Word Load Immediate Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Direct from SRAM Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Direct to SRAM Load Program Memory Load Program Memory Load Program Memory and Post-Inc Store Program Memory In Port Out Port Push Register on Stack Pop Register from Stack No Operation Sleep Watchdog Reset Break (see specific descr. for Sleep function) (see specific descr. for WDR/Timer) For On-chip Debug Only Rd ← Rr Rd+1:Rd ← Rr+1:Rr Rd ← K Rd ← (X) Rd ← (X), X ← X + 1 X ← X - 1, Rd ← (X) Rd ← (Y) Rd ← (Y), Y ← Y + 1 Y ← Y - 1, Rd ← (Y) Rd ← (Y + q) Rd ← (Z) Rd ← (Z), Z ← Z+1 Z ← Z - 1, Rd ← (Z) Rd ← (Z + q) Rd ← (k) (X) ← Rr (X) ← Rr, X ← X + 1 X ← X - 1, (X) ← Rr (Y) ← Rr (Y) ← Rr, Y ← Y + 1 Y ← Y - 1, (Y) ← Rr (Y + q) ← Rr (Z) ← Rr (Z) ← Rr, Z ← Z + 1 Z ← Z - 1, (Z) ← Rr (Z + q) ← Rr (k) ← Rr R0 ← (Z) Rd ← (Z) Rd ← (Z), Z ← Z+1 (z) ← R1:R0 Rd ← P P ← Rr STACK ← Rr Rd ← STACK None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None 1 1 2 2 1 1 1 N/A 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 Operands Rd Rd Rd s s Rr, b Rd, b Arithmetic Shift Right Swap Nibbles Flag Set Flag Clear Description Rotate Right Through Carry Operation Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Rd(n) ← Rd(n+1), n=0..6 Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0) SREG(s) ← 1 SREG(s) ← 0 T ← Rr(b) Rd(b) ← T C←1 C←0 N←1 N←0 Z←1 Z←0 I←1 I←0 S←1 S←0 V←1 V←0 T←1 T←0 H←1 H←0 Flags Z,C,N,V Z,C,N,V None SREG(s) SREG(s) T None C C N N Z Z I I S S V V T T H H #Clocks 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit Store from Register to T Bit load from T to Register Set Carry Clear Carry Set Negative Flag Clear Negative Flag Set Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Set Signed Test Flag Clear Signed Test Flag Set Twos Complement Overflow. Clear Twos Complement Overflow Set T in SREG Clear T in SREG Set Half Carry Flag in SREG Clear Half Carry Flag in SREG MCU CONTROL INSTRUCTIONS 9 2586JS–AVR–12/06 6. Ordering Information 6.1 ATtiny25 Speed (MHz)(3) 10 Power Supply 1.8 - 5.5V Ordering Code(2) ATtiny25V-10PU ATtiny25V-10SU ATtiny25V-10MU ATtiny25-20PU ATtiny25-20SU ATtiny25-20MU Package(1) 8P3 8S2 20M1 8P3 8S2 20M1 Operational Range Industrial (-40°C to 85°C) 20 Notes: 2.7 - 5.5V Industrial (-40°C to 85°C) 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. For Speed vs. VCC,see Figure 23.3 on page 168 Package Type 8P3 8S2 20M1 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8-lead, 0.209" Wide, Plastic Gull-Wing Small Outline (EIAJ SOIC) 20-pad, 4 x 4 x 0.8 mm Body, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 10 ATtiny25/45/85 2586JS–AVR–12/06 ATtiny25/45/85 6.2 ATtiny45 Speed (MHz)(3) 10 Power Supply 1.8 - 5.5V Ordering Code(2) ATtiny45V-10PU ATtiny45V-10SU ATtiny45V-10MU ATtiny45-20PU ATtiny45-20SU ATtiny45-20MU Package(1) 8P3 8S2 20M1 8P3 8S2 20M1 Operational Range Industrial (-40°C to 85°C) 20 Notes: 2.7 - 5.5V Industrial (-40°C to 85°C) 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. For Speed vs. VCC,see Figure 23.3 on page 168 Package Type 8P3 8S2 20M1 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8-lead, 0.209" Wide, Plastic Gull-Wing Small Outline (EIAJ SOIC) 20-pad, 4 x 4 x 0.8 mm Body, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 11 2586JS–AVR–12/06 6.3 ATtiny85 Speed (MHz)(3) 10 Power Supply 1.8 - 5.5V Ordering Code(2) ATtiny85V-10PU ATtiny85V-10SU ATtiny85V-10MU ATtiny85-20PU ATtiny85-20SU ATtiny85-20MU Package(1) 8P3 8S2 20M1 8P3 8S2 20M1 Operational Range Industrial (-40°C to 85°C) 20 Notes: 2.7 - 5.5V Industrial (-40°C to 85°C) 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. For Speed vs. VCC,see Figure 23.3 on page 168 Package Type 8P3 8S2 20M1 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8-lead, 0.209" Wide, Plastic Gull-Wing Small Outline (EIAJ SOIC) 20-pad, 4 x 4 x 0.8 mm Body, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 12 ATtiny25/45/85 2586JS–AVR–12/06 ATtiny25/45/85 7. Packaging Information 7.1 8P3 1 E E1 N Top View c eA End View D e D1 A2 A SYMBOL COMMON DIMENSIONS (Unit of Measure = inches) MIN NOM MAX NOTE A A2 b b2 b3 c D 0.115 0.014 0.045 0.030 0.008 0.355 0.005 0.300 0.240 0.310 0.250 0.100 BSC 0.300 BSC 0.115 0.130 0.130 0.018 0.060 0.039 0.010 0.365 0.210 0.195 0.022 0.070 0.045 0.014 0.400 2 5 6 6 3 3 b2 b3 4 PLCS L D1 E E1 e eA L b 0.325 0.280 4 3 Side View 4 0.150 2 Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information. 2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3. 3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch. 4. E and eA measured with the leads constrained to be perpendicular to datum. 5. Pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm). 01/09/02 2325 Orchard Parkway San Jose, CA 95131 TITLE 8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP) DRAWING NO. 8P3 REV. B R 13 2586JS–AVR–12/06 7.2 8S2 C 1 E E1 L N TOP VIEW θ END VIEW e A SYMBOL b COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX NOTE A1 A A1 b C 1.70 0.05 0.35 0.15 5.13 5.18 7.70 0.51 0° 1.27 BSC 2.16 0.25 0.48 0.35 5.35 5.40 8.26 0.85 8° 4 2, 3 5 5 D D E1 E SIDE VIEW Notes: 1. 2. 3. 4. 5. L θ e This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. Mismatch of the upper and lower dies and resin burrs are not included. It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded. Determines the true geometric position. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm. 4/7/06 TITLE 8S2, 8-lead, 0.209" Body, Plastic Small Outline Package (EIAJ) DRAWING NO. 8S2 REV. D R 2325 Orchard Parkway San Jose, CA 95131 14 ATtiny25/45/85 2586JS–AVR–12/06 ATtiny25/45/85 7.3 20M1 D 1 Pin 1 ID 2 3 E SIDE VIEW TOP VIEW A2 D2 A1 A 1 Pin #1 Notch (0.20 R) 2 3 0.08 C E2 SYMBOL A A1 COMMON DIMENSIONS (Unit of Measure = mm) MIN 0.70 – NOM 0.75 0.01 0.20 REF 0.18 0.23 4.00 BSC 2.45 2.60 4.00 BSC 2.45 2.60 0.50 BSC 0.35 0.40 0.55 2.75 2.75 0.30 MAX 0.80 0.05 NOTE b L e BOTTOM VIEW A2 b D D2 E E2 e Note: Reference JEDEC Standard MO-220, Fig. 1 (SAW Singulation) WGGD-5. L 10/27/04 2325 Orchard Parkway San Jose, CA 95131 TITLE 20M1, 20-pad, 4 x 4 x 0.8 mm Body, Lead Pitch 0.50 mm, 2.6 mm Exposed Pad, Micro Lead Frame Package (MLF) DRAWING NO. 20M1 REV. A R 15 2586JS–AVR–12/06 8. Errata 8.1 Errata ATtiny25 The revision letter in this section refers to the revision of the ATtiny25 device. 8.1.1 Rev C No known errata 8.1.2 Rev B • Reading EEPROM at low frequency may not work for frequencies below 900 kHz 1. Reading EEPROM at low frequency may not work for frequencies below 900 kHz Reading data from the EEPROM at low internal clock frequency may result in wrong data read. Problem Fix/Workaround Avoid using the EEPROM at clock frequency below 900kHz. 8.1.3 Rev A Not sampled. 16 ATtiny25/45/85 2586JS–AVR–12/06 ATtiny25/45/85 8.2 Errata ATtiny45 The revision letter in this section refers to the revision of the ATtiny45 device. 8.2.1 Rev E No known errata 8.2.2 Rev D • Reading EEPROM at low frequency may not work for frequencies below 900 kHz 1. Reading EEPROM at low frequency may not work for frequencies below 900 kHz Reading data from the EEPROM at low internal clock frequency may result in wrong data read. Problem Fix/Workaround Avoid using the EEPROM at clock frequency below 900kHz. 8.2.3 Rev B and C • • • • PLL not locking EEPROM read from application code does not work in Lock Bit Mode 3 Reading EEPROM at low frequency may not work for frequencies below 900 kHz Timer Counter 1 PWM output generation on OC1B- XOC1B does not work correctly 1. PLL not locking When at frequencies below 6.0 MHz, the PLL will not lock Problem fix / Workaround When using the PLL, run at 6.0 MHz or higher. 2. EEPROM read from application code does not work in Lock Bit Mode 3 When the Memory Lock Bits LB2 and LB1 are programmed to mode 3, EEPROM read does not work from the application code. Problem Fix/Work around Do not set Lock Bit Protection Mode 3 when the application code needs to read from EEPROM. 3. Reading EEPROM at low frequency may not work for frequencies below 900 kHz Reading data from the EEPROM at low internal clock frequency may result in wrong data read. Problem Fix/Workaround Avoid using the EEPROM at clock frequency below 900kHz. 4. Timer Counter 1 PWM output generation on OC1B – XOC1B does not work correctly Timer Counter1 PWM output OC1B-XOC1B does not work correctly. Only in the case when the control bits, COM1B1 and COM1B0 are in the same mode as COM1A1 and COM1A0, respectively, the OC1B-XOC1B output works correctly. Problem Fix/Work around The only workaround is to use same control setting on COM1A(1:0) and COM1B(1:0) control bits, see table 14-4 in the data sheet. The problem has been fixed for Tiny45 rev D. 17 2586JS–AVR–12/06 8.2.4 Rev A • • • • • Too high power down power consumption DebugWIRE looses communication when single stepping into interrupts PLL not locking EEPROM read from application code does not work in Lock Bit Mode 3 Reading EEPROM at low frequency may not work for frequencies below 900 kHz 1. Too high power down power consumption Three situations will lead to a too high power down power consumption. These are: – An external clock is selected by fuses, but the I/O PORT is still enabled as an output. – The EEPROM is read before entering power down. – VCC is 4.5 volts or higher. Problem fix / Workaround – When using external clock, avoid setting the clock pin as Output. – Do not read the EEPROM if power down power consumption is important. – Use VCC lower than 4.5 Volts. 2. DebugWIRE looses communication when single stepping into interrupts When receiving an interrupt during single stepping, debugwire will loose communication. Problem fix / Workaround – When singlestepping, disable interrupts. – When debugging interrupts, use breakpoints within the interrupt routine, and run into the interrupt. 3. PLL not locking When at frequencies below 6.0 MHz, the PLL will not lock Problem fix / Workaround When using the PLL, run at 6.0 MHz or higher. 4. EEPROM read from application code does not work in Lock Bit Mode 3 When the Memory Lock Bits LB2 and LB1 are programmed to mode 3, EEPROM read does not work from the application code. Problem Fix/Work around Do not set Lock Bit Protection Mode 3 when the application code needs to read from EEPROM. 5. Reading EEPROM at low frequency may not work for frequencies below 900 kHz Reading data from the EEPROM at low internal clock frequency may result in wrong data read. Problem Fix/Workaround Avoid using the EEPROM at clock frequency below 900kHz. 18 ATtiny25/45/85 2586JS–AVR–12/06 ATtiny25/45/85 8.3 Errata ATtiny85 The revision letter in this section refers to the revision of the ATtiny85 device. 8.3.1 Rev B No known errata. 8.3.2 Rev A • Reading EEPROM at low frequency may not work for frequencies below 900 kHz 1. Reading EEPROM at low frequency may not work for frequencies below 900 kHz Reading data from the EEPROM at low internal clock frequency may result in wrong data read. Problem Fix/Workaround Avoid using the EEPROM at clock frequency below 900kHz. 19 2586JS–AVR–12/06 9. Datasheet Revision History 9.1 Rev. 2586J-12/06 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. Updated ”Low Power Consumption” on page 1. Updated description of instruction length in “Architectural Overview” , starting on page 6. Updated Flash size in ”In-System Re-programmable Flash Program Memory” on page 14. Updated cross-references in sections “Atomic Byte Programming” , “Erase” and “Write” , starting on page 16. Updated ”Atomic Byte Programming” on page 16. Updated ”Internal PLL for Fast Peripheral Clock Generation - clkPCK” on page 23. Replaced single clocking system figure with two: Figure 7-2 and Figure 7-3 on page 23. Updated Table 7-1 on page 24, Table 7-4 on page 26 and Table 7-6 on page 28. Updated ”Calibrated Internal RC Oscillator” on page 27. Updated Table 7-11 on page 29. Updated ”OSCCAL – Oscillator Calibration Register” on page 31. Updated ”CLKPR – Clock Prescale Register” on page 32. Updated ”Power-down Mode” on page 35. Updated “Bit 0” in ”PRR – Power Reduction Register” on page 38. Added footnote to Table 9-3 on page 46. Updated Table 12-5 on page 64. Deleted “Bits 7, 2” in ”MCUCR – MCU Control Register” on page 65. Updated and moved section “Timer/Counter0 Prescaler and Clock Sources”, now located on page 67. Updated ”Timer/Counter1 Initialization for Asynchronous Mode” on page 89. Updated bit description in ”PLLCSR – PLL Control and Status Register” on page 97 and ”PLLCSR – PLL Control and Status Register” on page 107. Added recommended maximum frequency in”Prescaling and Conversion Timing” on page 129. Updated Figure 19-8 on page 134 . Updated ”Temperature Measurement” on page 138. Updated Table 19-3 on page 139. 21. 22. 23. 24. 20 ATtiny25/45/85 2586JS–AVR–12/06 ATtiny25/45/85 25. Updated bit R/W descriptions in: ”TIMSK – Timer/Counter Interrupt Mask Register” on page 84, ”TIFR – Timer/Counter Interrupt Flag Register” on page 84, ”TIMSK – Timer/Counter Interrupt Mask Register” on page 95, ”TIFR – Timer/Counter Interrupt Flag Register” on page 96, ”PLLCSR – PLL Control and Status Register” on page 97, ”TIMSK – Timer/Counter Interrupt Mask Register” on page 106, ”TIFR – Timer/Counter Interrupt Flag Register” on page 106, ”PLLCSR – PLL Control and Status Register” on page 107 and ”DIDR0 – Digital Input Disable Register 0” on page 143. Added limitation to ”Limitations of debugWIRE” on page 145. Updated ”DC Characteristics” on page 166. Updated Table 23-4 on page 170. Updated Figure 23-6 on page 173. Updated Table 23-7 on page 173. Updated Table 24-1 on page 179. Updated Table 24-2 on page 179. Updated Table 24-26, Table 24-27 and Table 24-28, starting on page 188. Updated Table 24-29, Table 24-30 and Table 24-31, starting on page 189. Updated Table 24-33 on page 191. Updated Table 24-40, Table 24-41, Table 24-42 and Table 24-43, starting on page 195. 26. 27. 28. 29. 30. 31. 32. 33. 34. 35. 36. 9.2 Rev. 2586I-09/06 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. All Characterization data moved to ”Electrical Characteristics” on page 166. All Register Descriptions are gathered up in seperate sections in the end of each chapter. Updated Table 13-3 on page 80, Table 13-6 on page 81, Table 13-8 on page 82 and Table 22-4 on page 152. Updated ”Calibrated Internal RC Oscillator” on page 27. Updated Note in Table 8-1 on page 34. Updated ”System Control and Reset” on page 39. Updated Register Description in ”I/O Ports” on page 53. Updated Features in ”USI – Universal Serial Interface” on page 111. Updated Code Example in ”SPI Master Operation Example” on page 113 and ”SPI Slave Operation Example” on page 115. Updated ”Analog Comparator Multiplexed Input” on page 123. Updated Figure 19-1 on page 127. Updated ”Signature Bytes” on page 153. Updated ”Electrical Characteristics” on page 166. 21 2586JS–AVR–12/06 9.3 Rev. 2586H-06/06 1. 2. 3. Updated ”Calibrated Internal RC Oscillator” on page 27. Updated Table 7.12.1 on page 31. Added Table 23-1 on page 169. 9.4 Rev. 2586G-05/06 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. Updated ”Internal PLL for Fast Peripheral Clock Generation - clkPCK” on page 23. Updated ”Default Clock Source” on page 25. Updated ”Low-frequency Crystal Oscillator” on page 27. Updated ”Calibrated Internal RC Oscillator” on page 27. Updated ”Clock Output Buffer” on page 30. Updated ”Power Management and Sleep Modes” on page 34. Added ”BOD Disable” on page 34. Updated Figure 18-1 on page 123. Updated ”Bit 6 – ACBG: Analog Comparator Bandgap Select” on page 124. Added note for Table 19-2 on page 129. Updated ”Register Summary” on page 199. 9.5 Rev. 2586F-04/06 1. 2. 3. Updated ”Digital Input Enable and Sleep Modes” on page 57. Updated Table 22-15 on page 163. Updated ”Ordering Information” on page 203. 9.6 Rev. 2586E-03/06 1. 2. 3. 4. 5. Updated Features in ”Analog to Digital Converter” on page 126. Updated Operation in ”Analog to Digital Converter” on page 126. Updated Table 19-3 on page 139. Updated Table 19-2 on page 138. Updated ”Errata” on page 209. 9.7 Rev. 2586D-02/06 1. Updated Table 7-4 on page 26, Table 7-5 on page 27, Table 7-9 on page 29, Table 7-12 on page 30, Table 7-11 on page 29, Table 10-1 on page 48,Table 19-4 on page 139, Table 22-15 on page 163, Table 23-5 on page 171. Updated ”Timer/Counter1 in PWM Mode” on page 89. Updated text ”Bit 2 - TOV1: Timer/Counter1 Overflow Flag” on page 96. 2. 3. 22 ATtiny25/45/85 2586JS–AVR–12/06 ATtiny25/45/85 4. 5. 6. 7. 8. 9. Updated values in ”DC Characteristics” on page 166. Updated ”Register Summary” on page 199. Updated ”Ordering Information” on page 203. Updated Rev B and C in ”Errata ATtiny45” on page 210. All references to power-save mode are removed. Updated Register Adresses. 9.8 Rev. 2586C-06/05 1. 2. 3. 4. 5. 6. Updated ”Features” on page 1. Updated Figure 1-1 on page 2. Updated Code Examples on page 17 and page 18. Moved “Temperature Measurement” to Section 19.9 page 138. Updated ”Register Summary” on page 199. Updated ”Ordering Information” on page 203. 9.9 Rev. 2586B-05/05 1. CLKI added, instances of EEMWE/EEWE renamed EEMPE/EEPE, removed some TBD. Removed “Preliminary Description” from ”Temperature Measurement” on page 138. Updated ”Features” on page 1. Updated Figure 1-1 on page 2 and Figure 9-1 on page 39. Updated Table 8-2 on page 38, Table 12-4 on page 64, Table 12-5 on page 64 Updated ”Serial Programming Instruction set” on page 157. Updated SPH register in ”Instruction Set Summary” on page 201. Updated ”DC Characteristics” on page 166. Updated ”Ordering Information” on page 203. Updated ”Errata” on page 209. 2. 3. 4. 5. 6. 7. 8. 9. 9.10 Rev. 2586A-02/05 1. Initial revision. 23 2586JS–AVR–12/06 A tmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. 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ATMEL ®, logo and combinations thereof, Everywhere You Are ® , AVR ®, AVR Studio ®, and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. 2586JS–AVR–12/06