ATTINY84-20SSU

Features • High Performance, Low Power AVR® 8-Bit Microcontroller • Advanced RISC Architecture – 120 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation Non-Volatile Program and Data Memories – 2/4/8K Bytes of In-System Programmable Program Memory Flash • Endurance: 10,000 Write/Erase Cycles – 128/256/512 Bytes of In-System Programmable EEPROM • Endurance: 100,000 Write/Erase Cycles – 128/256/512 Bytes of Internal SRAM – Data retention: 20 years at 1°C / 100 years at 25°C – Programming Lock for Self-Programming Flash & EEPROM Data Security Peripheral Features – One 8-Bit and One 16-Bit Timer/Counter with Two PWM Channels, Each – 10-bit ADC • 8 Single-Ended Channels • 12 Differential ADC Channel Pairs with Programmable Gain (1x / 20x) – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator – Universal Serial Interface Special Microcontroller Features – debugWIRE On-chip Debug System – In-System Programmable via SPI Port – Internal and External Interrupt Sources: Pin Change Interrupt on 12 Pins – Low Power Idle, ADC Noise Reduction, Standby and Power-Down Modes – Enhanced Power-on Reset Circuit – Programmable Brown-out Detection Circuit – Internal Calibrated Oscillator – On-chip Temperature Sensor I/O and Packages – Available in 20-Pin QFN/MLF & 14-Pin SOIC and PDIP – Twelve Programmable I/O Lines Operating Voltage: – 1.8 – 5.5V for ATtiny24V/44V/84V – 2.7 – 5.5V for ATtiny24/44/84 Speed Grade – ATtiny24V/44V/84V • 0 – 4 MHz @ 1.8 – 5.5V • 0 – 10 MHz @ 2.7 – 5.5V – ATtiny24/44/84 • 0 – 10 MHz @ 2.7 – 5.5V • 0 – 20 MHz @ 4.5 – 5.5V Industrial Temperature Range: -40°C to +85°C Low Power Consumption – Active Mode (1 MHz System Clock): 300 µA @ 1.8V – Power-Down Mode: 0.1 µA @ 1.8V • • 8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash ATtiny24 ATtiny44 ATtiny84 Summary • • • • • • Rev. 8006JS–AVR–07/10 1. Pin Configurations Figure 1-1. Pinout ATtiny24/44/84 PDIP/SOIC VCC (PCINT8/XTAL1/CLKI) PB0 (PCINT9/XTAL2) PB1 (PCINT11/RESET/dW) PB3 (PCINT10/INT0/OC0A/CKOUT) PB2 (PCINT7/ICP/OC0B/ADC7) PA7 (PCINT6/OC1A/SDA/MOSI/DI/ADC6) PA6 1 2 3 4 5 6 7 14 13 12 11 10 9 8 GND PA0 (ADC0/AREF/PCINT0) PA1 (ADC1/AIN0/PCINT1) PA2 (ADC2/AIN1/PCINT2) PA3 (ADC3/T0/PCINT3) PA4 (ADC4/USCK/SCL/T1/PCINT4) PA5 (ADC5/DO/MISO/OC1B/PCINT5) QFN/MLF Pin 16: PA6 (PCINT6/OC1A/SDA/MOSI/DI/ADC6) Pin 20: PA5 (ADC5/DO/MISO/OC1B/PCINT5) PA7 (PCINT7/ICP/OC0B/ADC7) PB2 (PCINT10/INT0/OC0A/CKOUT) PB3 (PCINT11/RESET/dW) PB1 (PCINT9/XTAL2) PB0 (PCINT8/XTAL1/CLKI) PA5 DNC DNC DNC PA6 NOTE Bottom pad should be soldered to ground. DNC: Do Not Connect 1.1 1.1.1 Pin Descriptions VCC Supply voltage. 1.1.2 GND Ground. 1.1.3 Port B (PB3:PB0) Port B is a 4-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability except PB3 which has the RESET capability. To use pin PB3 as an I/O pin, instead of RESET pin, program (‘0’) RSTDISBL fuse. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. 2 ATtiny24/44/84 8006JS–AVR–07/10 DNC DNC GND VCC DNC 6 7 8 9 10 (ADC4/USCK/SCL/T1/PCINT4) PA4 (ADC3/T0/PCINT3) PA3 (ADC2/AIN1/PCINT2) PA2 (ADC1/AIN0/PCINT1) PA1 (ADC0/AREF/PCINT0) PA0 1 2 3 4 5 20 19 18 17 16 15 14 13 12 11 ATtiny24/44/84 Port B also serves the functions of various special features of the ATtiny24/44/84 as listed in Section 10.2 “Alternate Port Functions” on page 58. 1.1.4 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running and provided the reset pin has not been disabled. The minimum pulse length is given in Table 20-4 on page 177. Shorter pulses are not guaranteed to generate a reset. The reset pin can also be used as a (weak) I/O pin. 1.1.5 Port A (PA7:PA0) Port A is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A has alternate functions as analog inputs for the ADC, analog comparator, timer/counter, SPI and pin change interrupt as described in “Alternate Port Functions” on page 58. 3 8006JS–AVR–07/10 2. Overview ATtiny24/44/84 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny24/44/84 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Figure 2-1. VCC 8-BIT DATABUS INTERNAL OSCILLATOR GND PROGRAM COUNTER STACK POINTER Block Diagram INTERNAL CALIBRATED OSCILLATOR WATCHDOG TIMER MCU CONTROL REGISTER TIMING AND CONTROL PROGRAM FLASH SRAM INSTRUCTION REGISTER GENERAL PURPOSE REGISTERS X Y Z MCU STATUS REGISTER TIMER/ COUNTER0 TIMER/ COUNTER1 INSTRUCTION DECODER CONTROL LINES ALU STATUS REGISTER INTERRUPT UNIT PROGRAMMING LOGIC ISP INTERFACE EEPROM OSCILLATORS ANALOG COMPARATOR DATA REGISTER PORT A DATA DIR. REG.PORT A ADC DATA REGISTER PORT B DATA DIR. REG.PORT B + - PORT A DRIVERS PORT B DRIVERS PA7-PA0 PB3-PB0 The AVR core combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. 4 ATtiny24/44/84 8006JS–AVR–07/10 ATtiny24/44/84 The ATtiny24/44/84 provides the following features: 2/4/8K byte of In-System Programmable Flash, 128/256/512 bytes EEPROM, 128/256/512 bytes SRAM, 12 general purpose I/O lines, 32 general purpose working registers, an 8-bit Timer/Counter with two PWM channels, a 16-bit timer/counter with two PWM channels, Internal and External Interrupts, a 8-channel 10-bit ADC, programmable gain stage (1x, 20x) for 12 differential ADC channel pairs, a programmable Watchdog Timer with internal oscillator, internal calibrated oscillator, and four software selectable power saving modes. Idle mode stops the CPU while allowing the SRAM, Timer/Counter, ADC, Analog Comparator, and Interrupt system to continue functioning. ADC Noise Reduction mode minimizes switching noise during ADC conversions by stopping the CPU and all I/O modules except the ADC. In Power-down mode registers keep their contents and all chip functions are disbaled until the next interrupt or hardware reset. In Standby mode, the crystal/resonator oscillator is running while the rest of the device is sleeping, allowing very fast start-up combined with low power consumption. The device is manufactured using Atmel’s high density non-volatile memory technology. The onchip ISP Flash allows the Program memory to be re-programmed in-system through an SPI serial interface, by a conventional non-volatile memory programmer or by an on-chip boot code running on the AVR core. The ATtiny24/44/84 AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators and Evaluation kits. 5 8006JS–AVR–07/10 3. About 3.1 Resources A comprehensive set of drivers, application notes, data sheets and descriptions on development tools are available for download at http://www.atmel.com/avr. 3.2 Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details. For I/O Registers located in the extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically, this means “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. Note that not all AVR devices include an extended I/O map. 3.3 Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. 3.4 Disclaimer Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. 6 ATtiny24/44/84 8006JS–AVR–07/10 ATtiny24/44/84 4. Register Summary Address 0x3F (0x5F) 0x3E (0x5E) 0x3D (0x5D) 0x3C (0x5C) 0x3B (0x5B) 0x3A (0x5A 0x39 (0x59) 0x38 (0x58) 0x37 (0x57) 0x36 (0x56) 0x35 (0x55) 0x34 (0x54) 0x33 (0x53) 0x32 (0x52) 0x31 (0x51) 0x30 (0x50) 0x2F (0x4F) 0x2E (0x4E) 0x2D (0x4D) 0x2C (0x4C) 0x2B (0x4B) 0x2A (0x4A) 0x29 (0x49) 0x28 (0x48) 0x27 (0x47) 0x26 (0x46) 0x25 (0x45) 0x24 (0x44) 0x23 (0x43) 0x22 (0x42) 0x21 (0x41) 0x20 (0x40) 0x1F (0x3F) 0x1E (0x3E) 0x1D (0x3D) 0x1C (0x3C) 0x1B (0x3B) 0x1A (0x3A) 0x19 (0x39) 0x18 (0x38) 0x17 (0x37) 0x16 (0x36) 0x15 (0x35) 0x14 (0x34) 0x13 (0x33) 0x12 (0x32) 0x11 (0x31)) 0x10 (0x30) 0x0F (0x2F) 0x0E (0x2E) 0x0D (0x2D) 0x0C (0x2C) 0x0B (0x2B) 0x0A (0x2A) 0x09 (0x29) 0x08 (0x28) 0x07 (0x27) 0x06 (0x26) 0x05 (0x25) 0x04 (0x24) 0x03 (0x23) 0x02 (0x22) 0x01 (0x21) 0x00 (0x20) Name SREG SPH SPL OCR0B GIMSK GIFR TIMSK0 TIFR0 SPMCSR OCR0A MCUCR MCUSR TCCR0B TCNT0 OSCCAL TCCR0A TCCR1A TCCR1B TCNT1H TCNT1L OCR1AH OCR1AL OCR1BH OCR1BL DWDR CLKPR ICR1H ICR1L GTCCR TCCR1C WDTCSR PCMSK1 EEARH EEARL EEDR EECR PORTA DDRA PINA PORTB DDRB PINB GPIOR2 GPIOR1 GPIOR0 PCMSK0 Reserved USIBR USIDR USISR USICR TIMSK1 TIFR1 Reserved Reserved ACSR ADMUX ADCSRA ADCH ADCL ADCSRB Reserved DIDR0 PRR Bit 7 I – SP7 – – – – BODS – FOC0A CAL7 COM0A1 COM1A1 ICNC1 Bit 6 T – SP6 INT0 INTF0 – – – PUD – FOC0B CAL6 COM0A0 COM1A0 ICES1 Bit 5 H – Bit 4 S – Bit 3 V – Bit 2 N – Bit 1 Z SP9 SP1 – – OCIE0A OCF0A PGERS ISC01 EXTRF CS01 CAL1 WGM01 WGM11 Bit 0 C SP8 SP0 – – TOIE0 TOV0 SPMEN ISC00 PORF CS00 CAL0 WGM00 WGM10 CS10 Page Page 8 Page 11 Page 11 Page 85 Page 51 Page 52 Page 85 Page 85 Page 157 Page 84 Pages 36, 51, and 67 Page 45 Page 83 Page 84 Page 30 Page 80 Page 108 Page 110 Page 112 Page 112 Page 112 Page 112 Page 112 Page 112 Page 152 SP5 SP4 SP3 SP2 Timer/Counter0 – Output Compare Register B PCIE1 PCIF1 – – PCIE0 PCIF0 – – – – – – – – OCIE0B OCF0B RSIG CTPB RFLB PGWRT Timer/Counter0 – Output Compare Register A SE – – CAL5 COM0B1 COM1B1 – SM1 – – CAL4 COM0B0 COM1B0 WGM13 SM0 WDRF WGM02 CAL3 – – WGM12 CS12 BODSE BORF CS02 CAL2 Timer/Counter0 CS11 Timer/Counter1 – Counter Register High Byte Timer/Counter1 – Counter Register Low Byte Timer/Counter1 – Compare Register A High Byte Timer/Counter1 – Compare Register A Low Byte Timer/Counter1 – Compare Register B High Byte Timer/Counter1 – Compare Register B Low Byte DWDR[7:0] CLKPCE – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 Timer/Counter1 - Input Capture Register High Byte Timer/Counter1 - Input Capture Register Low Byte TSM FOC1A WDIF – – EEAR7 – PORTA7 DDA7 PINA7 – – – – FOC1B WDIE – – EEAR6 – PORTA6 DDA6 PINA6 – – – – – WDP3 – – EEAR5 EEPM1 PORTA5 DDA5 PINA5 – – – – – WDCE – – EEAR4 EEPM0 PORTA4 DDA4 PINA4 – – – – – WDE PCINT11 – EEAR3 EERIE PORTA3 DDA3 PINA3 PORTB3 DDB3 PINB3 – – WDP2 PCINT10 – EEAR2 EEMPE PORTA2 DDA2 PINA2 PORTB2 DDB2 PINB2 – – WDP1 PCINT9 – EEAR1 EEPE PORTA1 DDA1 PINA1 PORTB1 DDB1 PINB1 PSR10 – WDP0 PCINT8 EEAR8 EEAR0 EERE PORTA0 DDA0 PINA0 PORTB0 DDB0 PINB0 Page 31 Page 113 Page 113 Page 116 Page 111 Page 45 Page 52 Page 20 Page 21 Page 21 Page 21 Page 67 Page 67 Page 68 Page 68 Page 68 Page 68 Page 23 Page 23 Page 23 EEPROM Data Register General Purpose I/O Register 2 General Purpose I/O Register 1 General Purpose I/O Register 0 PCINT7 PCINT6 PCINT5 PCINT4 – USI Buffer Register USI Data Register USISIF USISIE – – USIOIF USIOIE – – USIPF USIWM1 ICIE1 ICF1 USIDC USIWM0 – – – – ACD REFS1 ADEN ACBG REFS0 ADSC ACO MUX5 ADATE ACI MUX4 ADIF ACIE MUX3 ADIE ACIC MUX2 ADPS2 ACIS1 MUX1 ADPS1 ACIS0 MUX0 ADPS0 USICNT3 USICS1 – – USICNT2 USICS0 OCIE1B OCF1B USICNT1 USICLK OCIE1A OCF1A USICNT0 USITC TOIE1 TOV1 PCINT3 PCINT2 PCINT1 PCINT0 Page 53 Page 125 Page 124 Page 125 Page 126 Page 113 Page 114 Page 130 Page 145 Page 147 Page 149 Page 149 ADC Data Register High Byte ADC Data Register Low Byte BIN ADC7D – ACME ADC6D – – ADC5D – ADLAR – ADC4D – ADC3D PRTIM1 ADC2D PRTIM0 ADC1D PRUSI ADC0D PRADC – ADTS2 ADTS1 ADTS0 Page 131, Page 149 Page 131, Page 150 Page 37 7 8006JS–AVR–07/10 Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operation the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 8 ATtiny24/44/84 8006JS–AVR–07/10 ATtiny24/44/84 5. Instruction Set Summary Mnemonics ADD ADC ADIW SUB SUBI SBC SBCI SBIW AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER RJMP IJMP RCALL ICALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC BRIE BRID SBI CBI LSL LSR ROL Rd,Rr Rd,Rr Rd,Rr Rd,K Rr, b Rr, b P, b P, b s, k s, k k k k k k k k k k k k k k k k k k k P,b P,b Rd Rd Rd k Operands Rd, Rr Rd, Rr Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd Rd Rd,K Rd,K Rd Rd Rd Rd Rd k Add two Registers Description Rd ← Rd + Rr Operation Flags Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None None None None None None I None Z, N,V,C,H Z, N,V,C,H Z, N,V,C,H None None None None None None None None None None None None None None None None None None None None None None None None None None Z,C,N,V Z,C,N,V Z,C,N,V #Clocks 1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 3 3 4 4 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 2 2 1 1 1 ARITHMETIC AND LOGIC INSTRUCTIONS Add with Carry two Registers Add Immediate to Word Subtract two Registers Subtract Constant from Register Subtract with Carry two Registers Subtract with Carry Constant from Reg. Subtract Immediate from Word Logical AND Registers Logical AND Register and Constant Logical OR Registers Logical OR Register and Constant Exclusive OR Registers One’s Complement Two’s Complement Set Bit(s) in Register Clear Bit(s) in Register Increment Decrement Test for Zero or Minus Clear Register Set Register Relative Jump Indirect Jump to (Z) Relative Subroutine Call Indirect Call to (Z) Subroutine Return Interrupt Return Compare, Skip if Equal Compare Compare with Carry Compare Register with Immediate Skip if Bit in Register Cleared Skip if Bit in Register is Set Skip if Bit in I/O Register Cleared Skip if Bit in I/O Register is Set Branch if Status Flag Set Branch if Status Flag Cleared Branch if Equal Branch if Not Equal Branch if Carry Set Branch if Carry Cleared Branch if Same or Higher Branch if Lower Branch if Minus Branch if Plus Branch if Greater or Equal, Signed Branch if Less Than Zero, Signed Branch if Half Carry Flag Set Branch if Half Carry Flag Cleared Branch if T Flag Set Branch if T Flag Cleared Branch if Overflow Flag is Set Branch if Overflow Flag is Cleared Branch if Interrupt Enabled Branch if Interrupt Disabled Set Bit in I/O Register Clear Bit in I/O Register Logical Shift Left Logical Shift Right Rotate Left Through Carry Rd ← Rd + Rr + C Rdh:Rdl ← Rdh:Rdl + K Rd ← Rd - Rr Rd ← Rd - K Rd ← Rd - Rr - C Rd ← Rd - K - C Rdh:Rdl ← Rdh:Rdl - K Rd ← Rd • Rr Rd ← Rd • K Rd ← Rd v Rr Rd ← Rd v K Rd ← Rd ⊕ Rr Rd ← 0xFF − Rd Rd ← 0x00 − Rd Rd ← Rd v K Rd ← Rd • (0xFF - K) Rd ← Rd + 1 Rd ← Rd − 1 Rd ← Rd • Rd Rd ← Rd ⊕ Rd Rd ← 0xFF PC ← PC + k + 1 PC ← Z PC ← PC + k + 1 PC ← Z PC ← STACK PC ← STACK if (Rd = Rr) PC ← PC + 2 or 3 Rd − Rr Rd − Rr − C Rd − K if (Rr(b)=0) PC ← PC + 2 or 3 if (Rr(b)=1) PC ← PC + 2 or 3 if (P(b)=0) PC ← PC + 2 or 3 if (P(b)=1) PC ← PC + 2 or 3 if (SREG(s) = 1) then PC←PC+k + 1 if (SREG(s) = 0) then PC←PC+k + 1 if (Z = 1) then PC ← PC + k + 1 if (Z = 0) then PC ← PC + k + 1 if (C = 1) then PC ← PC + k + 1 if (C = 0) then PC ← PC + k + 1 if (C = 0) then PC ← PC + k + 1 if (C = 1) then PC ← PC + k + 1 if (N = 1) then PC ← PC + k + 1 if (N = 0) then PC ← PC + k + 1 if (N ⊕ V= 0) then PC ← PC + k + 1 if (N ⊕ V= 1) then PC ← PC + k + 1 if (H = 1) then PC ← PC + k + 1 if (H = 0) then PC ← PC + k + 1 if (T = 1) then PC ← PC + k + 1 if (T = 0) then PC ← PC + k + 1 if (V = 1) then PC ← PC + k + 1 if (V = 0) then PC ← PC + k + 1 if ( I = 1) then PC ← PC + k + 1 if ( I = 0) then PC ← PC + k + 1 I/O(P,b) ← 1 I/O(P,b) ← 0 Rd(n+1) ← Rd(n), Rd(0) ← 0 Rd(n) ← Rd(n+1), Rd(7) ← 0 Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7) BRANCH INSTRUCTIONS BIT AND BIT-TEST INSTRUCTIONS 9 8006JS–AVR–07/10 Mnemonics ROR ASR SWAP BSET BCLR BST BLD SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH CLH Operands Rd Rd Rd s s Rr, b Rd, b Arithmetic Shift Right Swap Nibbles Flag Set Flag Clear Description Rotate Right Through Carry Operation Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Rd(n) ← Rd(n+1), n=0..6 Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0) SREG(s) ← 1 SREG(s) ← 0 T ← Rr(b) Rd(b) ← T C←1 C←0 N←1 N←0 Z←1 Z←0 I←1 I←0 S←1 S←0 V←1 V←0 T←1 T←0 H←1 H←0 Rd ← Rr Rd+1:Rd ← Rr+1:Rr Rd ← K Rd ← (X) Rd ← (X), X ← X + 1 X ← X - 1, Rd ← (X) Rd ← (Y) Rd ← (Y), Y ← Y + 1 Y ← Y - 1, Rd ← (Y) Rd ← (Y + q) Rd ← (Z) Rd ← (Z), Z ← Z+1 Z ← Z - 1, Rd ← (Z) Rd ← (Z + q) Rd ← (k) (X) ← Rr (X) ← Rr, X ← X + 1 X ← X - 1, (X) ← Rr (Y) ← Rr (Y) ← Rr, Y ← Y + 1 Y ← Y - 1, (Y) ← Rr (Y + q) ← Rr (Z) ← Rr (Z) ← Rr, Z ← Z + 1 Z ← Z - 1, (Z) ← Rr (Z + q) ← Rr (k) ← Rr R0 ← (Z) Rd ← (Z) Rd ← (Z), Z ← Z+1 (z) ← R1:R0 Rd ← P P ← Rr STACK ← Rr Rd ← STACK Flags Z,C,N,V Z,C,N,V None SREG(s) SREG(s) T None C C N N Z Z I I S S V V T T H H None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None #Clocks 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 1 1 2 2 1 1 1 N/A Bit Store from Register to T Bit load from T to Register Set Carry Clear Carry Set Negative Flag Clear Negative Flag Set Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Set Signed Test Flag Clear Signed Test Flag Set Twos Complement Overflow. Clear Twos Complement Overflow Set T in SREG Clear T in SREG Set Half Carry Flag in SREG Clear Half Carry Flag in SREG DATA TRANSFER INSTRUCTIONS MOV MOVW LDI LD LD LD LD LD LD LDD LD LD LD LDD LDS ST ST ST ST ST ST STD ST ST ST STD STS LPM LPM LPM SPM IN OUT PUSH POP NOP SLEEP WDR BREAK Rd, P P, Rr Rr Rd Rd, Z Rd, Z+ Rd, Rr Rd, Rr Rd, K Rd, X Rd, X+ Rd, - X Rd, Y Rd, Y+ Rd, - Y Rd,Y+q Rd, Z Rd, Z+ Rd, -Z Rd, Z+q Rd, k X, Rr X+, Rr - X, Rr Y, Rr Y+, Rr - Y, Rr Y+q,Rr Z, Rr Z+, Rr -Z, Rr Z+q,Rr k, Rr Move Between Registers Copy Register Word Load Immediate Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Direct from SRAM Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Direct to SRAM Load Program Memory Load Program Memory Load Program Memory and Post-Inc Store Program Memory In Port Out Port Push Register on Stack Pop Register from Stack No Operation Sleep Watchdog Reset Break (see specific descr. for Sleep function) (see specific descr. for WDR/Timer) For On-chip Debug Only MCU CONTROL INSTRUCTIONS None None None 10 ATtiny24/44/84 8006JS–AVR–07/10 ATtiny24/44/84 6. Ordering Information 6.1 ATtiny24 Speed (MHz) 10 Power Supply 1.8 - 5.5V Ordering Code(1) ATtiny24V-10SSU ATtiny24V-10PU ATtiny24V-10MU ATtiny24-20SSU ATtiny24-20PU ATtiny24-20MU Package(2) 14S1 14P3 20M1 14S1 14P3 20M1 Operational Range Industrial (-40°C to +85°C) Industrial (-40°C to +85°C) 20 Notes: 2.7 - 5.5V 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. Package Type 14S1 14P3 20M1 14-lead, 0.150" Wide Body, Plastic Gull Wing Small Outline Package (SOIC) 14-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 20-pad, 4 x 4 x 0.8 mm Body, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 11 8006JS–AVR–07/10 6.2 ATtiny44 Speed (MHz) 10 Power Supply 1.8 - 5.5V Ordering Code(1) ATtiny44V-10SSU ATtiny44V-10PU ATtiny44V-10MU ATtiny44-20SSU ATtiny44-20PU ATtiny44-20MU Package(2) 14S1 14P3 20M1 14S1 14P3 20M1 Operational Range Industrial (-40°C to +85°C) Industrial (-40°C to +85°C) 20 Notes: 2.7 - 5.5V 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. Package Type 14S1 14P3 20M1 14-lead, 0.150" Wide Body, Plastic Gull Wing Small Outline Package (SOIC) 14-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 20-pad, 4 x 4 x 0.8 mm Body, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 12 ATtiny24/44/84 8006JS–AVR–07/10 ATtiny24/44/84 6.3 ATtiny84 Speed (MHz) 10 Power Supply 1.8 - 5.5V Ordering Code(1) ATtiny84V-10SSU ATtiny84V-10PU ATtiny84V-10MU ATtiny84-20SSU ATtiny84-20PU ATtiny84-20MU Package(2) 14S1 14P3 20M1 14S1 14P3 20M1 Operational Range Industrial (-40°C to +85°C) Industrial (-40°C to +85°C) 20 Notes: 2.7 - 5.5V 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. Package Type 14S1 14P3 20M1 14-lead, 0.150" Wide Body, Plastic Gull Wing Small Outline Package (SOIC) 14-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 20-pad, 4 x 4 x 0.8 mm Body, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 13 8006JS–AVR–07/10 7. Packaging Information 7.1 20M1 D 1 Pin 1 ID 2 3 E SIDE VIEW TOP VIEW A2 D2 A1 A 1 Pin #1 Notch (0.20 R) 2 3 0.08 C E2 SYMBOL A A1 COMMON DIMENSIONS (Unit of Measure = mm) MIN 0.70 – NOM 0.75 0.01 0.20 REF 0.18 0.23 4.00 BSC 2.45 2.60 4.00 BSC 2.45 2.60 0.50 BSC 0.35 0.40 0.55 2.75 2.75 0.30 MAX 0.80 0.05 NOTE b L e BOTTOM VIEW A2 b D D2 E E2 e Note: Reference JEDEC Standard MO-220, Fig. 1 (SAW Singulation) WGGD-5. L 10/27/04 2325 Orchard Parkway San Jose, CA 95131 TITLE 20M1, 20-pad, 4 x 4 x 0.8 mm Body, Lead Pitch 0.50 mm, 2.6 mm Exposed Pad, Micro Lead Frame Package (MLF) DRAWING NO. 20M1 REV. A R 14 ATtiny24/44/84 8006JS–AVR–07/10 ATtiny24/44/84 7.2 14P3 D PIN 1 E1 A SEATING PLANE L B1 e E B A1 C eC eB SYMBOL A A1 D E E1 B Notes: 1. This package conforms to JEDEC reference MS-001, Variation AA. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). B1 L C eB eC e COMMON DIMENSIONS (Unit of Measure = mm) MIN – 0.381 18.669 7.620 6.096 0.356 1.143 2.921 0.203 – 0.000 NOM – – – – – – – – – – – MAX 5.334 – 19.685 8.255 7.112 0.559 1.778 3.810 0.356 10.922 1.524 Note 2 Note 2 NOTE 2.540 TYP 11/02/05 2325 Orchard Parkway San Jose, CA 95131 TITLE 14P3, 14-lead (0.300"/7.62 mm Wide) Plastic Dual Inline Package (PDIP) DRAWING NO. 14P3 REV. A R 15 8006JS–AVR–07/10 7.3 14S1 1 E E H N L Top View End View e A1 b SYMBOL COMMON DIMENSIONS (Unit of Measure = mm/inches) MIN NOM MAX NOTE A 1.35/0.0532 0.1/.0040 0.33/0.0130 8.55/0.3367 3.8/0.1497 5.8/0.2284 0.41/0.0160 – – – – – – – 1.27/0.050 BSC 1.75/0.0688 0.25/0.0098 0.5/0.0200 5 8.74/0.3444 3.99/0.1574 6.19/0.2440 1.27/0.0500 4 2 3 A A1 b D D E Side View H L e Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-012, Variation AB for additional information. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusion and gate burrs shall not exceed 0.15 mm (0.006") per side. 3. Dimension E does not include inter-lead Flash or protrusion. Inter-lead flash and protrusions shall not exceed 0.25 mm (0.010") per side. 4. L is the length of the terminal for soldering to a substrate. 5. The lead width B, as measured 0.36 mm (0.014") or greater above the seating plane, shall not exceed a maximum value of 0.61 mm (0.024") per side. 2/5/02 TITLE R DRAWING NO. 14S1, 14-lead, 0.150" Wide Body, Plastic Gull Wing Small Outline Package (SOIC) 14S1 2325 Orchard Parkway San Jose, CA 95131 REV. A 16 ATtiny24/44/84 8006JS–AVR–07/10 ATtiny24/44/84 8. Errata The revision letters in this section refer to the revision of the corresponding ATtiny24/44/84 device. 8.1 8.1.1 ATtiny24 Rev. D – E No known errata. 8.1.2 Rev. C • Reading EEPROM when system clock frequency is below 900 kHz may not work 1. Reading EEPROM when system clock frequency is below 900 kHz may not work Reading data from the EEPROM at system clock frequency below 900 kHz may result in wrong data read. Problem Fix/Work around Avoid using the EEPROM at clock frequency below 900 kHz. 8.1.3 Rev. B • EEPROM read from application code does not work in Lock Bit Mode 3 • Reading EEPROM when system clock frequency is below 900 kHz may not work 1. EEPROM read from application code does not work in Lock Bit Mode 3 When the Memory Lock Bits LB2 and LB1 are programmed to mode 3, EEPROM read does not work from the application code. Problem Fix/Work around Do not set Lock Bit Protection Mode 3 when the application code needs to read from EEPROM. 2. Reading EEPROM when system clock frequency is below 900 kHz may not work Reading data from the EEPROM at system clock frequency below 900 kHz may result in wrong data read. Problem Fix/Work around Avoid using the EEPROM at clock frequency below 900 kHz. 8.1.4 Rev. A Not sampled. 17 8006JS–AVR–07/10 8.2 8.2.1 ATtiny44 Rev. B – D No known errata. 8.2.2 Rev. A • Reading EEPROM when system clock frequency is below 900 kHz may not work 1. Reading EEPROM when system clock frequency is below 900 kHz may not work Reading data from the EEPROM at system clock frequency below 900 kHz may result in wrong data read. Problem Fix/Work around Avoid using the EEPROM at clock frequency below 900 kHz. 18 ATtiny24/44/84 8006JS–AVR–07/10 ATtiny24/44/84 8.3 8.3.1 ATtiny84 Rev. A – B No known errata. 19 8006JS–AVR–07/10 9. Datasheet Revision History 9.1 Rev I. - 06/10 1. Removed “Preliminary” from cover page. 2. Updated notes in Table 19-16, “High-voltage Serial Programming Instruction Set for ATtiny24/44/84,” on page 171. 3. Added clarification before Table 6-8, “Capacitance for the Low-Frequency Crystal Oscillator,” on page 28. 4. Updated some table notes in Section 20. “Electrical Characteristics” on page 174. 9.2 Rev H. 10/09 1. Updated document template. Re-arranged some sections. 2. Updated “Low-Frequency Crystal Oscillator” with the Table 6-8 on page 28 3. Updated Tables: – “Active Clock Domains and Wake-up Sources in Different Sleep Modes” on page 33 – “DC Characteristics” on page 174 – “Register Summary” on page 7 4. Updated Register Description: – “ADMUX – ADC Multiplexer Selection Register” on page 145 5. Signature Imprint Reading Instructions updated in “Reading Device Signature Imprint Table from Firmware” on page 156. 6. Updated Section: – Step 1. on page 164 7. Added Table: – “Analog Comparator Characteristics” on page 179 8. Updated Figure: – “Active Supply Current vs. frequency (1 - 20 MHz)” on page 187 9. Updated Figure 21-30 on page 201 and Figure 21-33 on page 202 under “Pin Threshold and Hysteresis”. 10. Changed ATtiny24/44 device status to “Not Recommended for New Designs. Use: ATtiny24A/44A”. 9.3 Rev G. 01/08 1. Updated sections: – “Features” on page 1 – “RESET” on page 3 – “Overview” on page 4 – “About” on page 6 – “SPH and SPL — Stack Pointer Register” on page 11 – “Atomic Byte Programming” on page 17 – “Write” on page 17 – “Clock Sources” on page 25 – “Default Clock Source” on page 30 20 ATtiny24/44/84 8006JS–AVR–07/10 ATtiny24/44/84 – “Sleep Modes” on page 33 – “Software BOD Disable” on page 34 – “External Interrupts” on page 49 – “USIBR – USI Data Buffer” on page 125 – “USIDR – USI Data Register” on page 124 – “DIDR0 – Digital Input Disable Register 0” on page 131 – “Features” on page 132 – “Prescaling and Conversion Timing” on page 135 – “Temperature Measurement” on page 144 – “ADMUX – ADC Multiplexer Selection Register” on page 145 – “Limitations of debugWIRE” on page 152 – “Reading Lock, Fuse and Signature Data from Software” on page 155 – “Device Signature Imprint Table” on page 161 – “Enter High-voltage Serial Programming Mode” on page 168 – “Absolute Maximum Ratings*” on page 174 – “DC Characteristics” on page 174 – “Speed” on page 175 – “Clock Characteristics” on page 176 – “Accuracy of Calibrated Internal RC Oscillator” on page 176 – “System and Reset Characteristics” on page 177 – “Supply Current of I/O Modules” on page 185 – “ATtiny24” on page 17 – “ATtiny44” on page 18 – “ATtiny84” on page 19 2. Updated bit definitions in sections: – “MCUCR – MCU Control Register” on page 36 – “MCUCR – MCU Control Register” on page 51 – “MCUCR – MCU Control Register” on page 67 – “PINA – Port A Input Pins” on page 68 – “SPMCSR – Store Program Memory Control and Status Register” on page 157 – “Register Summary” on page 7 3. Updated Figures: – “Reset Logic” on page 39 – “Watchdog Reset During Operation” on page 42 – “Compare Match Output Unit, Schematic (non-PWM Mode)” on page 95 – “Analog to Digital Converter Block Schematic” on page 133 – “ADC Timing Diagram, Free Running Conversion” on page 137 – “Analog Input Circuitry” on page 140 – “High-voltage Serial Programming” on page 167 – “Serial Programming Timing” on page 183 – “High-voltage Serial Programming Timing” on page 184 21 8006JS–AVR–07/10 – “Active Supply Current vs. Low Frequency (0.1 - 1.0 MHz)” on page 186 – “Active Supply Current vs. frequency (1 - 20 MHz)” on page 187 – “Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz)” on page 187 – “Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz)” on page 188 – “Active Supply Current vs. VCC (Internal RC Oscillator, 128 kHz)” on page 188 – “Idle Supply Current vs. Low Frequency (0.1 - 1.0 MHz)” on page 189 – “Idle Supply Current vs. Frequency (1 - 20 MHz)” on page 189 – “Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz)” on page 190 – “Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz)” on page 190 – “Idle Supply Current vs. VCC (Internal RC Oscillator, 128 kHz)” on page 191 – “Power-down Supply Current vs. VCC (Watchdog Timer Disabled)” on page 191 – “Power-down Supply Current vs. VCC (Watchdog Timer Enabled)” on page 192 – “Reset Pin Input Hysteresis vs. VCC” on page 202 – “Reset Pin Input Hysteresis vs. VCC (Reset Pin Used as I/O)” on page 203 – “Watchdog Oscillator Frequency vs. VCC” on page 205 – “Watchdog Oscillator Frequency vs. Temperature” on page 205 – “Calibrated 8 MHz RC Oscillator Frequency vs. VCC” on page 206 – “Calibrated 8 MHz RC oscillator Frequency vs. Temperature” on page 206 – “ADC Current vs. VCC” on page 207 – “Programming Current vs. VCC (ATtiny24)” on page 209 – “Programming Current vs. VCC (ATtiny44)” on page 209 – “Programming Current vs. VCC (ATtiny84)” on page 210 4. Added Figures: – “Reset Pin Output Voltage vs. Sink Current (VCC = 3V)” on page 198 – “Reset Pin Output Voltage vs. Sink Current (VCC = 5V)” on page 198 – “Reset Pin Output Voltage vs. Source Current (VCC = 3V)” on page 199 – “Reset Pin Output Voltage vs. Source Current (VCC = 5V)” on page 199 5. Updated Tables: – “Device Clocking Options Select” on page 25 – “Start-up Times for the Crystal Oscillator Clock Selection” on page 29 – “Start-up Times for the Internal Calibrated RC Oscillator Clock Selection” on page 27 – “Start-up Times for the External Clock Selection” on page 26 – “Start-up Times for the 128 kHz Internal Oscillator” on page 27 – “Active Clock Domains and Wake-up Sources in Different Sleep Modes” on page 33 – “Watchdog Timer Prescale Select” on page 47 – “Reset and Interrupt Vectors” on page 48 – “Overriding Signals for Alternate Functions in PA7:PA5” on page 63 – “Overriding Signals for Alternate Functions in PA4:PA2” on page 64 – “Overriding Signals for Alternate Functions in PA1:PA0” on page 64 – “Port B Pins Alternate Functions” on page 65 – “Overriding Signals for Alternate Functions in PB3:PB2” on page 66 22 ATtiny24/44/84 8006JS–AVR–07/10 ATtiny24/44/84 – “Overriding Signals for Alternate Functions in PB1:PB0” on page 67 – “Waveform Generation Modes” on page 110 – “ADC Conversion Time” on page 138 – “Temperature vs. Sensor Output Voltage (Typical Case)” on page 144 – “DC Characteristics. TA = -40°C to +85°C” on page 174 – “Calibration Accuracy of Internal RC Oscillator” on page 176 – “Reset, Brown-out, and Internal Voltage Characteristics” on page 177 – “VBOT vs. BODLEVEL Fuse Coding” on page 179 – “ADC Characteristics, Single Ended Channels. T = -40°C to +85°C” on page 180 – “ADC Characteristics, Differential Channels (Bipolar Mode), TA = -40°C to +85°C” on page 182 – “Serial Programming Characteristics, TA = -40°C to +85°C, VCC = 1.8 - 5.5V (Unless Otherwise Noted)” on page 183 – “High-voltage Serial Programming Characteristics TA = 25°C, VCC = 5V (Unless otherwise noted)” on page 184 6. Updated code examples in sections: – “Write” on page 17 – “SPI Master Operation Example” on page 119 7. Updated “Ordering Information” in: – “ATtiny84” on page 13 9.4 Rev F. 02/07 1. 2. Updated Figure 1-1 on page 2, Figure 8-7 on page 43, Figure 20-6 on page 184. Updated Table 9-1 on page 48, Table 10-7 on page 65, Table 11-2 on page 80, Table 11-3 on page 81, Table 11-5 on page 81, Table 11-6 on page 82, Table 11-7 on page 82, Table 11-8 on page 83, Table 20-11 on page 182, Table 20-13 on page 184. Updated table references in “TCCR0A – Timer/Counter Control Register A” on page 80. Updated Port B, Bit 0 functions in “Alternate Functions of Port B” on page 65. Updated WDTCR bit name to WDTCSR in assembly code examples. Updated bit5 name in “TIFR1 – Timer/Counter Interrupt Flag Register 1” on page 114. Updated bit5 in “TIFR1 – Timer/Counter Interrupt Flag Register 1” on page 114. Updated “SPI Master Operation Example” on page 119. Updated step 5 in “Enter High-voltage Serial Programming Mode” on page 168. 3. 4. 5. 6. 7. 8. 9. 9.5 Rev E. 09/06 1. 2. 3. 4. 5. 6. All characterization data moved to “Electrical Characteristics” on page 174. All Register Descriptions gathered up in separate sections at the end of each chapter. Updated “System Control and Reset” on page 39. Updated Table 11-3 on page 81, Table 11-6 on page 82, Table 11-8 on page 83, Table 12-3 on page 109 and Table 12-5 on page 110. Updated “Fast PWM Mode” on page 97. Updated Figure 12-7 on page 98 and Figure 16-1 on page 133. 23 8006JS–AVR–07/10 7. 8. 9. 10. Updated “Analog Comparator Multiplexed Input” on page 129. Added note in Table 19-12 on page 165. Updated “Electrical Characteristics” on page 174. Updated “Typical Characteristics” on page 185. 9.6 Rev D. 08/06 1. 2. 3. 4. 5. 6. Updated “Calibrated Internal 8 MHz Oscillator” on page 26. Updated “OSCCAL – Oscillator Calibration Register” on page 30. Added Table 20-2 on page 176. Updated code examples in “SPI Master Operation Example” on page 119. Updated code examples in “SPI Slave Operation Example” on page 121. Updated “Signature Bytes” on page 162. 9.7 Rev C. 07/06 1. 2. 3. 4. Updated Features in “USI – Universal Serial Interface” on page 117. Added “Clock speed considerations” on page 123. Updated Bit description in “ADMUX – ADC Multiplexer Selection Register” on page 145. Added note to Table 18-1 on page 157. 9.8 Rev B. 05/06 1. 2. 3. Updated “Default Clock Source” on page 30 Updated “Power Reduction Register” on page 35. Updated Table 20-4 on page 177, Table 9-4 on page 42, Table 16-3 on page 145, Table 19-5 on page 161, Table 19-12 on page 165, Table 19-16 on page 171, Table 2011 on page 182. Updated Features in “Analog to Digital Converter” on page 132. Updated Operation in “Analog to Digital Converter” on page 132. Updated “Temperature Measurement” on page 144. Updated DC Characteristics in “Electrical Characteristics” on page 174. Updated “Typical Characteristics” on page 185. Updated “Errata” on page 17. 4. 5. 6. 7. 8. 9. 9.9 Rev A. 12/05 Initial revision. 24 ATtiny24/44/84 8006JS–AVR–07/10 Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 International Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Product Contact Web Site www.atmel.com Technical Support avr@atmel.com Sales Contact www.atmel.com/contacts Literature Requests www.atmel.com/literature Disclaimer: T he information in this document is provided in connection with Atmel products. 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