ATTINY87-XU

Features • High Performance, Low Power AVR® 8-Bit Microcontroller • Advanced RISC Architecture – 123 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation Non-volatile Program and Data Memories – 8K/16K Bytes of In-System Programmable Flash Program Memory • Endurance: 10,000 Write/Erase Cycles – 512 Bytes of In-System Programmable EEPROM • Endurance: 100,000 Write/Erase Cycles – 512 Bytes of Internal SRAM – Data retention: 20 Years at 85°C / 100 Years at 25°C – In-System Programmable via SPI Port – Low size LIN/UART Software In-System Programmable – Programming Lock for Software Security Peripheral Features – LIN 2.1 and 1.3 Controller or 8-Bit UART – One 8-bit Asynchronous Timer/Counter with Prescaler • Output Compare or 8-bit PWM Channel – One 16-bit Synchronous Timer/Counter with Prescaler • External Event Counter • 2 Output Compare Units or PWM Channels each Driving up to 4 Output Pins – Master/Slave SPI Serial Interface – Universal Serial Interface with Start Condition Detector – 10-bit ADC • 11 Single Ended Channels • 8 Differential ADC Channel Pairs with Programmable Gain (8x or 20x) – On-chip Analog Comparator with Selectable Voltage Reference – 100µA ±10% Current Source for LIN Node Identification – On-chip Temperature Sensor – Programmable Watchdog Timer with Separate On-chip Oscillator Special Microcontroller Features – Software Controlled Clock Switching for Power Control, EMC Reduction – debugWIRE On-chip Debug System – External and Internal Interrupt Sources – Low Power Idle, ADC Noise Reduction, and Power-down Modes – Power-on Reset and Programmable Brown-out Detection – Internal 8MHz Calibrated Oscillator – 4-16 MHz and 32 KHz Crystal/Ceramic Resonator Oscillators I/O and Packages – 16 Programmable I/O Lines – 20-pin SOIC, 32-pad MLF and 20-pin TSSOP Operating Voltage: – 1.8 – 5.5V for ATtiny87/167 Speed Grade: – 0 – 4 MHz @ 1.8 – 5.5V – 0 – 8 MHz @ 2.7 – 5.5V – 0 – 16 MHz @ 4.5 – 5.5V Industrial Temperature Range • • 8-bit Microcontroller with 8K/16K Bytes In-System Programmable Flash and LIN Controller ATtiny87 ATtiny167 Preliminary • • • • • Rev. 8265A–AVR–08/10 1. Description 1.1 Comparison Between ATtiny87 and ATtiny167 ATtiny87 and ATtiny167 are hardware and software compatible. They differ only in memory sizes as shown in Table 1-1. Table 1-1. Device ATtiny167 ATtiny87 Memory Size Summary Flash 16K Bytes 8K Bytes Flash 512 Bytes 512 Bytes Flash 512 Bytes 512 Bytes Interrupt Vector size 2-instruction-words / vector 2-instruction-words / vector 1.2 Part Description The ATtiny87/167 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny87/167 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATtiny87/167 provides the following features: 8K/16K byte of In-System Programmable Flash, 512 bytes EEPROM, 512 bytes SRAM, 16 general purpose I/O lines, 32 general purpose working registers, one 8-bit Timer/Counter with compare modes, one 8-bit high speed Timer/Counter, Universal Serial Interface, a LIN controller, Internal and External Interrupts, a 11-channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, and three software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counter, ADC, Analog Comparator, and Interrupt system to continue functioning. The Power-down mode saves the register contents, disabling all chip functions until the next Interrupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize switching noise during ADC conversions. The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI serial interface, by a conventional non-volatile memory programmer or by an On-chip boot code running on the AVR core. The Boot program can use any interface to download the application program in the Flash memory. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATtiny87/167 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATtiny87/167 AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits. 2 ATtiny87/ATtiny167 8265A–AVR–08/10 ATtiny87/ATtiny167 1.3 Block Diagram Figure 1-1. Block Diagram GND VCC Watchdog Timer Watchdog Oscillator Power Supervision POR / BOD & RESET debugWIRE PROGRAM LOGIC Oscillator Circuits / Clock Generation Flash SRAM CPU EEPROM AVCC AGND Timer/Counter-1 DATABUS Timer/Counter-0 A/D Conv. SPI & USI Analog Comp. 2 Internal Voltage References 11 PORT B (8) PORT A (8) LIN / UART RESET XTAL[1;2] PB[0..7] PA[0..7] 3 8265A–AVR–08/10 1.4 Pin Configuration Pinout ATtiny87/167 - SOIC20 & TSSOP20 Figure 1-2. (RXLIN / RXD / ADC0 / PCINT0) PA0 (TXLIN / TXD / ADC1 / PCINT1) PA1 (MISO / DO / OC0A / ADC2 / PCINT2) PA2 (INT1 / ISRC / ADC3 / PCINT3) PA3 AVCC AGND (MOSI / SDA / DI / ICP1 / ADC4 / PCINT4) PA4 (SCK / SCL / USCK / T1 / ADC5 / PCINT5) PA5 (SS / AIN0 / ADC6 / PCINT6) PA6 (AREF / XREF / AIN1 / ADC7 / PCINT7) PA7 1 20 2 19 18 3 4 20-pin 17 5 16 6 top 15 7 view 14 8 13 9 12 10 11 PB0 (PCINT8 / OC1AU / DI / SDA) PB1 (PCINT9 / OC1BU / DO) PB2 (PCINT10 / OC1AV / USCK / SCL) PB3 (PCINT11 / OC1BV) GND VCC PB4 (PCINT12 / OC1AW / XTAL1 / CLKI) PB5 (PCINT13 / ADC8 / OC1BW / XTAL2 / CLKO) PB6 (PCINT14 / ADC9 / OC1AX / INT0) PB7 (PCINT15 / ADC10 / OC1BX / RESET / dW) Figure 1-3. Pinout ATtiny87/167 - QFN32/MLF32 nc PA2 (PCINT2 / ADC2 / OC0A / DO / MISO) PA1 (PCINT1 / ADC1 / TXD / TXLIN) PA0 (PCINT0 / ADC0 / RXD / RXLIN) PB0 (PCINT8 / OC1AU / DI / SDA) PB1 (PCINT9 / OC1BU / DO) PB2 (PCINT10 / OC1AV / USCK / SCL) PB3 (PCINT11 / OC1BV) 32 31 29 28 27 30 26 25 INDEX CORNER nc nc (INT1 / ISRC / ADC3 / PCINT3) PA3 AVCC AGND nc nc nc 1 2 3 4 5 6 7 8 10 12 13 14 15 24 23 22 21 20 19 18 17 16 11 9 32-lead top view nc nc nc GND VCC PB4 (PCINT12 / OC1AW / XTAL1 / CLKI) PB5 (PCINT13 / ADC8 / OC1BW / XTAL2 / CLKO) nc (MOSI / SDA / DI / ICP1 / ADC4 / PCINT4) PA4 (SCK / SCL / USCK / T1 / ADC5 / PCINT5) PA5 (SS / AIN0 / ADC6 / PCINT6) PA6 (AREF / XREF / AIN1 / ADC7 / PCINT7) PA7 nc (dW / RESET / OC1BX / ADC10 / PCINT15) PB7 (INT0 / OC1AX / ADC9 / PCINT14 ) PB6 nc Bottom pad should be soldered to ground 4 ATtiny87/ATtiny167 8265A–AVR–08/10 ATtiny87/ATtiny167 1.5 1.5.1 Pin Description VCC Supply voltage. 1.5.2 GND Ground. 1.5.3 AVCC Analog supply voltage. 1.5.4 AGND Analog ground. 1.5.5 Port A (PA7:PA0) Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various special features of the ATtiny87/167 as listed on Section 9.3.3 “Alternate Functions of Port A” on page 76. 1.5.6 Port B (PB7:PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATtiny87/167 as listed on Section 9.3.4 “Alternate Functions of Port B” on page 81. 5 8265A–AVR–08/10 1.6 Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 1.7 About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details. 1.8 Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. 1.9 Disclaimer Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device has been characterized. 6 ATtiny87/ATtiny167 8265A–AVR–08/10 ATtiny87/ATtiny167 2. AVR CPU Core 2.1 Overview This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Figure 2-1. Block Diagram of the AVR Architecture Data Bus 8-bit Flash Program Memory Program Counter Status and Control Interrupt Unit 32 x 8 General Purpose Registrers Watchdog Timer Instruction Register Indirect Addressing Instruction Decoder Direct Addressing A.D.C. ALU Control Lines Analog Comparator I/O Module1 Data SRAM I/O Module 2 I/O Module n EEPROM I/O Lines In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the Program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the Program memory. This concept enables instructions to be executed in every clock cycle. The Program memory is In-System Reprogrammable Flash memory. The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. 7 8265A–AVR–08/10 Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash Program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation. Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every Program memory address contains a 16- or 32-bit instruction. During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority. The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O memory can be accessed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F. 2.2 ALU – Arithmetic Logic Unit The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description. 2.3 Status Register The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. 8 ATtiny87/ATtiny167 8265A–AVR–08/10 ATtiny87/ATtiny167 2.3.1 SREG – AVR Status Register The AVR Status Register – SREG – is defined as: Bit 0x3F (0x5F) Read/Write Initial Value 7 I R/W 0 6 T R/W 0 5 H R/W 0 4 S R/W 0 3 V R/W 0 2 N R/W 0 1 Z R/W 0 0 C R/W 0 SREG • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference. • Bit 6 – T: Bit Copy Storage The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction. • Bit 5 – H: Half Carry Flag The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is useful in BCD arithmetic. See the “Instruction Set Description” for detailed information. • Bit 4 – S: Sign Bit, S = N ⊕ V The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See the “Instruction Set Description” for detailed information. • Bit 3 – V: Two’s Complement Overflow Flag The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction Set Description” for detailed information. • Bit 2 – N: Negative Flag The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 1 – Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. 9 8265A–AVR–08/10 2.4 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: • One 8-bit output operand and one 8-bit result input • Two 8-bit output operands and one 8-bit result input • Two 8-bit output operands and one 16-bit result input • One 16-bit output operand and one 16-bit result input Figure 2-2 shows the structure of the 32 general purpose working registers in the CPU. Figure 2-2. AVR CPU General Purpose Working Registers 7 R0 R1 R2 … R13 General Purpose Working Registers R14 R15 R16 R17 … R26 R27 R28 R29 R30 R31 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F X-register Low Byte X-register High Byte Y-register Low Byte Y-register High Byte Z-register Low Byte Z-register High Byte 0x0D 0x0E 0x0F 0x10 0x11 0 Addr. 0x00 0x01 0x02 Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions. As shown in Figure 2-2, each register is also assigned a Data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file. 2.4.1 The X-register, Y-register, and Z-register The registers R26:R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 2-3 on page 11. 10 ATtiny87/ATtiny167 8265A–AVR–08/10 ATtiny87/ATtiny167 Figure 2-3. The X-, Y-, and Z-registers 15 X-register 7 R27 (0x1B) 15 Y-register 7 R29 (0x1D) 15 Z-register 7 R31 (0x1F) ZH 0 7 R30 (0x1E) YH 0 7 R28 (0x1C) ZL 0 0 XH 0 7 R26 (0x1A) YL 0 0 XL 0 0 In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 2.5 Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations to lower memory locations. This implies that a Stack PUSH command decreases the Stack Pointer. The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to point above 0x60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when the return address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when data is popped from the Stack with return from subroutine RET or return from interrupt RETI. The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present 2.5.1 SPH and SPL – Stack Pointer Register Bit 0x3E (0x5E) 0x3D (0x5D) Read/Write Initial Value 15 SP15 SP7 7 R/W R/W 14 SP14 SP6 6 R/W R/W 13 SP13 SP5 5 R/W R/W 12 SP12 SP4 4 R/W R/W 11 SP11 SP3 3 R/W R/W 10 SP10 SP2 2 R/W R/W 9 SP9 SP1 1 R/W R/W 8 SP8 SP0 0 R/W R/W SPH SPL ISRAM end (See Table 3-1 on page 15) 11 8265A–AVR–08/10 2.6 Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. Figure 2-4 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. Figure 2-4. The Parallel Instruction Fetches and Instruction Executions T1 T2 T3 T4 clkCPU 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch Figure 2-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. Figure 2-5. Single Cycle ALU Operation T1 T2 T3 T4 clkCPU Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back 2.7 Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate Program Vector in the Program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt. The lowest addresses in the Program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in Section 7. “Interrupts” on page 59. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. 12 ATtiny87/ATtiny167 8265A–AVR–08/10 ATtiny87/ATtiny167 2.7.1 Interrupt behavior When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed. There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority. The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software. When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence. Assembly Code Example in cli sbi sbi out r16, SREG EECR, EEMPE EECR, EEPE SREG, r16 ; restore SREG value (I-bit) ; store SREG value ; start EEPROM write ; disable interrupts during timed sequence C Code Example char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ _CLI(); EECR |= (1