ATV2500B-12JC

Features • High Performance, High Density Programmable Logic Device – Typical 7 ns Pin-to-Pin Delay – Fully Connected Logic Array With 416 Product Terms • Flexible Output Macrocell – 48 Flip-Flops - Two per Macrocell – 72 Sum Terms – All Flip-Flops, I/O Pins Feed In Independently – Achieves Over 80% Gate Utilization • Enhanced Macrocell Configuration Selections – D- or T-Type Flip-Flops – Product Term or Direct Input Pin Clocking – Registered or Combinatorial Internal Feedback • Several Power Saving Options Device ATV2500B ATV2500BQ ATV2500BL ATV2500BQL ICC, Stand-By 110 mA 30 mA 2 mA 2 mA High-Speed High-Density UV Erasable Programmable Logic Device ATV2500B • • • • Backward Compatible With ATV2500H/L Software Proven and Reliable High Speed UV EPROM Process Reprogrammable - Tested 100% for Programmability 40-Pin Dual-In-Line and 44-Pin Lead Surface Mount Packages Block Diagram Pin Configurations Pin Name IN CLK/IN I/O I/O 0,2,4.. I/O 1,3,5.. GND VCC Note: Function Logic Inputs Pin Clock and Input Bidirectional Buffers “Even” I/O Buffers “Odd” I/O Buffers Ground +5V Supply For ATV2500BQ and ATV2500BQL (PLCC/LCC package only) pin 4 and pin 26 connections are not required. DIP CLK/IN IN IN I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 VCC I/O17 I/O16 I/O15 I/O14 I/O13 I/O12 IN IN IN IN LCC/PLCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 IN IN IN IN I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 GND I/O23 I/O22 I/O21 I/O20 I/O19 I/O18 IN IN IN Rev. 0249F–06/98 1 Functional Logic Diagram ATV2500B Note: 1. Not required for PLCC versions of ATV2500BQ or ATV2500BQL, making them compatible with ATV2500H and ATV2500L pinout. 2 ATV2500B ATV2500B Description The ATV2500Bs are the highest density PLDs available in a 40- or 44-pin package. With their fully connected logic array and flexible macrocell structure, high gate utilization is easily obtainable. The ATV2500Bs are organized around a single universal and-or array. All pin and feedback terms are always available to every macrocell. Each of the 38 logic pins are array inputs, as are the outputs of each flip-flop. In the ATV2500Bs, four product terms are input to each sum term. Furthermore, each macrocell's three sum terms can be combined to provide up to 12 product terms per sum term with no performance penalty . Each flip-flop is individually selectable to be either D- or T-type, providing further logic compaction. Also, 24 of the flip-flops may be bypassed to provide internal combinatorial feedback to the logic array. Product terms provide individual clocks and asynchronous resets for each flip-flop. The flip-flops may also be individually configured to have direct input pin clocking. Each output has its own enable product term. Eight synchronous preset product terms serve local groups of either four or eight flip-flops. Register preload functions are provided to simplify testing. All registers automatically reset upon power up. Several low power device options allow selection of the optimum solution for many power-sensitive applications. Each of the options significantly reduces total system power and enhances system reliability. Functional Logic Diagram Description The ATV2500B functional logic diagram describes the interconnections between the input, feedback pins and logic cells. All interconnections are routed through the single global bus. The ATV2500Bs are straightforward and uniform PLDs. The 24 macrocells are numbered 0 through 23. Each macrocell contains 17 AND gates. All AND gates have 172 inputs. The five lower product terms provide AR1, CK1, CK2, AR2, and OE. These are: one asynchronous reset and clock per flip-flop, and an output enable. The top 12 product terms are grouped into three sum terms, which are used as shown in the macrocell diagrams. Eight synchronous preset terms are distributed in a 2/4 pattern. The first four macrocells share Preset 0, the next two share Preset 1, and so on, ending with the last two macrocells sharing Preset 7. The 14 dedicated inputs and their complements use the numbered positions in the global bus as shown. Each macrocell provides six inputs to the global bus: (left to right) feedback F2 (1) true and false, flip-flop Q1 true and false, and the pin true and false. The positions occupied by these signals in the global bus are the six numbers in the bus diagram next to each macrocell. Note: 1. Either the flip-flop input (D/T2) or output (Q2) may be fed back in the ATV2500Bs. 3 Absolute Maximum Ratings* emperature Under Bias.................................. -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C Voltage on Any Pin with Respect to Ground ........................................-2.0V to +7.0V (1) Voltage on Input Pins with Respect to Ground During Programming....................................-2.0V to +14.0V (1) Programming Voltage with Respect to Ground ......................................-2.0V to +14.0V (1) Integrated UV Erase Dose..............................7258 W•sec/cm2 *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Minimum voltage is -0.6V dc which may undershoot to -2.0V for pulses of less than 20ns. Maximum output pin voltage is VCC+0.75V dc which may overshoot to +7.0V for pulses of less than 20ns. Note: 1. DC and AC Operating Conditions Commercial Operating Temperature (Case) VCC Power Supply 0°C - 70°C 5V ± 5% Industrial -40°C - 85°C 5V ± 10% Military -55°C - 125°C 5V ± 10% Pin Capacitance (f = 1 MHz, T = 25°C) (1) Typ CIN COUT Note: 4 8 Max 6 12 Units pF pF VIN = 0V VOUT = 0V Conditions 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. 4 ATV2500B ATV2500B Output Logic, Registered(1) Output Logic, Combinatiorial(1) Note: 1. S2 = 0 These diagrams show equivalent logic functions, not necessarily the actual circuit implementation. Terms in S0 0 0 1 D/T1 8 12 8 D/T2 4 4 (1) S2 = 1 Output Configuration Registered (Q1); Q2 FB Registered (Q1); Q2 FB Registered (Q1); D/T2 FB X X 0 1 1 1 1 0 1 1 S5 X S1 0 S0 0 Terms in D/T1 4(1) 4 4(1) 4(1) 4 D/T2 4 4 4(1) 4 4 Output Configuration Combinatorial (8 Terms); Q2 FB Combinatorial (4 Terms); Q2 FB Combinatorial (12 Terms); Q2 FB Combinatorial (8 Terms); D/T2 FB Combinatorial (4 Terms); D/T2 FB S1 0 1 1 4 S3 0 1 S4 0 1 S5 0 1 Ouput Configuration Active Low Active High Register 1 Type D T Register 2 Type D T S6 0 1 S7 0 1 Q1 CLOCK CK1 CK1 • PIN1 Q2 CLOCK CK2 CK2 • PIN1 1 0 Note: 1. These four terms are shared with D/T1. Clock Option 5 DC Characteristics Symbol IIL ILO Parameter Input Load Current Output Leakage Current Condition VIN = -0.1V to VCC + 1V VOUT = -0.1V to VCC + 0.1V Com. ATV2500B Ind., Mil. Com. ICC Power Supply Current, Standby VCC = MAX, VIN = GND or VCC f = 0 MHz, Outputs Open ATV2500BQ Ind., Mil. Com. ATV2500BL Ind., Mil. Com. ATV2500BQL Ind., Mil. IOS VIL VIH VOL Output Short Circuit Current Input Low Voltage Input High Voltage VIN = VIH or VIL, VCC = 4.5V IOL = 8 mA IOL = 6 mA IOH = -4.0 mA IOH = -4.0 mA Com., Ind. Mil. VCC - 0.3 2.4 VOUT = 0.5V MIN ≤ VCC ≤ MAX -0.6 2.0 2 5 -120 0.8 VCC + 0.75 0.5 0.5 mA mA V V V V V 2 2 10 4 mA mA 30 2 85 5 mA mA 110 30 210 70 mA mA 110 Min Typ Max 10 10 190 Units µA µA mA Output Low Voltage VOH Note: Output High Voltage VCC = MIN 1. See ICC versus frequency characterization curves. 6 ATV2500B ATV2500B AC Waveforms(1) Input Pin Clock AC Waveforms(1) Product Term Clock Note: 1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise speicified. Register AC Characteristics, Input Pin Clock -12 Symbol tCOS tCFS tSIS tSFS tHS tWS tPS Parameter Clock to Output Clock to Feedback Input Setup Time Feedback Setup Time Hold Time Clock Width Clock Period External Feedback 1/(tSIS + tCOS) FMAXS Internal Feedback 1/(tSFS + tCFS) No Feedback 1/(tPS) tARS Asynchronous Reset/Preset Recovery Time 7 0 7 7 0 5 10 69 90 100 12 Min Max Min -15 Max Min -20 Max Min -25 Max Min -30 Max Units ns ns ns ns ns ns ns 7.5 4 0 9 9 0 6 12 10 5 0 14 14 0 7 14 52 71 83 15 11 6 0 20 20 0 8 16 40 50 71 20 12 7 0 23 23 0 9 18 31 37 62 25 15 8 26 32 55 MHz MHz MHz ns 7 Register AC Characteristics, Product Term Clock -12 Symbol tCOA tCFA tSIA tSFA tHA tWA tPA Parameter Clock to Output Clock to Feedback Input Setup Time Feedback Setup Time Hold Time Clock Width Clock Period External Feedback 1/(tSIA + tCOA) FMAXA Internal Feedback 1/(tSFA + tCFA) No Feedback 1/(tPS) tARA Asynchronous Reset/Preset Recovery Time 3 3 4 4 3 5.5 11 62.5 90 90 8 Min Max Min -15 Max Min -20 Max Min -25 Max Min -30 Max Units ns ns ns ns ns ns ns 12 7 5 5 5 5 7.5 15 15 12 10 10 8 10 11 22 50 58 66 12 20 16 12 15 10 12 14 28 33 38 45 15 22 18 13 19 10 13 15 30 27 36 36 18 25 20 23 24 33 MHz MHz MHz ns AC Waveforms(1) Combinatorial Outputs and Feedback Note: 1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified. 8 ATV2500B ATV2500B AC Characteristics -12 Symbol tPD1 tPD2 tPD3 tPD4 tEA1 tER1 tEA2 tER2 tAW tAP tAPF Parameter Input to Non-Registered Output Feedback to Non-Registered Output Input to Non-Registered Feedback Feedback to Non-Registered Feedback Input to Output Enable Input to Output Disable Feedback to Output Enable Feedback to Output Disable Asynchronous Reset Width Asynchronous Reset to Registered Output Asynchronous Reset to Registered Feedback 6 15 12 Min Max Mi n -15 Ma x Min -20 Ma x Min -25 Ma x Min -30 Ma x Units ns ns ns ns ns ns ns ns ns 12 12 8 8 12 12 12 12 8 15 15 11 11 15 15 15 15 12 18 15 20 20 15 15 20 20 20 20 15 22 19 25 25 18 18 25 25 25 25 18 28 25 30 30 20 20 30 30 30 30 30 30 ns ns Input Test Waveforms and Measurement Levels Output Test Load Preload and Observability of Registered Outputs The ATV2500Bs registers are provided with circuitry to allow loading of each register asynchronously with either a high or a low. This feature will simplify testing since any state can be forced into the registers to control test sequencing. A VIH level on the odd I/O pins will force the appropriate register high; a VIL will force it low, independent of the polarity or other configuration bit settings. The PRELOAD state is entered by placing an 10.25V to 10.75V signal on SMP lead 42. When the preload clock SMP lead 23 is pulsed high, the data on the I/O pins is placed into the 12 registers chosen by the Q select and even/odd select pins. Register 2 observability mode is entered by placing an 10.25V to 10.75V signal on pin/lead 2. In this mode, the contents of the buried register bank will appear on the associated outputs when the OE control signals are active. 9 Level forced on Odd I/O pin during PRELOAD cycle Q Select Pin State Even/Odd Select Even Q1 state after cycle Even Q2 state after cycle Odd Q1 state after cycle Odd Q2 state after cycle VIH/VIL VIH/VIL VIH/VIL VIH/VIL Low High Low High Low Low High High High/Low X X X X High/Low X X X X High/Low X X X X High/Low Power-Up Reset The registers in the ATV2500Bs are designed to reset during power up. At a point delayed slightly from VCC crossing VRST, all registers will be reset to the low state. The output state will depend on the polarity of the output buffer. This feature is critical for state as nature of reset and the uncertainty of how VCC actually rises in the system, the following conditions are required: 1. The VCC rise must be monotonic, 2. After reset occurs, all input and feedback setup times must be met before driving the clock pin or terms high, and 3. The clock pin, and any signals from which clock terms are derived, must remain stable during t PR. Parameter tPR VRST Description Power-Up Reset Time Power-Up Reset Voltage Typ 600 3.8 Max 1000 4.5 Units ns V 10 ATV2500B ATV2500B Security Fuse Usage A single fuse is provided to prevent unauthorized copying of ATV2500B fuse patterns. Once programmed, the outputs will read programmed during verify. The security fuse should be programmed last, as its effect is immediate. The security fuse also inhibits Preload and Q2 observability. • A Total of 48 Registers The ATV2500B provides two flip-flops per macrocell - a total of 48. Each register has its own clock and reset terms, as well as its own sum term. • Independent I/O Pin and Feedback Paths Each I/O pin on the ATV2500B has a dedicated input path. Each of the 48 registers has its own feedback term into the array as well. These features, combined with individual product terms for each I/O's output enable, facilitate true bidirectional I/O design. • Combinable Sum Terms Each output macrocell's three sum terms may be combined into a single term. This provides a fan in of up to 12 product terms per sum term with no speed penalty. Atmel CMOS PLDs The ATV2500Bs utilize an advanced 0.65-micron CMOS EPROM technology. This technology's state of the art features are the optimum combination for PLDs: • CMOS technology provides high speed, low power, and high noise immunity. • EPROM technology is the most cost effective method for producing PLDs - surpassing bipolar fusible link technology in low cost, while providing the necessary reprogrammability. • EPROM reprogrammability, which is 100% tested before shipment, provides inherently better programmability and reliability than one-time fusible PLDs. Programming Software Support As with all other Atmel PLDs, several third party PLD development software products and programmers will support the ATV2500Bs. S ev e r al th i r d pa r ty p r og r am m er s wi l l s u pp o r t th e ATV2500B as well. Additionally, the ATV2500B may be programmed to perform the ATV2500H/Ls functional subset (no T-type flip-flops, pin clocking or D/T2 feedback) using the ATV2500H/L JEDEC file. In this case, the ATV2500B becomes a direct replacement or speed upgrade for the ATV2500H/L (additional GND connections are required). Please refer to the Programmable Logic Development Tools section for a complete PLD software and programmer listing. Using the ATV2500Bs Many Advanced Features The ATV2500Bs advanced flexibility packs more usable gates into 44 leads than other PLDs. Some of the ATV2500Bs key features are: • Fully Connected Logic Array Each array input is always available to every product term. This makes logic placement a breeze. • Selectable D- and T-Type Registers Each ATV2500B flip-flop can be individually configured as either D- or T-type. Using the T-type configuration, JK and SR flip-flops are also easily created. These options allow more efficient product term usage. • Buried Combinatorial Feedback Each macrocell's Q2 register may be bypassed to feed its input (D/T2) directly back to the logic array. This provides further logic expansion capability without using precious pin resources. • Selectable Synchronous/Asynchronous Clocking Each of the ATV2500Bs flip-flops has a dedicated clock product term. This removes the constraint that all registers use the same clock. Buried state machines, counters and registers can all coexist in one device while running on separate clocks. Individual flip-flop clock source selection further allows mixing higher performance pin clocking and flexible product term clocking within one design. Erasure Characteristics The entire memory array of an ATV2500B is erased after exposure to ultraviolet light at a wavelength of 2537 Å. Complete erasure is assured after a minimum of 20 minutes exposure using 12,000 µ W/cm 2 i ntensity lamps spaced one inch away from the chip. Minimum erase time for lamps at other intensity ratings can be calculated from the minimum integrated erasure dose of 15 W•sec/cm2. To prevent unintentional erasure, an opaque label is recommended to cover the clear window on any UV erasable PLD which will be subjected to continuous fluorescent indoor lighting or sunlight. 11 Note: 1. All normalized values referenced to maximum specification in AC Characteristics of data sheet. 12 ATV2500B ATV2500B OUTPUT SOURCE CURRENT vs. OUTPUT VOLT AGE (VCC=5V, TA=25°C) 0 -1 -2 -3 I O H m A -4 -5 3.5 3.8 4.1 4.4 4.7 5.0 OUTPUT VOLT AGE (V) OUTPUT SOURCE CURRENT 0 vs. OUTPUT VOLT AGE (VCC=5V,TA=25°C) I -20 O H -40 m A -60 -80 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 OUTPUT VOLT AGE (V) NORMALIZED TPD vs. AMBIENT TEMPERATURE (VCC = 5V) 1.3 N O R M T P D ATV2500B(L) 1.2 1.1 1.0 ATV2500BQ (L) 0.9 0.8 -55 -25 5 35 65 95 125 AMBIENT TEMPERATURE (C) NORMALIZED TCO vs. SUPPLY VOLTAGE (TA=25°C) 1.3 1.3 NORMALIZED TCO vs. AMBIENT TEMPERATURE (VCC = 5V) N O R M T C O N O R M T C O 1.2 1.1 1.2 1.1 1.0 ATV2500B(L) ATV2500BQ(L) 1.0 ATV2500B(L) 0.9 0.8 4.50 4.75 5.00 5.25 5.50 ATV2500BQ (L) 0.9 0.8 -55 -25 5 35 65 95 125 SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE (C) Note: 1. All normalized values referenced to maximum specification in AC Characteristics of data sheet. 13 Note: 1. All normalized values referenced to maximum specification in AC Characteristics of data sheet. 14 ATV2500B ATV2500B Ordering Information tPD (ns) 12 15 tCOS (ns) 7.5 10 Ext. fMAXS (MHz) 69 52 Ordering Code ATV2500B-12JC ATV2500B-12KC ATV2500B-15JC ATV2500B-15KC ATV2500B-15JI ATV2500B-15KI ATV2500B-15KM ATV2500B-15LM ATV2500B-15KM/883 ATV2500B-15LM/883 20 11 40 ATV2500BL-20JC ATV2500BL-20KC ATV2500BL-20JI ATV2500BL-20KI ATV2500BL-20KM ATV2500BL-20LM ATV2500BL-20KM/883 ATV2500BL-20LM/883 20 11 40 ATV2500BQ-20DC ATV2500BQ-20JC ATV2500BQ-20KC ATV2500BQ-20PC 25 12 31 ATV2500BQ-25DC ATV2500BQ-25JC ATV2500BQ-25KC ATV2500BQ-25PC ATV2500BQ-25DI ATV2500BQ-25JI ATV2500BQ-25KI ATV2500BQ-25PI ATV2500BQ-25DM ATV2500BQ-25KM ATV2500BQ-25LM ATV2500BQ-25DM/883 ATV2500BQ-25KM/883 ATV2500BQ-25LM/883 Package 44J 44KW 44J 44KW 44J 44KW 44KW 44LW 44KW 44LW 44J 44KW 44J 44KW 44KW 44LW 44KW 44LW 40DW6 44J 44KW 40P6 40DW6 44J 44KW 40P6 40DW6 44J 44KW 40P6 40DW6 44KW 44LW 40DW6 44KW 44LW Military/883C (-55°C to 125°C) Class B, Fully Compliant Military/883C (-55°C to 125°C) Industrial (-40°C to 85°C) Commercial (0°C to 70°C) Operation Range Commercial (0°C to 70°C) Commercial (0°C to 70°C) Industrial (-40°C to 85°C) Military (-55°C to 125°C) Military/883C (-55°C to 125°C) Class B, Fully Compliant Commercial (0°C to 70°C) Industrial (-40°C to 85°C) Military (-55°C to 125°C) Military/883C (-55°C to 125°C) Class B, Fully Compliant Commercial (0°C to 70°C) 15 Ordering Information (Continued) tPD (ns) 25 tCOS (ns) 12 Ext. fMAXS (MHz) 31 Ordering Code ATV2500BQL-25DC ATV2500BQL-25JC ATV2500BQL-25KC ATV2500BQL-25PC 25 12 31 ATV2500BQL-25DI ATV2500BQL-25JI ATV2500BQL-25KI ATV2500BQL-25PI 30 15 26 ATV2500BQL-30DM ATV2500BQL-30KM ATV2500BQL-30LM 15 26 ATV2500BQL-30DM/883 ATV2500BQL-30KM/883 ATV2500BQL-30LM/883 15 10 52 5962 - 9154504MXX 5962 - 9154504MYX 20 11 40 5962 - 9154505MXX 5962 - 9154505MYX 25 12 31 5962 - 9154506MXX 5962 - 9154506MYX 5962 - 9154506MQA 30 15 26 5962 - 9154507MXX 5962 - 9154507MYX 5962 - 9154507MQA Package 40DW6 44J 44KW 40P6 40DW6 44J 44KW 40P6 40DW6 44KW 44LW 40DW6 44KW 44LW 44LW 44KW 44LW 44KW 44LW 44KW 40DW6 44LW 44KW 40DW6 Military/883C (-55°C to 125°C) Class B, Fully Compliant Military/883C (-55°C to 125°C) Class B, Fully Compliant Military/883C (-55°C to 125°C) Class B, Fully Compliant Military/883C (-55°C to 125°C) Class B, Fully Compliant Military/883C (-55°C to 125°C) Class B, Fully Compliant Military/883C (-55°C to 125°C) Industrial (-40°C to 85°C) Operation Range Commercial (0°C to 70°C) Package Type 40DW6 44J 44KW 40P6 44LW 40-Lead, 0.600" Wide, Ceramic, Dual Inline Package (Cerdip) 44-Lead, Plastic J-Leaded Chip Carrier OTP (PLCC) 44-Lead, Windowed, Ceramic J-Leaded Chip Carrier (JLCC) 40-Lead, 0.600" Wide, Plastic, Dual Inline Package OTP (PDIP) 44-Pad, Windowed, Ceramic Leadless Chip Carrier (LCC) 16 ATV2500B ATV2500B Packaging Information 40DW6, 40-Lead, 0.600” Wide, Windowed, Ceramic Dual Inline Package (Cerdip) Dimensions in Inches and (Millimeters) MIL-STD-1835 D-5 CONFIG A 44J, 44-Lead, Plastic J-Leaded Chip Carrier (PLCC) Dimensiosn in Inches and (Millimeters) JEDEC STANDARD MS-018 AC .045(1.14) X 45° PIN NO. 1 IDENTIFY .045(1.14) X 30° - 45° .012(.305) .008(.203) .656(16.7) SQ .650(16.5) .032(.813) .026(.660) .695(17.7) SQ .685(17.4) .630(16.0) .590(15.0) .021(.533) .013(.330) .050(1.27) TYP .500(12.7) REF SQ .043(1.09) .020(.508) .120(3.05) .090(2.29) .180(4.57) .165(4.19) .022(.559) X 45° MAX (3X) 44KW, 44-Lead, Windowed, Ceramic J-Leaded Chip Carrier (JLCC) Dimensions in Inches and (Millimeters) MIL-STD-1835 CJ1 40P6, 40-Lead, 0.600” Wide, Plastic Dual Inline Package (PDIP) Dimensions in Inches and (Millimeters) JEDED STANDARD MS-011 AC 2.07(52.6) 2.04(51.8) PIN 1 .035(.889) X 45° .045(1.14) X 45° .010(.254) .006(.152) .566(14.4) .530(13.5) .032(.813) .026(.660) .665(16.9) SQ .645(16.4) .695(17.7) SQ .685(17.4) .630(16.0) .590(15.0) .021(.533) .017(.432) 1.900(48.26) REF .220(5.59) MAX SEATING PLANE .161(4.09) .125(3.18) .110(2.79) .090(2.29) .065(1.65) .041(1.04) .630(16.0) .590(15.0) 0 REF 15 .690(17.5) .610(15.5) .090(2.29) MAX .005(.127) MIN .050(1.27) TYP .500(12.7) REF SQ .045(1.14) .035(.889) .120(3.05) .090(2.29) .180(4.57) .156(3.96) .065(1.65) .015(.381) .022(.559) .014(.356) .025(.635) RADIUS MAX (3X) .012(.305) .008(.203) 17 Packaging Information 44LW, 44-Pad, Windowed, Ceramic Leadless Chip Carrier (LCC) Dimensions in Inches and (Millimeters)* MIL-STD-1835 C-5 *Controlling dimension: millimeters 18 ATV2500B