ATV5000L-35KI

ATV5000/L Features • • • • • • • • • Advanced Programmable Logic Device - High Gate Utilization Flexible Interconnect Architecture - Universal Routing Flexible Logic Cells - 128 Flip-Flops and 52 Latches Multiple Flip-Flop Types - Synchronous or Asynchronous Registers High Speed - 50 MHz Operation Complete Third Party Software Support No Placement, Routing or Layout Software Required Proven and Reliable High Speed CMOS EPROM Process 2000 V ESD Protection 200 mA Latchup Immunity Reprogrammable - Tested 100% for Programmability Commercial, Industrial and Military Temperature Grades Block Diagram 52 INPUT LATCHES High Density UV Erasable Programmable Logic Device 8 INPUT PINS UNIVERSAL AND REGIONAL INTERCONNECT 52 LOGIC CELLS (104 FLIP-FLOPS) 52 I/O PINS 24 BURIED CELLS (24 FLIP-FLOPS) Description The Atmel V5000 is an easy to use, high density programmable logic device. Its simple, regular architecture translates into increased utilization and high performance. The ATV5000 has one programmable combinatorial logic array. This guarantees easy interconnection of and uniform performance from all nodes. "Sum terms", which are easy to use groupings of AND-OR gates, provide combinatorial logic blocks. Sum terms can be wireOR’d together to integrate larger logic blocks. To expand the levels of logic, buried sum terms feed back into the logic array. The 52 I/O pins can each be driven by a register or a sum term. Each I/O pin has an individually enabled input latch. All 128 registers are configurable as D- or T-types without using extra logic gates. Individual sum terms, asynchronous presets, resets and clocks give each flip-flop added flexibility. A direct "clock from pin" option guarantees synchronization and fast clock to output performance. Standard, off-the-shelf third-party software tools and programmers support the ATV5000. This minimizes start-up investment and improves product support. JLCC Chip Carrier Pin Configuration Pin Name IN Pins 2,32,36,66 Pins 1,34,35,68 I/O VCC Function Logic and Clock Inputs Input/Register Clocks 1-4 Input/Latch Clocks 1-4 Bidirectional Buffers +5 V Supply I/Os GND I/Os VCC 18 I/Os VCC I/Os IN 1 GND IN I/Os I/Os VCC 52 I/Os GND I/Os 35 I/Os IN GND IN VCC I/Os 0065B 1-193 Absolute Maximum Ratings* Temperature Under Bias.................-55oC to +125oC Storage Temperature......................-65oC to +150oC Voltage on Any Pin with Respect to Ground..........................-2.0 V to +7.0 V1 Voltage on Input Pins with Respect to Ground During Programming.....................-2.0 V to +14.0 V1 Programming Voltage with Respect to Ground........................-2.0 V to +14.0 V1 Integrated UV Erase Dose .............. 7258 W• sec/cm2 *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: 1. Minimum voltage is -0.6 V dc which may undershoot to -2.0 V for pulses of less than 20 ns. Maximum output pin voltage is VCC+0.75 V dc which may overshoot to +7.0 V for pulses of less than 20 ns. Functional Logic Diagram Description There are 52 identical input/ouput logic cells and 24 identical buried logic cells in the ATV5000. Each I/O cell has two flipflops, up to three sum terms, individual clock, reset, and preset terms per flip-flop, and one output enable term. Independent of output configuration, all flip-flops are always usable, and have at least four product term inputs each. Each I/O pin (52 total) signal or its latched version drives the logic array. There is one latch clock per quadrant. The ATV5000 has four identical quadrants (see Figure 2). The universal bus routes true and false signals from each of the 52 I/O pins to all four quadrants. Regional buses route each quadrant’s flip-flop Q and Q locally. The eight input-only pins are available in all four regional buses. Each logic cell has a number of "regional" and "universal" product terms (see Figure 1). The I/O logic cells contain three sum terms, two flip-flops, and an I/O buffer. The buried logic cells each contain one flip-flop. In addition, in each buried logic cell the sum term can drive the regional bus. This allows for logic expansion. Serial register preload and observability simplify testing. All registers automatically clear at power up. Quadrant Functional Logic Diagram ATV5000 UNIVERSAL INPUTS UNIVERSAL PRODUCT TERMS REGIONAL PRODUCT TERMS REGIONAL INPUTS REGISTERCLOCKS INPUT PINS REGISTERCLOCKS UNIVERSAL PRODUCT TERMS REGIONAL PRODUCT TERMS REGIONAL INPUTS UNIVERSAL BUS TO ALL QUADRANTS BURIED LOGIC CELLS (6 TOTAL PERQUADRANT) INPUT/OUTPUT LOGIC CELLS (13 TOTAL PERQUADRANT) I/O PINS REGIONAL BUS Figure 1 D.C. and A.C. Operating Range ATV5000-25 Operating Temperature (Case) VCC Power Supply Commercial 0 C - 70 C 5 V ± 5% o o ATV5000/L-30 Industrial 0 C - 70 C 5 V ± 10% o o ATV5000/L-35 Military -55 C - 125oC 5 V ± 10% o 1-194 ATV5000/L ATV5000/L ATV5000 Block Diagram REGISTER CLOCK PIN 2 LATCH CLOCK PIN 1 13 I/O PINS 4-15,17 QUADRANT 1 13 I/O CELLS REGIONAL BUS REGIONAL BUS QUADRANT 4 13 I/O CELLS REGISTER CLOCK PIN 66 LATCH CLOCK PIN 68 13 I/O PINS 52,53,55-65 REGISTER CLOCK PIN 32 LATCH CLOCK PIN 34 13 I/O PINS 18,19,21-31 6 BURIED LOGIC CELLS 16 UNIVERSAL BUS 6 BURIED LOGIC CELLS 16 REGISTER CLOCK PIN 36 LATCH CLOCK PIN 35 13 I/O CELLS 13 I/O CELLS 13 I/O PINS 38-49,51 6 BURIED LOGIC CELLS QUADRANT 2 16 16 6 BURIED LOGIC CELLS QUADRANT 3 REGIONAL BUS INPUT PINS 1,2,32,34,35, 36,66,68 REGIONAL BUS Figure 2 Quadrant Logic Diagram and Description The ATV5000 has: four identical quadrants, 52 identical input/ output logic cells, and 24 identical buried logic cells. The universal bus routes true and false signals from each of the 52 I/O pins to all four quadrants. Regional buses route each quadrant’s flip-flop Q and Q locally. The eight input-only pins are available in every regional bus. Each logic cell has a number of "regional" and "universal" product terms (see Figure 3). The I/O logic cells (Figures 7, 8, 9) contain three sum terms, two flip-flops, and an I/O buffer. Sum term B has five product terms - two universal and three regional. Sum terms A and C each have four product terms - one universal and three regional. Flip-flop Q1 has global asynchronous preset, reset, and clock product terms. Flip-flop Q2 has universal asynchronous reset and clock terms and a regional asynchronous preset term. There is one universal product term for the I/O pin output enable. The buried logic cells (Figure 4) each contain one flip-flop. The sum term has one universal product term and four regional product terms for a total of five. The flip-flop has universal asynchronous preset, reset, and clock terms. In addition, in each buried logic cell the sum term can be fed back into the regional bus instead of the flip-flop. This allows for logic expansion. Regional product terms have as inputs all quadrant flip-flop outputs (or buried flip-flop inputs) and the eight dedicated input pins. Universal product terms have the same inputs plus the 52 I/O pins and their complements. Quadrant Clock Pin Assignments Quadrant Number 1 2 3 4 Register Clock Pin 2 32 36 66 Latch Clock Pin 1 34 35 68 Quadrant Structure UNIVERSAL PRODUCT TERMS REGIONAL PRODUCT TERMS UNIVERSAL BUS INPUTS REGIONAL BUS INPUTS IN/LIN Q1 Q2 REGISTER CLOCK LATCH CLOCK INPUT/ OUTPUT LOGIC CELLS (13 TOTAL) 13 I/O PINS OE Q1/D1 BURIED LOGIC CELLS (6 TOTAL) REGISTER CLOCK UNIVERSAL BUS TO ALL QUADRANTS 16 REGIONAL BUS ALL 8 INPUT ONLY PINS Figure 3 1-195 Logic Cell Options The ATV5000 logic cells contain most of the chip’s logic options. The standard logic cell contains two flip-flops, three sum terms and three array inputs. The three sum terms can be combined to provide sum term options of four, five, nine, or 13 product terms. A combinatorial signal or the output of Q1 can be sent to the I/O cell. The ATV5000 retains the ATV2500’s ability to bury both registers in the I/O cell and still output a combinatorial signal (see Figure 8). A new feature, unique to the ATV5000, is the ability to output Q1 and feedback the combinatorial term directly (see Figure 7). This high speed logic expansion term increases the devices flexibility and gate utilization. Logic Cell with Buried Sum Term and Register to I/O Cell U U R R R R R U R U R U R R A R U U U R U R C D2/T2 Q2 CK1 AR1 AP2 CLOCK OPTION D1/T1 Q1 TO I/O CELL AP1 B Q1 Q2 Buried Logic Cells Each quadrant has six buried logic cells (see Figure 4). Each cell contains one sum term with five product terms, a flip-flop, and individual preset, clear, and clock terms. A configuration bit selects either the Q output or the D input for feedback into the regional bus. Buried Logic Cells R R SELECT U R R R R U U U CK1 AR1 CLOCK OPTION D1/T1 Q1 AP1 R R U U CK2 AR2 CLOCK OPTION Figure 7 Flip-Flop Clock Options Each register may be connected to its regional clock to provide fast clock-to-output timing (see Figure 5). In this "synchronous" mode, the clock is one of four input pins, a unique clock pin for each chip quadrant. One product term defines each flip-flop’s clock in the "asynchronous" mode. In the "synchronous" mode, the regional clock is ANDed with the product term. This provides the fast timing of a synchronous clock with the local control of the product term. Figure 4 Clock Option RCKn TO LOGIC CELL SELECT CLOCK PRODUCT TERM Figure 5 I/O Pin Logic TO LOGIC CELL Q D C I/O Pin Latches Each I/O pin of the ATV5000 has an input latch which can be individually enabled or disabled (see Figure 6). Each chip quadrant has a unique latch clock. When the latch is inactive, pin input flows directly into the array. When activated, the latch is flow-through when the clock signal is low, and data is captured on the clock’s rising edge. SELECT LCKn FROM LOGIC CELL U 0/1 I/O OE Flip-Flop Types Each flip-flop in the ATV5000 may be configured as either a Tor D-type flip-flop. A T-type flip-flop can also easily be configured into a JK or SR flip-flop. Figure 6 1-196 ATV5000/L ATV5000/L Logic Cell, Two Buried Registers, Combinatorial to I/O Cell U U R R R R U R R A R U U U R U R U R R U R C R R U U CK2 AR2 CLOCK OPTION D2/T2 Q2 AP2 B TO I/O CELL CK1 AR1 CLOCK OPTION D1/T1 Q1 AP1 Q1 Q2 FROM I/O CELL Logic Cell with Combinable Sum Terms, Register to I/O Cell U U R R R R U R R A R U U U R U R U R R U R C R R U U CK2 AR2 CLOCK OPTION D2/T2 Q2 AP2 B TO D1/T1 CK1 AR1 CLOCK OPTION D1/T1 Q1 TO I/O CELL AP1 Q1 Q2 FROM I/O CELL Figure 8 Figure 9 D.C. Characteristics Symbol Parameter ILI ILO ICC Input Load Current Output Leakage Current Power Supply Current ATV5000 Power Supply Current ATV5000L Clocked Power Supply Current, ATV5000L Only Output Short Circuit Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage VIN = VIH or VIL, IOL = 8 mA Com,Ind; 6 mA Mil. IOH = -100 µA IOH = -4.0 mA VCC-0.3 2.4 Condition VIN = -0.1 V to VCC+1 V VOUT = -0.1 V to VCC+0.1 V VCC = MAX, VIN = GND or VCC Outputs Open VCC = MAX, VIN = GND or VCC Outputs Open f = 1 MHz, VCC = MAX Outputs Open VOUT = 0.5 V -0.6 2.0 Com. Ind.,Mil. Com. Ind.,Mil. Com. Ind.,Mil. 200 200 32 32 30 (2) Min Typ Max 10 10 350 400 40 50 Units µA µA mA mA mA mA mA mA ICC ICC2 IOS (1) VIL VIH VOL VOH 30 (2) -120 0.8 VCC+0.75 0.5 mA V V V V V Notes: 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 seconds. 2. See ICC vs. Frequency curve. 1-197 A.C. Waveforms Input Pin Clock INPUTS AND I/O PINS (1) A.C. Waveforms Product Term Clock INPUTS AND I/O PINS tHS tWS tPS (1) tSIS REGISTER CLOCK PIN tWS tSIA REGISTER CLOCK TERM ASYNCHRONOUS RESET/PRESET tWA tHA tWA tPA tARS ASYNCHRONOUS RESET/PRESET tCOS REGISTERED OUTPUTS tSFS INTERNAL FEEDBACKS tCFS VALID OUTPUT VALID tAW tAP OUTPUT VALID tAPF VALID tARA tAW tCOA tAP OUTPUT VALID tSFA tCFA VALID OUTPUT VALID tAPF VALID REGISTERED OUTPUTS INTERNAL FEEDBACKS Notes: 1. Timing measurement reference is 1.5 V. Input AC driving levels are 0.0 V and 3.0 V, unless otherwise specified. Register A.C. Characteristics, Input Pin Clock ATV5000-25 Symbol Parameter tCOS tCFS tSIS tSFS tHS tWS tPS FMAXS tARS Note: Min Max ATV5000/L-30 Min Max ATV5000/L-35 Min Max Units ns ns ns ns ns ns ns Clock to Output Clock to Feedback Input Setup Time (1) 15 0 16 11 0 10 20 50 20 25 9 0 17 13 0 12 25 20 12 0 20 15 0 15 30 40 30 25 15 Feedback Setup Time(1) Hold Time Clock Width Clock Period Maximum Frequency (1/tPS) Asynchronous Reset/Preset Recovery Time 1. Add 3 ns for Universal Product Terms. 33 MHz ns Register A.C. Characteristics, Product Term Clock ATV5000-25 Symbol tCOA tCFA tSIA tSFA tHA tWA tPA FMAXA tARA Note: ATV5000/L-30 Min Max ATV5000/L-35 Min Max Parameter Clock to Output Clock to Feedback Input Setup Time (1) (1) Min Max Units ns ns ns ns ns ns ns 25 7 10 5 8 12 25 40 15 20 20 10 12 8 10 15 33 30 25 12 15 13 12 15 40 30 25 35 27 Feedback Setup Time Hold Time Clock Width Clock Period Maximum Frequency (1/tPA) Asynchronous Reset/Preset Recovery Time 25 MHz ns 1. Add 3 ns for Universal Product Terms. 1-198 ATV5000/L ATV5000/L A.C. Waveforms (1) INPUTS AND I/O PINS tS INPUT LATCH CLOCK tH tW tP tER1 COMBINATORIAL OUTPUTS tPD1 REGISTERED tPD3 INTERNAL FEEDBACKS tPD2 VALID tPD4 tER2 VALID HIGH Z OUTPUT VALID OUTPUT VALID OUTPUT VALID tEA1 HIGH Z OUTPUT VALID tW tEA2 Notes: 1. Timing measurement reference is 1.5 V. Input AC driving levels are 0.0 V and 3.0 V, unless otherwise specified. A.C. Characteristics ATV5000-25 Symbol tPD1 tPD2 tPD3 tPD4 tEA1 tER1 tEA2 tER2 tS tH tW tP FMAX tAW tAP tAPF Note: ATV5000/L-30 Min Max ATV5000/L-35 Min Max Parameter Input to Non-Registered Output (1) (1) Min Max Units ns ns ns ns ns ns ns ns ns ns ns ns 25 20 20 15 30 30 25 25 5 5 10 20 50 15 30 25 20 6 5 12 25 (1) 30 25 25 18 35 35 30 30 7 5 12 30 40 20 35 30 35 30 30 22 40 40 35 35 Feedback to Non-Registered Output Input to Non-Registered Feedback Feedback to Non-Registered Feedback(1) Input to Output Enable Input to Output Disable Feedback to Output Enable Feedback to Output Disable Input Latch Setup Time Input Latch Hold Time Clock Width Clock Period Maximum Frequency (1/tP) Asynchronous Reset/Preset Width Asynchronous Reset/ Preset to Registered Output Asynchronous Reset/ Preset to Registered Feedback 1. Add 3 ns for Universal Product Terms. 33 MHz ns 40 35 ns ns Input Test Waveforms and Measurement Levels 3.0V AC DRIVING LEVELS 0.0V 1.5V AC MEASUREMENT LEVEL Output Test Load 5.0V R1= 450 (580 MIL.) R2= 250 (280 MIL.) OUTPUT PIN CL= 35pF tR, tF < 5 ns (10% to 90%) 1-199 Preload and Observability of Registers The ATV5000’s registers include circuity to load and unload them serially. This feature simplifies testing. Any state can be forced into the registers to control test sequencing, and all registers may be observed, independent of being buried. A VIH level on the Data In pin will force the appropriate register high; a VIL will force it low, independent of the polarity or other configuration bit settings. The preload/observe state is entered by placing an 11-V to 14-V signal on pin 68 on the JLCC. When the clock (pin 1) is pulsed high, data (pin 2) is clocked serially through all registers in the device, as in the following table. All register contents are also clocked out of the device on Pin 65 in FIFO fashion. If observability only is required, data out should be connected back to data in. If preload only is required, OE (pin 66) can be held high and data out (pin 65) will remain high impedance. Any user contemplating the use of register preload/obervability is encouraged to contact Atmel’s PLD applications department. Note: All register clock terms or pins must be low prior to entering the preload/observe state, and low prior to leaving the preload/observe state. Pin 1 must be low prior to entering the preload/observe state. tD VH PRELOAD tSP CLOCK tHP Clock #1 Pin 65 New Q1 tWPP tWPP tD tPR Clock #2 Pin 65 New Q2 Clock #128 DATA IN tERP OE tEAP DATA OUT Pin 65 Q1 Pin 65 Q2 Pin 4 Q2 Pin 65 Q1 tCOP tDMIN = 100 ns tSPMIN = 50 ns tHPMIN = 50 ns tWPPMIN = 100 ns tPRMIN = 1000 ns tERPMAX = 100 ns tEAPMAX = 100 ns tCOPMAX = 100 ns Preload / Observe Register Scan Order Quadrant Quadrant 1 Pin Pin DIN Q2 18 Q2 Pin Q2 Pin Q2 52 Q1 Q2 38 Q1 B11 53 Q1 B5 Q2 Q2 Q1 Q2 4 Q1 B23 19 Q1 39 Q1 Q2 55 Q1 Q2 B17 Q2 40 Q1 Q2 5 Q1 Q2 21 Q1 Q2 ••• ••• 56 Q1 B6 Q2 ••• ••• B0 Q2 6 Q1 ••• ••• 22 Q1 B18 Q2 ••• ••• 49 Q1 Q2 65 Q1 DOUT B12 Q2 51 Q1 (Quadrant 4) 15 Q1 Q2 31 Q1 (Quadrant 3) 17 Q1 (Quadrant 2) Quadrant 2 (Quadrant 1)→ Quadrant 3 (Quadrant 2)→ Quadrant 4 (Quadrant 3)→ Pin 1-200 ATV5000/L ATV5000/L Power Up Reset The registers in the ATV5000 are designed to reset during power up. At a point delayed slightly from VCC crossing 3.8 V, all registers will be reset to the low state. The output state will depend on the polarity of the output buffer. This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the uncertainty of how VCC actually rises in the system, the following conditions are required: 1) The VCC rise must be monotonic, 2) After reset occurs, all input and feedback setup times must be met before driving the clock term high, and 3) The signals from which the clock is derived must remain stable during tPR. Parameter tPR Description Power-Up Reset Time Min Typ 600 Max Units 1000 ns Design Flow Diagram PA R T I T I O N D E S I G N I N TO M A N A G A B L E P I E C E S Using The ATV5000 The ATV5000’s simple, regular architecture means that only simple logic compilers are required to configure the device. No layout or route and place are required. These software tools are readily available from companies such as Data I/O Corporation (ABEL™ ), Logical Devices (CUPL™ ), MINC Inc. (PLDesigner-XL™ ), and ISDATA (LOGiC™ ). The first step in designing a device as complex as the ATV5000 is to partition your design into manageable blocks. These blocks are then allocated proportionally to each of the four quadrants of the ATV5000. Random gates can be described either with boolean equations (a behavioral description) or with a schematic editor. Truth table logic and state machines are best described behaviorially and entered with a text editor. The design is then combined into one ASCII file, which is then submitted to the logic compiler. Compilation, logic reduction, simulation, JEDEC file creation and documentation are then completed by all of the popular compilers. Assignment of signals to pins or buried nodes as well as selecting the various options of the ATV5000 (such as register clocks and input latches) can be done manually in the design data base file, or an automatic fitter may be used. A logic fitter assigns pins and nodes to make best use of the features in the ATV5000, and frees the designer from being required to learn all of the features of a complex device such as the ATV5000. For further information on fitters for the ATV5000, contact Atmel’s PLD applications department. After correcting any syntax and logic errors discovered by the compiler, the JEDEC file is ready to download to an PLD programmer. These are available from a number of manufacturers. Programmed devices are usually first tested in the programmer with your supplied test vectors. The next step is check out your "custom chip" in the target system. When this hardware debug step is complete, your system is ready to go— all in a matter of hours. ABEL™ , CUPL™ , PLDesigner-XL™ and LOGiC™ may be trademarks of others. RANDOM G AT E S S TAT E MACHINES TRUTH TA B L E S S C H E M AT I C E D I TO R TEXT E D I TO R D E S I G N D ATA B A S E (ASCII FILE) C O M P I L E A N D S I M U L AT E ER R O R S? ER R O R S? TRANSFER JEDEC FILE AND PROGRAM H A R D WA R E T E S T ER R O R S? C O R R EC T ER R O R S? SHIP IT! 1-201 ATV5000 PLCC/PGA Pin Assignments PLCC Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PGA Pin B6 A6 B5 A5 B4 A4 B3 A3 A2 B2 B1 C2 C1 D2 D1 E2 E1 Name IN IN VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O PLCC Pin 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 PGA Pin F2 F1 G2 G1 H2 H1 J2 J1 K1 K2 L2 K3 L3 K4 L4 K5 L5 Name I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O IN GND IN PLCC Pin 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 PGA Pin K6 L6 K7 L7 K8 L8 K9 L9 L10 K10 K11 J10 J11 H10 H11 G10 G11 Name IN IN VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND I/O PLCC Pin 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 PGA Pin F10 F11 E10 E11 D10 D11 C10 C11 B11 B10 A10 B9 A9 B8 A8 B7 A7 Name I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O IN GND IN Pin Capacitance (f = 1 MHz, T = 25°C) (1) Typ CIN COUT Note: Max 8 12 Units pF pF Conditions VIN = 0 V VOUT = 0 V 6 8 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. Security Fuse Usage A single fuse is provided to prevent unauthorized copying of the ATV5000 fuse patterns. Once programmed, all outputs appear programmed during verify. The security fuse should be programmed last (after verifying all other programmed bits), as its effect is immediate. The security fuse also inhibits preload and observability. Erasure Characteristics The entire memory array of an ATV5000 is erased after exposure to ultraviolet light at a wavelength of 2537 Å. Complete erasure is assured after a minimum of 20 minutes exposure using 12,000 µW/cm2 intensity lamps spaced one inch away from the chip. Minimum erase time for lamps at other intensity ratings can be calculated from the minimum integrated erasure dose of 15 W• sec/cm2. To prevent unintentional erasure, an opaque label is recommended to cover the clear window on any UV erasable PLD which will be subjected to continuous fluorescent indoor lighting or sunlight. 1-202 ATV5000/L ATV5000/L SUPPLY CURRENT vs. INPUT FREQUENCY S U P P L Y C U R R E N T m A ATV5000 (TA = 25C, VCC = 5V) 200 150 100 50 0 0 3 6 9 12 15 18 21 INPUT FREQUENCY (MHz) SUPPLY CURRENT vs. INPUT FREQUENCY S U P P L Y C U R R E N T m A ATV5000L (TA = 25C, VCC = 5V) 200 150 100 50 0 0 3 6 9 12 15 18 21 INPUT FREQUENCY (MHz) 1-203 Ordering Information tPD (ns) 25 tCOS (ns) 15 fMAX (MHz) 50 Ordering Code ATV5000-25JC ATV5000-25KC ATV5000-25UC ATV5000-30JC ATV5000-30KC ATV5000-30UC ATV5000-30KI ATV5000-30UI ATV5000-30KM ATV5000-30UM ATV5000-30KM/883 ATV5000-30UM/883 35 25 33 ATV5000-35JC ATV5000-35KC ATV5000-35UC ATV5000-35KI ATV5000-35UI ATV5000-35KM ATV5000-35UM ATV5000-35KM/883 ATV5000-35UM/883 35 25 33 ATV5962-93248 02M XX ATV5962-93248 02M YX Package 68J 68KW 68UW 68J 68KW 68UW 68KW 68UW 68KW 68UW 68KW 68UW 68J 68KW 68UW 68KW 68UW 68KW 68UW 68KW 68UW 68KW 68UW Operation Range Commercial (0°C to 70°C) Commercial (0°C to 70°C) Industrial (-40°C to 85°C) Military (-55°C to 125°C) Military/883C Class B, Fully Compliant (-55°C to 125°C) Commercial (0°C to 70°C) Industrial (-40°C to 85°C) Military (-55°C to 125°C) Military/883C Class B, Fully Compliant (-55°C to 125°C) Military/883C Class B, Fully Compliant (-55°C to 125°C) 30 20 40 tPD (ns) 30 tCOS (ns) 20 fMAX (MHz) 40 Ordering Code ATV5000L-30JC ATV5000L-30KC ATV5000L-30UC ATV5000L-35JC ATV5000L-35KC ATV5000L-35UC ATV5000L-35KI ATV5000L-35UI ATV5000L-35KM ATV5000L-35UM ATV5000L-35KM/883 ATV5000L-35UM/883 Package 68J 68KW 68UW 68J 68KW 68UW 68KW 68UW 68KW 68UW 68KW 68UW 68KW 68UK Operation Range Commercial (0°C to 70°C) Commercial (0°C to 70°C) Industrial (-40°C to 85°C) Military (-55°C to 125°C) Military/883C Class B, Fully Compliant (-55°C to 125°C) Military/883C Class B, Fully Compliant (-55°C to 125°C) 35 25 33 35 25 33 ATV5962-93248 03M XX ATV5962-93248 08M YX 1-204 ATV5000/L ATV5000/L Ordering Information Package Type 68J 68KW 68UW 68 Lead, Plastic J-Leaded Chip Carrier OTP (PLCC) 68 Lead, Windowed, Ceramic J-Leaded Chip Carrier (JLCC) 68 Pin, Windowed, Ceramic Pin Grid Array (PGA) 1-205