ATXMEGA384A1-CU

Features • High-performance, Low-power 8/16-bit Atmel® AVR® XMEGATM Microcontroller • Non-Volatile Program and Data Memories 64K - 384K Bytes of In-System Self-Programmable Flash 4K - 8K Bytes Boot Section with Independent Lock Bits 2 KB - 4 KB EEPROM 4 KB - 32 KB Internal SRAM External Bus Interface for up to 16M bytes SRAM External Bus Interface for up to 128M bit SDRAM Peripheral Features – Four-channel DMA Controller with support for external requests – Eight-channel Event System – Eight 16-bit Timer/Counters Four Timer/Counters with 4 Output Compare or Input Capture channels Four Timer/Counters with 2 Output Compare or Input Capture channels High-Resolution Extension on all Timer/Counters Advanced Waveform Extension on two Timer/Counters – Eight USARTs IrDA modulation/demodulation for one USART – Four Two-Wire Interfaces with dual address match (I2C and SMBus compatible) – Four SPI (Serial Peripheral Interface) peripherals – AES and DES Crypto Engine – 16-bit Real Time Counter with separate Oscillator – Two Eight-channel, 12-bit, 2 Msps Analog to Digital Converters – Two Two-channel, 12-bit, 1 Msps Digital to Analog Converters – Four Analog Comparators with Window compare function – External Interrupts on all General Purpose I/O pins – Programmable Watchdog Timer with Separate On-chip Ultra Low Power Oscillator Special Microcontroller Features – Power-on Reset and Programmable Brown-out Detection – Internal and External Clock Options with PLL and Prescaler – Programmable Multi-level Interrupt Controller – Sleep Modes: Idle, Power-down, Standby, Power-save, Extended Standby – Advanced Programming, Test and Debugging Interfaces JTAG (IEEE 1149.1 Compliant) Interface for programming, test and debugging PDI (Program and Debug Interface) for programming and debugging I/O and Packages – 78 Programmable I/O Lines – 100 - lead TQFP – 100 - ball CBGA – 100 - ball VFBGA Operating Voltage – 1.6 – 3.6V Speed performance – 0 – 12 MHz @ 1.6 – 3.6V – 0 – 32 MHz @ 2.7 – 3.6V – – – – • 8/16-bit XMEGA A1 Microcontroller ATxmega384A1 ATxmega256A1 ATxmega192A1 ATxmega128A1 ATxmega64A1 Preliminary • • • • Typical Applications • • • • • Industrial control Factory automation Building control Board control White Goods • • • • • Climate control ZigBee Motor control Networking Optical • • • • • Hand-held battery applications Power tools HVAC Metering Medical Applications 8067L–AVR–08/10 XMEGA A1 ‘ 1. Ordering Information Ordering Code ATxmega384A1-AU ATxmega256A1-AU ATxmega192A1-AU ATxmega128A1-AU ATxmega64A1-AU ATxmega384A1-CU ATxmega256A1-CU ATxmega192A1-CU ATxmega128A1-CU ATxmega64A1-CU ATxmega128A1-C7U ATxmega64A1-C7U Notes: 1. 2. 3. Flash (B) 384K + 8K 256K + 8K 192K + 8K 128K + 8K 64K + 4K 384K + 8K 256K + 8K 192K + 8K 128K + 8K 64K + 4K 128K + 8K 64K + 4K E2 4 KB 4 KB 2 KB 2 KB 2 KB 4 KB 4 KB 2 KB 2 KB 2 KB 2 KB 2 KB SRAM 32 KB 16 KB 16 KB 8 KB 4 KB 32 KB 16 KB 16 KB 8 KB 4 KB 8 KB 4 KB Speed (MHz) 32 32 32 32 32 32 32 32 32 32 32 32 Power Supply 1.6 - 3.6V 1.6 - 3.6V 1.6 - 3.6V 1.6 - 3.6V 1.6 - 3.6V 1.6 - 3.6V 1.6 - 3.6V 1.6 - 3.6V 1.6 - 3.6V 1.6 - 3.6V 1.6 - 3.6V 1.6 - 3.6V Package(1)(2)(3) Temp 100A -40°C - 85°C 100C1 100C2 This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. For packaging information, see “Packaging information” on page 64. Package Type 100A 100C1 100C2 100-lead, 14 x 14 x 1.0 mm, 0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) 100-ball, 9 x 9 x 1.2 mm Body, Ball Pitch 0.88 mm, Chip Ball Grid Array (CBGA) 100-ball, 7 x 7 x 1.0 mm Body, Ball Pitch 0.65 mm, Very Thin Fine-Pitch Ball Grid Array (VFBGA) 2 8067L–AVR–08/10 XMEGA A1 2. Pinout/Block Diagram Figure 2-1. Block diagram and pinout INDEX CORNER PA6 PA7 GND AVCC PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 GND VCC PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 GND VCC PD0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PA5 PA4 PA3 PA2 PA1 PA0 AVCC GND PR1 PR0 RESET/PDI PDI PQ3 PQ2 PQ1 PQ0 GND VCC PK7 PK6 PK5 PK4 PK3 PK2 PK1 Port R Port Q DATA BU S ADC A Port A DAC A AC A0 AC A1 ADC B OSC/CLK Contro l BOD TEMP VREF RTC FLASH POR OCD Port K Power Contro l CPU Reset Contro l DMA RAM E 2 PROM Port B DAC B AC B0 Port J Interrupt Controlle r Watchdog Event System ctrl DATA BU S EVENT ROUTING NETWORK USART0/1 USART0:1 USART0:1 USART0:1 T/C0:1 T/C0:1 T/C0:1 T/C0:1 AC B1 Port H Port C Port D Port E Port F PK0 VCC GND PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 VCC GND PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 VCC GND PF7 PF6 TWI TWI TWI TWI SPI SPI SPI Notes: 1. For full details on pinout and pin functions refer to “Pinout and Pin Functions” on page 49. 2. VCC/GND on pin 83/84 are swapped compared to other VCC/GND to allow easier routing of GND to 32 kHz crystal. PD1 PD2 PD3 PD4 PD5 PD6 PD7 GND VCC PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 GND VCC PF0 PF1 PF2 PF3 PF4 PF5 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 SPI External Bus Interface 3 8067L–AVR–08/10 XMEGA A1 Figure 2-2. CBGA-pinout Top view 1 A B C D E F G H J K 2 3 4 5 6 7 8 9 10 10 9 8 Bottom view 7 6 5 4 3 2 1 A B C D E F G H J K Table 2-1. 1 A B C D E F G H J K CBGA-pinout 2 VCC PK2 PK5 PK6 PQ1 PR0 PA1 PA2 PA3 PA7 3 GND PK1 PK4 PK7 PQ2 RESET/ PDI PA4 PA5 PB0 GND 4 PJ3 PJ4 PJ5 PJ6 PJ7 PDI PB3 PB2 PB1 AVCC 5 VCC PH7 PJ0 PJ1 PJ2 PQ3 PB4 PB5 PB6 PB7 6 GND PH4 PH5 PH6 PE7 PC2 PC1 PC0 PC3 VCC 7 PH1 PH2 PH3 PF0 PE6 PE2 PC6 PC5 PC4 GND 8 GND PH0 PF2 PF1 PE5 PE1 PD7 PD5 PC7 VCC 9 VCC PF6 PF3 PF4 PE4 PE0 PD6 PD4 PD2 GND 10 PF7 PF5 VCC GND PE3 VCC GND PD3 PD1 PD0 PK0 PK3 VCC GND PQ0 PR1 GND AVCC PA0 PA6 4 8067L–AVR–08/10 XMEGA A1 3. Overview The Atmel® AVR® XMEGA™ A1 is a family of low power, high performance and peripheral rich CMOS 8/16-bit microcontrollers based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the XMEGA A1 achieves throughputs approaching 1 Million Instructions Per Second (MIPS) per MHz allowing the system designer to optimize power consumption versus processing speed. The AVR CPU combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction, executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs many times faster than conventional single-accumulator or CISC based microcontrollers. The XMEGA A1 devices provides the following features: In-System Programmable Flash with Read-While-Write capabilities, Internal EEPROM and SRAM, four-channel DMA Controller, eight-channel Event System, Programmable Multi-level Interrupt Controller, 78 general purpose I/O lines, 16-bit Real Time Counter (RTC), eight flexible 16-bit Timer/Counters with compare modes and PWM, eight USARTs, four Two Wire Serial Interfaces (TWIs), four Serial Peripheral Interfaces (SPIs), AES and DES crypto engine, two 8-channel, 12-bit ADCs with optional differential input with programmable gain, two 2-channel, 12-bit DACs, four analog comparators with window mode, programmable Watchdog Timer with seperate Internal Oscillator, accurate internal oscillators with PLL and prescaler and programmable Brown-Out Detection. The Program and Debug Interface (PDI), a fast 2-pin interface for programming and debugging, is available. The devices also have an IEEE std. 1149.1 compliant JTAG test interface, and this can also be used for On-chip Debug and programming. The XMEGA A1 devices have five software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, DMA Controller, Event System, Interrupt Controller and all peripherals to continue functioning. The Power-down mode saves the SRAM and register contents but stops the oscillators, disabling all other functions until the next TWI or pin-change interrupt, or Reset. In Power-save mode, the asynchronous Real Time Counter continues to run, allowing the application to maintain a timer base while the rest of the device is sleeping. In Standby mode, the Crystal/Resonator Oscillator is kept running while the rest of the device is sleeping. This allows very fast start-up from external crystal combined with low power consumption. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run. To further reduce power consumption, the peripheral clock to each individual peripheral can optionally be stopped in Active mode and Idle sleep mode. The device is manufactured using Atmel's high-density nonvolatile memory technology. The program Flash memory can be reprogrammed in-system through the PDI or JTAG. A Bootloader running in the device can use any interface to download the application program to the Flash memory. The Bootloader software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8/16-bit RISC CPU with In-System Self-Programmable Flash, the Atmel XMEGA A1 is a powerful microcontroller family that provides a highly flexible and cost effective solution for many embedded applications. The XMEGA A1 devices are supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, programmers, and evaluation kits. 5 8067L–AVR–08/10 XMEGA A1 3.1 Block Diagram XMEGA A1 Block Diagram PR[0..1] XTAL1 XTAL2 PQ[0..3] TOSC1 TOSC2 Figure 3-1. PORT Q (4) PORT R (2) EVENT ROUTING NETWORK Oscillator Circuits/ Clock Generation Watchdog Oscillator Real Time Counter Watchdog Timer DACA PA[0..7] PORT A (8) ACA ADCA AREFA VCC/10 Int. Ref. Tempref AREFB AES ADCB ACB DES DMA Controller DATA BUS Event System Controller SRAM Oscillator Control Sleep Controller Power Supervision POR/BOD & RESET VCC GND RESET/ PDI_CLK PDI_DATA PDI BUS Controller Prog/Debug Controller JTAG OCD CPU Interrupt Controller PORT K (8) PORT J (8) NVM Controller PB[0..7]/ JTAG PORT B (8) Flash DACB EEPROM EBI PORT H (8) PORT B PK[0..7] PJ[0..7] PH[0..7] IRCOM DATA BUS EVENT ROUTING NETWORK USARTC0:1 USARTD0:1 USARTE0:1 USARTF0:1 TCC0:1 TCD0:1 TCE0:1 TCF0:1 TWIC TWID TWIE PORT C (8) PORT D (8) PORT E (8) PORT F (8) PC[0..7] PD[0..7] PE[0..7] PF[0..7] TWIF SPIC SPID SPIE SPIF 6 8067L–AVR–08/10 XMEGA A1 4. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 4.1 Recommended reading • XMEGA A Manual • XMEGA A Application Notes This device data sheet only contains part specific information and a short description of each peripheral and module. The XMEGA A Manual describes the modules and peripherals in depth. The XMEGA A application notes contain example code and show applied use of the modules and peripherals. The XMEGA A Manual and Application Notes are available from http://www.atmel.com/avr. 5. Disclaimer For devices that are not available yet, typical values contained in this datasheet are based on simulations and characterization of other AVR XMEGA microcontrollers manufactured on the same process technology. Min. and Max values will be available after the device is characterized. 7 8067L–AVR–08/10 XMEGA A1 6. AVR CPU 6.1 Features • 8/16-bit high performance AVR RISC Architecture – 138 instructions – Hardware multiplier 32x8-bit registers directly connected to the ALU Stack in SRAM Stack Pointer accessible in I/O memory space Direct addressing of up to 16M Bytes of program and data memory True 16/24-bit access to 16/24-bit I/O registers Support for 8-, 16- and 32-bit Arithmetic Configuration Change Protection of system critical features • • • • • • • 6.2 Overview The XMEGA A1 uses the 8/16-bit AVR CPU. The main function of the CPU is program execution. The CPU must therefore be able to access memories, perform calculations and control peripherals. Interrupt handling is described in a separate section. Figure 6-1 on page 8 shows the CPU block diagram. Figure 6-1. CPU block diagram DATA BUS Program Counter Flash Program Memory 32 x 8 General Purpose Registers OCD Instruction Register STATUS/ CONTROL Instruction Decode ALU Multiplier/ DES DATA BUS Peripheral Module 1 Peripheral Module 2 SRAM EEPROM PMIC The AVR uses a Harvard architecture - with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipeline. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This 8 8067L–AVR–08/10 XMEGA A1 concept enables instructions to be executed in every clock cycle. The program memory is InSystem Self-Programmable Flash memory. 6.3 Register File The fast-access Register File contains 32 x 8-bit general purpose working registers with single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU cycle, the operation is performed on two Register File operands, and the result is stored back in the Register File. Six of the 32 registers can be used as three 16-bit address register pointers for data space addressing - enabling efficient address calculations. One of these address pointers can also be used as an address pointer for look up tables in Flash program memory. 6.4 ALU - Arithmetic Logic Unit The high performance Arithmetic Logic Unit (ALU) supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. After an arithmetic or logic operation, the Status Register is updated to reflect information about the result of the operation. The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Both 8- and 16-bit arithmetic is supported, and the instruction set allows for efficient implementation of 32-bit aritmetic. The ALU also provides a powerful multiplier supporting both signed and unsigned multiplication and fractional format. 6.5 Program Flow When the device is powered on, the CPU starts to execute instructions from the lowest address in the Flash Program Memory ‘0’. The Program Counter (PC) addresses the next instruction to be fetched. After a reset, the PC is set to location ‘0’. Program flow is provided by conditional and unconditional jump and call instructions, capable of addressing the whole address space directly. Most AVR instructions use a 16-bit word format, while a limited number uses a 32-bit format. During interrupts and subroutine calls, the return address PC is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. After reset the Stack Pointer (SP) points to the highest address in the internal SRAM. The SP is read/write accessible in the I/O memory space, enabling easy implementation of multiple stacks or stack areas. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR CPU. 9 8067L–AVR–08/10 XMEGA A1 7. Memories 7.1 Features • Flash Program Memory – One linear address space – In-System Programmable – Self-Programming and Bootloader support – Application Section for application code – Application Table Section for application code or data storage – Boot Section for application code or bootloader code – Separate lock bits and protection for all sections – Built in fast CRC check of a selectable flash program memory section • Data Memory – One linear address space – Single cycle access from CPU – SRAM – EEPROM Byte and page accessible Optional memory mapping for direct load and store – I/O Memory Configuration and Status registers for all peripherals and modules 16 bit-accessible General Purpose Register for global variables or flags – External Memory support SRAM SDRAM Memory mapped external hardware – Bus arbitration Safe and deterministic handling of CPU and DMA Controller priority – Separate buses for SRAM, EEPROM, I/O Memory and External Memory access Simultaneous bus access for CPU and DMA Controller • Production Signature Row Memory for factory programmed data Device ID for each microcontroller device type Serial number for each device Oscillator calibration bytes ADC, DAC and temperature sensor calibration data • User Signature Row One flash page in size Can be read and written from software Content is kept after chip erase 7.2 Overview The AVR architecture has two main memory spaces, the Program Memory and the Data Memory. In addition, the XMEGA A1 features an EEPROM Memory for non-volatile data storage. All three memory spaces are linear and require no paging. The available memory size configurations are shown in “Ordering Information” on page 2. In addition each device has a Flash memory signature row for calibration data, device identification, serial number etc. Non-volatile memory spaces can be locked for further write or read/write operations. This prevents unrestricted access to the application software. 10 8067L–AVR–08/10 XMEGA A1 7.3 In-System Programmable Flash Program Memory The XMEGA A1 devices contain On-chip In-System Programmable Flash memory for program storage, see Figure 7-1 on page 11. Since all AVR instructions are 16- or 32-bits wide, each Flash address location is 16 bits. The Program Flash memory space is divided into Application and Boot sections. Both sections have dedicated Lock Bits for setting restrictions on write or read/write operations. The Store Program Memory (SPM) instruction must reside in the Boot Section when used to write to the Flash memory. A third section inside the Application section is referred to as the Application Table section which has separate Lock bits for storage of write or read/write protection. The Application Table section can be used for storing non-volatile data or application software. Figure 7-1. Flash Program Memory (Hexadecimal address) Word Address 0 Application Section (Bytes) (384K/256K/192K/128K/64K) ... 2EFFF 2F000 2FFFF 30000 30FFF / / / / / 1EFFF 1F000 1FFFF 20000 20FFF / / / / / 16FFF 17000 17FFF 18000 18FFF / / / / / EFFF F000 FFFF 10000 10FFF / / / / / 77FF 7800 7FFF 8000 87FF Application Table Section (Bytes) (8K/8K/8K/8K/4K) Boot Section (Bytes) (8K/8K/8K/8K/4K) The Application Table Section and Boot Section can also be used for general application software. 7.4 Data Memory The Data Memory consists of the I/O Memory, EEPROM and SRAM memories, all within one linear address space, see Figure 7-2 on page 11. To simplify development, the memory map for all devices in the family is identical and with empty, reserved memory space for smaller devices. Figure 7-2. Data Memory Map (Hexadecimal address) ATxmega192A1 I/O Registers (4 KB) EEPROM (2 KB) RESERVED Byte Address 0 FFF 1000 17FF Byte Address 0 FFF 1000 17FF ATxmega128A1 I/O Registers (4 KB) EEPROM (2 KB) RESERVED Byte Address 0 FFF 1000 17FF ATxmega64A1 I/O Registers (4 KB) EEPROM (2 KB) RESERVED 11 8067L–AVR–08/10 XMEGA A1 Figure 7-2. Data Memory Map (Hexadecimal address) 2000 5FFF 6000 FFFFFF Internal SRAM (16 KB) External Memory (0 to 16 MB) 2000 3FFF 4000 FFFFFF Byte Address 0 FFF 1000 EEPROM (4 KB) 1FFF 2000 9FFF 10000 FFFFFF Internal SRAM (32 KB) External Memory (0 to 16 MB) 1FFF 2000 5FFF 6000 FFFFFF Internal SRAM (16 KB) External Memory (0 to 16 MB) Internal SRAM (8 KB) External Memory (0 to 16 MB) 2000 2FFF 3000 FFFFFF Byte Address 0 FFF 1000 EEPROM (4 KB) Internal SRAM (4 KB) External Memory (0 to 16 MB) ATxmega384A1 I/O Registers (4 KB) ATxmega256A1 I/O Registers (4 KB) 7.4.1 I/O Memory All peripherals and modules are addressable through I/O memory locations in the data memory space. All I/O memory locations can be accessed by the Load (LD/LDS/LDD) and Store (ST/STS/STD) instructions, transferring data between the 32 general purpose registers in the CPU and the I/O Memory. The IN and OUT instructions can address I/O memory locations in the range 0x00 - 0x3F directly. I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. The value of single bits can be checked by using the SBIS and SBIC instructions on these registers. The I/O memory address for all peripherals and modules in XMEGA A1 is shown in the “Peripheral Module Address Map” on page 58. 7.4.2 SRAM Data Memory The XMEGA A1 devices has internal SRAM memory for data storage. 7.4.3 EEPROM Data Memory The XMEGA A1 devices have internal EEPROM memory for non-volatile data storage. It is addressable either in a separate data space or it can be memory mapped into the normal data memory space. The EEPROM memory supports both byte and page access. 12 8067L–AVR–08/10 XMEGA A1 7.4.4 EBI - External Bus Interface • Supports SRAM up to – 512K Bytes using 2-port EBI – 16M Bytes using 3-port EBI Supports SDRAM up to – 128M bit using 3-port EBI Four software configurable Chip Selects Software configurable Wait State insertion Clocked from the Peripheral 2x Clock at up to two times the CPU clock speed • • • • The External Bus Interface (EBI) is the interface for connecting external peripheral and memory to the data memory space. The XMEGA A1 has 3 ports that can be used for the EBI. It can interface external SRAM, SDRAM, and/or peripherals such as LCD displays and other memory mapped devices. The address space, and the number of pins used, for the external memory is selectable from 256 bytes (8-bit) and up to 16M bytes (24-bit). Various multiplexing modes for address and data lines can be selected for optimal use of pins when more or less pins is available for the EBI. Each of the four chip selects has seperate configuration, and can be configured for SRAM, SRAM Low Pin Count (LPC) or SDRAM. The data memory address space associated for each chip select is decided by a configurable base address and address size for each chip celect. For SDRAM both 4-bit SDRAM is supported, and SDRAM configurations such as CAS Latency and Refresh rate is configurable in software. The EBI is clocked from the Peripheral 2x Clock, running up to two times faster than the CPU and supporting speeds of up to 64 MHz. 13 8067L–AVR–08/10 XMEGA A1 7.5 Production Signature Row The Production Signature Row is a separate memory section for factory programmed data. It contains calibration data for functions such as oscillators and analog modules. The production signature row also contains a device ID that identify each microcontroller device type, and a serial number that is unique for each manufactured device. The device ID for the available XMEGA A1 devices is shown in Table 7-1 on page 14. The serial number consist of the production LOT number, wafer number, and wafer coordinates for the device. The production signature row can not be written or erased, but it can be read from both application software and external programming. Table 7-1. Device ID bytes for XMEGA A1 devices. Device Byte 2 ATxmega64A1 ATxmega128A1 ATxmega192A1 ATxmega256A1 ATxmega384A1 4E 4C 4E 46 TBD Device ID bytes Byte 1 96 97 97 98 TBD Byte 0 1E 1E 1E 1E TBD 7.6 User Signature Row The User Signature Row is a separate memory section that is fully accessible (read and write) from application software and external programming. The user signature row is one flash page in size, and is meant for static user parameter storage, such as calibration data, custom serial numbers or identification numbers, random number seeds etc. This section is not erased by Chip Erase commands that erase the Flash, and requires a dedicated erase command. This ensures parameter storage during multiple program/erase session and on-chip debug sessions. 14 8067L–AVR–08/10 XMEGA A1 7.7 Flash and EEPROM Page Size The Flash Program Memory and EEPROM data memory is organized in pages. The pages are word accessible for the Flash and byte accessible for the EEPROM. Table 7-2 on page 15 shows the Flash Program Memory organization. Flash write and erase operations are performed on one page at a time, while reading the Flash is done one byte at a time. For Flash access the Z-pointer (Z[m:n]) is used for addressing. The most significant bits in the address (FPAGE) gives the page number and the least significant address bits (FWORD) gives the word in the page. Table 7-2. Devices Flash Size (Bytes) ATxmega64A1 ATxmega128A1 ATxmega192A1 ATxmega256A1 ATxmega384A1 64K + 4K 128K + 8K 192K + 8K 256K + 8K 384K + 8K Page Size (words) 128 256 256 256 256 Z[7:1] Z[8:1] Z[8:1] Z[8:1] Z[8:1] Z[16:8] Z[17:9] Z[18:9] Z[18:9] Z[19:9] Number of words and Pages in the Flash. FWORD FPAGE Application Size (Bytes) 64K 128K 192K 256K 384K No of Pages 256 256 384 512 768 Boot Size (Bytes) 4K 8K 8K 8K 8K No of Pages 16 16 16 16 16 Table 7-3 on page 15 shows EEPROM memory organization for the XMEGA A1 devices. EEPROM write and erase operations can be performed one page or one byte at a time, while reading the EEPROM is done one byte at a time. For EEPROM access the NVM Address Register (ADDR[m:n]) is used for addressing. The most significant bits in the address (E2PAGE) gives the page number and the least significant address bits (E2BYTE) gives the byte in the page. Table 7-3. Devices EEPROM Size ATxmega64A1 ATxmega128A1 ATxmega192A1 ATxmega256A1 ATxmega384A1 2 KB 2 KB 2 KB 4 KB 4 KB Number of Bytes and Pages in the EEPROM. Page Size (Bytes) 32 32 32 32 32 ADDR[4:0] ADDR[4:0] ADDR[4:0] ADDR[4:0] ADDR[4:0] ADDR[10:5] ADDR[10:5] ADDR[10:5] ADDR[11:5] ADDR[11:5] 64 64 64 128 128 E2BYTE E2PAGE No of Pages 15 8067L–AVR–08/10 XMEGA A1 8. DMAC - Direct Memory Access Controller 8.1 Features • Allows High-speed data transfer – From memory to peripheral – From memory to memory – From peripheral to memory – From peripheral to peripheral 4 Channels From 1 byte and up to 16M bytes transfers in a single transaction Multiple addressing modes for source and destination address – Increment – Decrement – Static 1, 2, 4, or 8 byte Burst Transfers Programmable priority between channels • • • • • 8.2 Overview The XMEGA A1 has a Direct Memory Access (DMA) Controller to move data between memories and peripherals in the data space. The DMA controller uses the same data bus as the CPU to transfer data. It has 4 channels that can be configured independently. Each DMA channel can perform data transfers in blocks of configurable size from 1 to 64K bytes. A repeat counter can be used to repeat each block transfer for single transactions up to 16M bytes. Each DMA channel can be configured to access the source and destination memory address with incrementing, decrementing or static addressing. The addressing is independent for source and destination address. When the transaction is complete the original source and destination address can automatically be reloaded to be ready for the next transaction. The DMAC can access all the peripherals through their I/O memory registers, and the DMA may be used for automatic transfer of data to/from communication modules, as well as automatic data retrieval from ADC conversions, data transfer to DAC conversions, or data transfer to or from port pins. A wide range of transfer triggers is available from the peripherals, Event System and software. Each DMA channel has different transfer triggers. To allow for continuous transfers, two channels can be interlinked so that the second takes over the transfer when the first is finished and vice versa. The DMA controller can read from memory mapped EEPROM, but it cannot write to the EEPROM or access the Flash. 16 8067L–AVR–08/10 XMEGA A1 9. Event System 9.1 Features • • • • Inter-peripheral communication and signalling with minimum latency CPU and DMA independent operation 8 Event Channels allows for up to 8 signals to be routed at the same time Events can be generated by – Timer/Counters (TCxn) – Real Time Counter (RTC) – Analog to Digital Converters (ADCx) – Analog Comparators (ACx) – Ports (PORTx) – System Clock (ClkSYS) – Software (CPU) Events can be used by – Timer/Counters (TCxn) – Analog to Digital Converters (ADCx) – Digital to Analog Converters (DACx) – Ports (PORTx) – DMA Controller (DMAC) – IR Communication Module (IRCOM) The same event can be used by multiple peripherals for synchronized timing Advanced Features – Manual Event Generation from software (CPU) – Quadrature Decoding – Digital Filtering Functions in Active and Idle mode • • • • 9.2 Overview The Event System is a set of features for inter-peripheral communication. It enables the possibility for a change of state in one peripheral to automatically trigger actions in one or more peripherals. These changes in a peripheral that will trigger actions in other peripherals are configurable by software. It is a simple, but powerful system as it allows for autonomous control of peripherals without any use of interrupts, CPU or DMA resources. The indication of a change in a peripheral is referred to as an event, and is usually the same as the interrupt conditions for that peripheral. Events are passed between peripherals using a dedicated routing network called the Event Routing Network. Figure 9-1 on page 18 shows a basic block diagram of the Event System with the Event Routing Network and the peripherals to which it is connected. This highly flexible system can be used for simple routing of signals, pin functions or for sequencing of events. The maximum latency is two CPU clock cycles from when an event is generated in one peripheral, until the actions are triggered in one or more other peripherals. The Event System is functional in both Active and Idle modes. 17 8067L–AVR–08/10 XMEGA A1 Figure 9-1. Event system block diagram. PORTx ClkSYS CPU ADCx Event Routing Network DACx RTC ACx IRCOM T/Cxn DMAC The Event Routing Network can directly connect together ADCs, DACs, Analog Comparators (ACx), I/O ports (PORTx), the Real-time Counter (RTC), Timer/Counters (T/C) and the IR Communication Module (IRCOM). Events can also be generated from software (CPU). All events from all peripherals are always routed into the Event Routing Network. This consist of eight multiplexers where each can be configured in software to select which event to be routed into that event channel. All eight event channels are connected to the peripherals that can use events, and each of these peripherals can be configured to use events from one or more event channels to automatically trigger a software selectable action. 18 8067L–AVR–08/10 XMEGA A1 10. System Clock and Clock options 10.1 Features • Fast start-up time • Safe run-time clock switching • Internal Oscillators: – 32 MHz run-time calibrated RC oscillator – 2 MHz run-time calibrated RC oscillator – 32.768 kHz calibrated RC oscillator – 32 kHz Ultra Low Power (ULP) oscillator with 1 kHz ouput External clock options – 0.4 - 16 MHz Crystal Oscillator – 32 kHz Crystal Oscillator – External clock PLL with internal and external clock options with 1 to 31x multiplication Clock Prescalers with 1 to 2048x division Fast peripheral clock running at 2 and 4 times the CPU clock speed Automatic Run-Time Calibration of internal oscillators Crystal Oscillator failure detection • • • • • • 10.2 Overview XMEGA A1 has an advanced clock system, supporting a large number of clock sources. It incorporates both integrated oscillators, external crystal oscillators and resonators. A high frequency Phase Locked Loop (PLL) and clock prescalers can be controlled from software to generate a wide range of clock frequencies from the clock source input. It is possible to switch between clock sources from software during run-time. After reset the device will always start up running from the 2 Mhz internal oscillator. A calibration feature is available, and can be used for automatic run-time calibration of the internal 2 MHz and 32 MHz oscillators. This reduce frequency drift over voltage and temperature. A Crystal Oscillator Failure Monitor can be enabled to issue a Non-Maskable Interrupt and switch to internal oscillator if the external oscillator fails. Figure 10-1 on page 20 shows the principal clock system in XMEGA A1. 19 8067L–AVR–08/10 XMEGA A1 Figure 10-1. Clock system overview clkULP 32 kHz ULP Internal Oscillator WDT/BOD clkRTC 32.768 kHz Calibrated Internal Oscillator 2 MHz Run-Time Calibrated Internal Oscillator 32 MHz Run-time Calibrated Internal Oscillator 32.768 KHz Crystal Oscillator RTC PERIPHERALS ADC DAC CLOCK CONTROL clkPER UNIT with PLL and Prescaler PORTS ... DMA INTERRUPT EVSYS RAM 0.4 - 16 MHz Crystal Oscillator CPU clkCPU NVM MEMORY External Clock Input FLASH EEPROM Each clock source is briefly described in the following sub-sections. 10.3 10.3.1 Clock Options 32 kHz Ultra Low Power Internal Oscillator The 32 kHz Ultra Low Power (ULP) Internal Oscillator is a very low power consumption clock source. It is used for the Watchdog Timer, Brown-Out Detection and as an asynchronous clock source for the Real Time Counter. This oscillator cannot be used as the system clock source, and it cannot be directly controlled from software. 10.3.2 32.768 kHz Calibrated Internal Oscillator The 32.768 kHz Calibrated Internal Oscillator is a high accuracy clock source that can be used as the system clock source or as an asynchronous clock source for the Real Time Counter. It is calibrated during production to provide a default frequency which is close to its nominal frequency. 20 8067L–AVR–08/10 XMEGA A1 10.3.3 32.768 kHz Crystal Oscillator The 32.768 kHz Crystal Oscillator is a low power driver for an external watch crystal. It can be used as system clock source or as asynchronous clock source for the Real Time Counter. 10.3.4 0.4 - 16 MHz Crystal Oscillator The 0.4 - 16 MHz Crystal Oscillator is a driver intended for driving both external resonators and crystals ranging from 400 kHz to 16 MHz. 10.3.5 2 MHz Run-time Calibrated Internal Oscillator The 2 MHz Run-time Calibrated Internal Oscillator is a high frequency oscillator. It is calibrated during productionn to provide a default frequency which is close to its nominal frequency. The oscillator can use the 32 kHz Calibrated Internal Oscillator or the 32 kHz Crystal Oscillator as a source for calibrating the frequency run-time to compensate for temperature and voltage drift hereby optimizing the accuracy of the oscillator. 10.3.6 32 MHz Run-time Calibrated Internal Oscillator The 32 MHz Run-time Calibrated Internal Oscillator is a high frequency oscillator. It is calibrated during production to provide a default frequency which is close to its nominal frequency. The oscillator can use the 32 kHz Calibrated Internal Oscillator or the 32 kHz Crystal Oscillator as a source for calibrating the frequency run-time to compensate for temperature and voltage drift hereby optimizing the accuracy of the oscillator. 10.3.7 External Clock input The external clock input gives the possibility to connect a clock from an external source. 10.3.8 PLL with Multiplication factor 1 - 31x The PLL provides the possibility of multiplying a frequency by any number from 1 to 31. In combination with the prescalers, this gives a wide range of output frequencies from all clock sources. 21 8067L–AVR–08/10 XMEGA A1 11. Power Management and Sleep Modes 11.1 Features • 5 sleep modes – Idle – Power-down – Power-save – Standby – Extended standby • Power Reduction registers to disable clocks to unused peripherals 11.2 Overview The XMEGA A1 provides various sleep modes tailored to reduce power consumption to a minimum. All sleep modes are available and can be entered from Active mode. In Active mode the CPU is executing application code. The application code decides when and what sleep mode to enter. Interrupts from enabled peripherals and all enabled reset sources can restore the microcontroller from sleep to Active mode. In addition, Power Reduction registers provide a method to stop the clock to individual peripherals from software. When this is done, the current state of the peripheral is frozen and there is no power consumption from that peripheral. This reduces the power consumption in Active mode and Idle sleep mode. 11.3 11.3.1 Sleep Modes Idle Mode In Idle mode the CPU and Non-Volatile Memory are stopped, but all peripherals including the Interrupt Controller, Event System and DMA Controller are kept running. Interrupt requests from all enabled interrupts will wake the device. 11.3.2 Power-down Mode In Power-down mode all system clock sources, and the asynchronous Real Time Counter (RTC) clock source, are stopped. This allows operation of asynchronous modules only. The only interrupts that can wake up the MCU are the Two Wire Interface address match interrupts, and asynchronous port interrupts, e.g pin change. 11.3.3 Power-save Mode Power-save mode is identical to Power-down, with one exception: If the RTC is enabled, it will keep running during sleep and the device can also wake up from RTC interrupts. 11.3.4 Standby Mode Standby mode is identical to Power-down with the exception that all enabled system clock sources are kept running, while the CPU, Peripheral and RTC clocks are stopped. This reduces the wake-up time when external crystals or resonators are used. 11.3.5 Extended Standby Mode Extended Standby mode is identical to Power-save mode with the exception that all enabled system clock sources are kept running while the CPU and Peripheral clocks are stopped. This reduces the wake-up time when external crystals or resonators are used. 22 8067L–AVR–08/10 XMEGA A1 12. System Control and Reset 12.1 Features • Multiple reset sources for safe operation and device reset – Power-On Reset – External Reset – Watchdog Reset The Watchdog Timer runs from separate, dedicated oscillator – Brown-Out Reset Accurate, programmable Brown-Out levels – PDI reset – Software reset • Asynchronous reset – No running clock in the device is required for reset • Reset status register 12.2 Resetting the AVR During reset, all I/O registers are set to their initial values. The SRAM content is not reset. Application execution starts from the Reset Vector. The instruction placed at the Reset Vector should be an Absolute Jump (JMP) instruction to the reset handling routine. By default the Reset Vector address is the lowest Flash program memory address, ‘0’, but it is possible to move the Reset Vector to the first address in the Boot Section. The I/O ports of the AVR are immediately tri-stated when a reset source goes active. The reset functionality is asynchronous, so no running clock is required to reset the device. After the device is reset, the reset source can be determined by the application by reading the Reset Status Register. 12.3 12.3.1 Reset Sources Power-On Reset The MCU is reset when the supply voltage VCC is below the Power-on Reset threshold voltage. 12.3.2 External Reset The MCU is reset when a low level is present on the RESET pin. 12.3.3 Watchdog Reset The MCU is reset when the Watchdog Timer period expires and the Watchdog Reset is enabled. The Watchdog Timer runs from a dedicated oscillator independent of the System Clock. For more details see “WDT - Watchdog Timer” on page 24. 12.3.4 Brown-Out Reset The MCU is reset when the supply voltage VCC is below the Brown-Out Reset threshold voltage and the Brown-out Detector is enabled. The Brown-out threshold voltage is programmable. 12.3.5 PDI reset The MCU can be reset through the Program and Debug Interface (PDI). 23 8067L–AVR–08/10 XMEGA A1 12.3.6 Software reset The MCU can be reset by the CPU writing to a special I/O register through a timed sequence. 12.4 12.4.1 WDT - Watchdog Timer Features • 11 selectable timeout periods, from 8 ms to 8s. • Two operation modes – Standard mode – Window mode • Runs from the 1 kHz output of the 32 kHz Ultra Low Power oscillator • Configuration lock to prevent unwanted changes 12.4.2 Overview The XMEGA A1 has a Watchdog Timer (WDT). The WDT will run continuously when turned on and if the Watchdog Timer is not reset within a software configurable time-out period, the microcontroller will be reset. The Watchdog Reset (WDR) instruction must be run by software to reset the WDT, and prevent microcontroller reset. The WDT has a Window mode. In this mode the WDR instruction must be run within a specified period called a window. Application software can set the minimum and maximum limits for this window. If the WDR instruction is not executed inside the window limits, the microcontroller will be reset. A protection mechanism using a timed write sequence is implemented in order to prevent unwanted enabling, disabling or change of WDT settings. For maximum safety, the WDT also has an Always-on mode. This mode is enabled by programming a fuse. In Always-on mode, application software can not disable the WDT. 24 8067L–AVR–08/10 XMEGA A1 13. PMIC - Programmable Multi-level Interrupt Controller 13.1 Features • Separate interrupt vector for each interrupt • Short, predictable interrupt response time • Programmable Multi-level Interrupt Controller – 3 programmable interrupt levels – Selectable priority scheme within low level interrupts (round-robin or fixed) – Non-Maskable Interrupts (NMI) • Interrupt vectors can be moved to the start of the Boot Section 13.2 Overview XMEGA A1 has a Programmable Multi-level Interrupt Controller (PMIC). All peripherals can define three different priority levels for interrupts; high, medium or low. Medium level interrupts may interrupt low level interrupt service routines. High level interrupts may interrupt both lowand medium level interrupt service routines. Low level interrupts have an optional round robin scheme to make sure all interrupts are serviced within a certain amount of time. The built in oscillator failure detection mechanism can issue a Non-Maskable Interrupt (NMI). 13.3 Interrupt vectors When an interrupt is serviced, the program counter will jump to the interrupt vector address. The interrupt vector is the sum of the peripheral’s base interrupt address and the offset address for specific interrupts in each peripheral. The base addresses for the XMEGA A1 devices are shown in Table 13-1. Offset addresses for each interrupt available in the peripheral are described for each peripheral in the XMEGA A manual. For peripherals or modules that have only one interrupt, the interrupt vector is shown in Table 13-1. The program address is the word address. Table 13-1. Reset and Interrupt Vectors Source RESET OSCF_INT_vect PORTC_INT_base PORTR_INT_base DMA_INT_base RTC_INT_base TWIC_INT_base TCC0_INT_base TCC1_INT_base SPIC_INT_vect USARTC0_INT_base USARTC1_INT_base AES_INT_vect Crystal Oscillator Failure Interrupt vector (NMI) Port C Interrupt base Port R Interrupt base DMA Controller Interrupt base Real Time Counter Interrupt base Two-Wire Interface on Port C Interrupt base Timer/Counter 0 on port C Interrupt base Timer/Counter 1 on port C Interrupt base SPI on port C Interrupt vector USART 0 on port C Interrupt base USART 1 on port C Interrupt base AES Interrupt vector Interrupt Description Program Address (Base Address) 0x000 0x002 0x004 0x008 0x00C 0x014 0x018 0x01C 0x028 0x030 0x032 0x038 0x03E 25 8067L–AVR–08/10 XMEGA A1 Table 13-1. Reset and Interrupt Vectors (Continued) Source NVM_INT_base PORTB_INT_base ACB_INT_base ADCB_INT_base PORTE_INT_base TWIE_INT_base TCE0_INT_base TCE1_INT_base SPIE_INT_vect USARTE0_INT_base USARTE1_INT_base PORTD_INT_base PORTA_INT_base ACA_INT_base ADCA_INT_base TWID_INT_base TCD0_INT_base TCD1_INT_base SPID_INT_vector USARTD0_INT_base USARTD1_INT_base PORTQ_INT_base PORTH_INT_base PORTJ_INT_base PORTK_INT_base PORTF_INT_base TWIF_INT_base TCF0_INT_base TCF1_INT_base SPIF_INT_vector USARTF0_INT_base USARTF1_INT_base Interrupt Description Non-Volatile Memory Interrupt base Port B Interrupt base Analog Comparator on Port B Interrupt base Analog to Digital Converter on Port B Interrupt base Port E Interrupt base Two-Wire Interface on Port E Interrupt base Timer/Counter 0 on port E Interrupt base Timer/Counter 1 on port E Interrupt base SPI on port E Interrupt vector USART 0 on port E Interrupt base USART 1 on port E Interrupt base Port D Interrupt base Port A Interrupt base Analog Comparator on Port A Interrupt base Analog to Digital Converter on Port A Interrupt base Two-Wire Interface on Port D Interrupt base Timer/Counter 0 on port D Interrupt base Timer/Counter 1 on port D Interrupt base SPI on port D Interrupt vector USART 0 on port D Interrupt base USART 1 on port D Interrupt base Port Q INT base Port H INT base Port J INT base Port K INT base Port F INT base Two-Wire Interface on Port F INT base Timer/Counter 0 on port F Interrupt base Timer/Counter 1 on port F Interrupt base SPI ion port F Interrupt base USART 0 on port F Interrupt base USART 1 on port F Interrupt base Program Address (Base Address) 0x040 0x044 0x048 0x04E 0x056 0x05A 0x05E 0x06A 0x072 0x074 0x07A 0x080 0x084 0x088 0x08E 0x096 0x09A 0x0A6 0x0AE 0x0B0 0x0B6 0x0BC 0x0C0 0x0C4 0x0C8 0x0D0 0x0D4 0x0D8 0x0E4 0x0EC 0x0EE 0x0F4 26 8067L–AVR–08/10 XMEGA A1 14. I/O Ports 14.1 Features • Selectable input and output configuration for each pin individually • Flexible pin configuration through dedicated Pin Configuration Register • Synchronous and/or asynchronous input sensing with port interrupts and events – Sense both edges – Sense rising edges – Sense falling edges – Sense low level Asynchronous wake-up from all input sensing configurations Two port interrupts with flexible pin masking Highly configurable output driver and pull settings: – Totem-pole – Pull-up/-down – Wired-AND – Wired-OR – Bus-keeper – Inverted I/O Optional Slew rate control Configuration of multiple pins in a single operation Read-Modify-Write (RMW) support Toggle/clear/set registers for Output and Direction registers Clock output on port pin Event Channel 0 output on port pin 7 Mapping of port registers (virtual ports) into bit accessible I/O memory space • • • • • • • • • • 14.2 Overview The XMEGA A1 devices have flexible General Purpose I/O Ports. A port consists of up to 8 pins, ranging from pin 0 to pin 7. The ports implement several functions, including synchronous/asynchronous input sensing, pin change interrupts and configurable output settings. All functions are individual per pin, but several pins may be configured in a single operation. 14.3 I/O configuration All port pins (Pn) have programmable output configuration. In addition, all port pins have an inverted I/O function. For an input, this means inverting the signal between the port pin and the pin register. For an output, this means inverting the output signal between the port register and the port pin. The inverted I/O function can be used also when the pin is used for alternate functions. The port pins also have configurable slew rate limitation to reduce electromagnetic emission. 27 8067L–AVR–08/10 XMEGA A1 14.3.1 Push-pull Figure 14-1. I/O configuration - Totem-pole DIRn OUTn INn Pn 14.3.2 Pull-down Figure 14-2. I/O configuration - Totem-pole with pull-down (on input) DIRn OUTn INn Pn 14.3.3 Pull-up Figure 14-3. I/O configuration - Totem-pole with pull-up (on input) DIRn OUTn INn 14.3.4 Bus-keeper Pn The bus-keeper’s weak output produces the same logical level as the last output level. It acts as a pull-up if the last level was ‘1’, and pull-down if the last level was ‘0’. 28 8067L–AVR–08/10 XMEGA A1 Figure 14-4. I/O configuration - Totem-pole with bus-keeper DIRn OUTn INn Pn 14.3.5 Others Figure 14-5. Output configuration - Wired-OR with optional pull-down OUTn Pn INn Figure 14-6. I/O configuration - Wired-AND with optional pull-up INn Pn OUTn 29 8067L–AVR–08/10 XMEGA A1 14.4 Input sensing • • • • Sense both edges Sense rising edges Sense falling edges Sense low level Input sensing is synchronous or asynchronous depending on the enabled clock for the ports, and the configuration is shown in Figure 14-7 on page 30. Figure 14-7. Input sensing system overview Asynchronous sensing EDGE DETECT Interrupt Control IREQ Synchronous sensing Pn Synchronizer INn D QD Q EDGE DETECT Event INVERTED I/O R R When a pin is configured with inverted I/O the pin value is inverted before the input sensing. 14.5 Port Interrupt Each ports have two interrupts with seperate priority and interrupt vector. All pins on the port can be individually selected as source for each of the interrupts. The interrupts are then triggered according to the input sense configuration for each pin configured as source for the interrupt. 14.6 Alternate Port Functions In addition to the input/output functions on all port pins, most pins have alternate functions. This means that other modules or peripherals connected to the port can use the port pins for their functions, such as communication or pulse-width modulation. “Pinout and Pin Functions” on page 49 shows which modules on peripherals that enables alternate functions on a pin, and what alternate functions that is available on a pin. 30 8067L–AVR–08/10 XMEGA A1 15. T/C - 16-bit Timer/Counter 15.1 Features • Eight 16-bit Timer/Counters – Four Timer/Counters of type 0 – Four Timer/Counters of type 1 Four Compare or Capture (CC) Channels in Timer/Counter 0 Two Compare or Capture (CC) Channels in Timer/Counter 1 Double Buffered Timer Period Setting Double Buffered Compare or Capture Channels Waveform Generation: – Single Slope Pulse Width Modulation – Dual Slope Pulse Width Modulation – Frequency Generation Input Capture: – Input Capture with Noise Cancelling – Frequency capture – Pulse width capture – 32-bit input capture Event Counter with Direction Control Timer Overflow and Timer Error Interrupts and Events One Compare Match or Capture Interrupt and Event per CC Channel Supports DMA Operation Hi-Resolution Extension (Hi-Res) Advanced Waveform Extension (AWEX) • • • • • • • • • • • • 15.2 Overview XMEGA A1 has eight Timer/Counters, four Timer/Counter 0 and four Timer/Counter 1. The difference between them is that Timer/Counter 0 has four Compare/Capture channels, while Timer/Counter 1 has two Compare/Capture channels. The Timer/Counters (T/C) are 16-bit and can count any clock, event or external input in the microcontroller. A programmable prescaler is available to get a useful T/C resolution. Updates of Timer and Compare registers are double buffered to ensure glitch free operation. Single slope PWM, dual slope PWM and frequency generation waveforms can be generated using the Compare Channels. Through the Event System, any input pin or event in the microcontroller can be used to trigger input capture, hence no dedicated pins is required for this. The input capture has a noise canceller to avoid incorrect capture of the T/C, and can be used to do frequency and pulse width measurements. A wide range of interrupt or event sources are available, including T/C Overflow, Compare match and Capture for each Compare/Capture channel in the T/C. PORTC, PORTD, PORTE and PORTF each has one Timer/Counter 0 and one Timer/Counter1. Notation of these Timer/Counters are TCC0 (Time/Counter C0), TCC1, TCD0, TCD1, TCE0, TCE1, TCF0, and TCF1, respectively. 31 8067L–AVR–08/10 XMEGA A1 Figure 15-1. Overview of a Timer/Counter and closely related peripherals Timer/Counter Base Counter Timer Period Counter Control Logic Prescaler Event System clkPER clkPER4 Compare/Capture Channel D Compare/Capture Channel C Compare/Capture Channel B Compare/Capture Channel A Comparator Buffer Capture Control Waveform Generation AWeX Hi-Res DTI Dead-Time Insertion Pattern Generation Fault Protection The Hi-Resolution Extension can be enabled to increase the waveform generation resolution by 2 bits (4x). This is available for all Timer/Counters. See “Hi-Res - High Resolution Extension” on page 34 for more details. The Advanced Waveform Extension can be enabled to provide extra and more advanced features for the Timer/Counter. This are only available for Timer/Counter 0. See “AWEX - Advanced Waveform Extension” on page 33 for more details. PORT 32 8067L–AVR–08/10 XMEGA A1 16. AWEX - Advanced Waveform Extension 16.1 Features • • • • • • • • Output with complementary output from each Capture channel Four Dead Time Insertion (DTI) Units, one for each Capture channel 8-bit DTI Resolution Separate High and Low Side Dead-Time Setting Double Buffered Dead-Time Event Controlled Fault Protection Single Channel Multiple Output Operation (for BLDC motor control) Double Buffered Pattern Generation 16.2 Overview The Advanced Waveform Extension (AWEX) provides extra features to the Timer/Counter in Waveform Generation (WG) modes. The AWEX enables easy and safe implementation of for example, advanced motor control (AC, BLDC, SR, and Stepper) and power control applications. Any WG output from a Timer/Counter 0 is split into a complimentary pair of outputs when any AWEX feature is enabled. These output pairs go through a Dead-Time Insertion (DTI) unit that enables generation of the non-inverted Low Side (LS) and inverted High Side (HS) of the WG output with dead time insertion between LS and HS switching. The DTI output will override the normal port value according to the port override setting. Optionally the final output can be inverted by using the invert I/O setting for the port pin. The Pattern Generation unit can be used to generate a synchronized bit pattern on the port it is connected to. In addition, the waveform generator output from Compare Channel A can be distributed to, and override all port pins. When the Pattern Generator unit is enabled, the DTI unit is bypassed. The Fault Protection unit is connected to the Event System. This enables any event to trigger a fault condition that will disable the AWEX output. Several event channels can be used to trigger fault on several different conditions. The AWEX is available for TCC0 and TCE0. The notation of these peripherals are AWEXC and AWEXE. 33 8067L–AVR–08/10 XMEGA A1 17. Hi-Res - High Resolution Extension 17.1 Features • Increases Waveform Generator resolution by 2-bits (4x) • Supports Frequency, single- and dual-slope PWM operation • Supports the AWEX when this is enabled and used for the same Timer/Counter 17.2 Overview The Hi-Resolution (Hi-Res) Extension is able to increase the resolution of the waveform generation output by a factor of 4. When enabled for a Timer/Counter, the Fast Peripheral clock running at four times the CPU clock speed will be as input to the Timer/Counter. The High Resolution Extension can also be used when an AWEX is enabled and used with a Timer/Counter. XMEGA A1 devices have four Hi-Res Extensions that each can be enabled for each Timer/Counters pair on PORTC, PORTD, PORTE and PORTF. The notation of these peripherals are HIRESC, HIRESD, HIRESE and HIRESF, respectively. 34 8067L–AVR–08/10 XMEGA A1 18. RTC - 16-bit Real-Time Counter 18.1 Features • • • • • • 16-bit Timer Flexible Tick resolution ranging from 1 Hz to 32.768 kHz One Compare register One Period register Clear timer on Overflow or Compare Match Overflow or Compare Match event and interrupt generation 18.2 Overview The XMEGA A1 includes a 16-bit Real-time Counter (RTC). The RTC can be clocked from an accurate 32.768 kHz Crystal Oscillator, the 32.768 kHz Calibrated Internal Oscillator, or from the 32 kHz Ultra Low Power Internal Oscillator. The RTC includes both a Period and a Compare register. For details, see Figure 18-1. A wide range of Resolution and Time-out periods can be configured using the RTC. With a maximum resolution of 30.5 µs, time-out periods range up to 2000 seconds. With a resolution of 1 second, the maximum time-out period is over 18 hours (65536 seconds). Figure 18-1. Real Time Counter overview Period 32 kHz 10-bit prescaler 1 kHz = = Overflow Counter Compare Match Compare 35 8067L–AVR–08/10 XMEGA A1 19. TWI - Two-Wire Interface 19.1 Features • • • • • • • • • • • • Four Identical TWI peripherals Simple yet Powerful and Flexible Communication Interface Both Master and Slave Operation Supported Device can Operate as Transmitter or Receiver 7-bit Address Space Allows up to 128 Different Slave Addresses Multi-master Arbitration Support Up to 400 kHz Data Transfer Speed Slew-rate Limited Output Drivers Noise Suppression Circuitry Rejects Spikes on Bus Lines Fully Programmable Slave Address with General Call Support Address Recognition Causes Wake-up when in Sleep Mode I2C and System Management Bus (SMBus) compatible 19.2 Overview The Two-Wire Interface (TWI) is a bi-directional wired-AND bus with only two lines, the clock (SCL) line and the data (SDA) line. The protocol makes it possible to interconnect up to 128 individually addressable devices. Since it is a multi-master bus, one or more devices capable of taking control of the bus can be connected. The only external hardware needed to implement the bus is a single pull-up resistor for each of the TWI bus lines. Mechanisms for resolving bus contention are inherent in the TWI protocol. PORTC, PORTD, PORTE, and PORTF each has one TWI. Notation of these peripherals are TWIC, TWID, TWIE, and TWIF, respectively. 36 8067L–AVR–08/10 XMEGA A1 20. SPI - Serial Peripheral Interface 20.1 Features • • • • • • • • • Four Identical SPI peripherals Full-duplex, Three-wire Synchronous Data Transfer Master or Slave Operation LSB First or MSB First Data Transfer Seven Programmable Bit Rates End of Transmission Interrupt Flag Write Collision Flag Protection Wake-up from Idle Mode Double Speed (CK/2) Master SPI Mode 20.2 Overview The Serial Peripheral Interface (SPI) allows high-speed full-duplex, synchronous data transfer between different devices. Devices can communicate using a master-slave scheme, and data is transferred both to and from the devices simultaneously. PORTC, PORTD, PORTE, and PORTF each has one SPI. Notation of these peripherals are SPIC, SPID, SPIE, and SPIF, respectively. 37 8067L–AVR–08/10 XMEGA A1 21. USART 21.1 Features • • • • • • • • • • • • • • • Eight Identical USART peripherals Full Duplex Operation (Independent Serial Receive and Transmit Registers) Asynchronous or Synchronous Operation Master or Slave Clocked Synchronous Operation High-resolution Arithmetic Baud Rate Generator Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits Odd or Even Parity Generation and Parity Check Supported by Hardware Data OverRun Detection Framing Error Detection Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete Multi-processor Communication Mode Double Speed Asynchronous Communication Mode Master SPI mode for SPI communication IrDA support through the IRCOM module 21.2 Overview The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication module. The USART supports full duplex communication, and both asynchronous and clocked synchronous operation. The USART can also be set in Master SPI mode to be used for SPI communication. Communication is frame based, and the frame format can be customized to support a wide range of standards. The USART is buffered in both direction, enabling continued data transmission without any delay between frames. There are separate interrupt vectors for receive and transmit complete, enabling fully interrupt driven communication. Frame error and buffer overflow are detected in hardware and indicated with separate status flags. Even or odd parity generation and parity check can also be enabled. One USART can use the IRCOM module to support IrDA 1.4 physical compliant pulse modulation and demodulation for baud rates up to 115.2 kbps. PORTC, PORTD, PORTE, and PORTF each has two USARTs. Notation of these peripherals are USARTC0, USARTC1, USARTD0, USARTD1, USARTE0, USARTE1, USARTF0, USARTF1, respectively. 38 8067L–AVR–08/10 XMEGA A1 22. IRCOM - IR Communication Module 22.1 Features • Pulse modulation/demodulation for infrared communication • Compatible to IrDA 1.4 physical for baud rates up to 115.2 kbps • Selectable pulse modulation scheme – 3/16 of baud rate period – Fixed pulse period, 8-bit programmable – Pulse modulation disabled • Built in filtering • Can be connected to and used by one USART at a time 22.2 Overview XMEGA contains an Infrared Communication Module (IRCOM) for IrDA communication with baud rates up to 115.2 kbps. This supports three modulation schemes: 3/16 of baud rate period, fixed programmable pulse time based on the Peripheral Clock speed, or pulse modulation disabled. There is one IRCOM available which can be connected to any USART to enable infrared pulse coding/decoding for that USART. 39 8067L–AVR–08/10 XMEGA A1 23. Crypto Engine 23.1 Features • Data Encryption Standard (DES) CPU instruction • Advanced Encryption Standard (AES) Crypto module • DES Instruction – Encryption and Decryption – Single-cycle DES instruction – Encryption/Decryption in 16 clock cycles per 8-byte block • AES Crypto Module – Encryption and Decryption – Support 128-bit keys – Support XOR data load mode to the State memory for Cipher Block Chaining – Encryption/Decryption in 375 clock cycles per 16-byte block 23.2 Overview The Advanced Encryption Standard (AES) and Data Encryption Standard (DES) are two commonly used encryption standards. These are supported through an AES peripheral module and a DES CPU instruction. All communication interfaces and the CPU can optionally use AES and DES encrypted communication and data storage. DES is supported by a DES instruction in the AVR XMEGA CPU. The 8-byte key and 8-byte data blocks must be loaded into the Register file, and then DES must be executed 16 times to encrypt/decrypt the data block. The AES Crypto Module encrypts and decrypts 128-bit data blocks with the use of a 128-bit key. The key and data must be loaded into the key and state memory in the module before encryption/decryption is started. It takes 375 peripheral clock cycles before the encryption/decryption is done and decrypted/encrypted data can be read out, and an optional interrupt can be generated. The AES Crypto Module also has DMA support with transfer triggers when encryption/decryption is done and optional auto-start of encryption/decryption when the state memory is fully loaded. 40 8067L–AVR–08/10 XMEGA A1 24. ADC - 12-bit Analog to Digital Converter 24.1 Features • • • • • • • Two ADCs with 12-bit resolution 2 Msps sample rate for each ADC Signed and Unsigned conversions 4 result registers with individual input channel control for each ADC 8 single ended inputs for each ADC 8x4 differential inputs for each ADC 4 internal inputs: – Integrated Temperature Sensor – DAC Output – VCC voltage divided by 10 – Bandgap voltage Software selectable gain of 2, 4, 8, 16, 32 or 64 Software selectable resolution of 8- or 12-bit. Internal or External Reference selection Event triggered conversion for accurate timing DMA transfer of conversion results Interrupt/Event on compare result • • • • • • 24.2 Overview XMEGA A1 devices have two Analog to Digital Converters (ADC), see Figure 24-1 on page 42. The two ADC modules can be operated simultaneously, individually or synchronized. The ADC converts analog voltages to digital values. The ADC has 12-bit resolution and is capable of converting up to 2 million samples per second. The input selection is flexible, and both single-ended and differential measurements can be done. For differential measurements an optional gain stage is available to increase the dynamic range. In addition several internal signal inputs are available. The ADC can provide both signed and unsigned results. This is a pipeline ADC. A pipeline ADC consists of several consecutive stages, where each stage convert one part of the result. The pipeline design enables high sample rate at low clock speeds, and remove limitations on samples speed versus propagation delay. This also means that a new analog voltage can be sampled and a new ADC measurement started while other ADC measurements are ongoing. ADC measurements can either be started by application software or an incoming event from another peripheral in the device. Four different result registers with individual input selection (MUX selection) are provided to make it easier for the application to keep track of the data. Each result register and MUX selection pair is referred to as an ADC Channel. It is possible to use DMA to move ADC results directly to memory or peripherals when conversions are done. Both internal and external analog reference voltages can be used. An accurate internal 1.0V reference is available. An integrated temperature sensor is available and the output from this can be measured with the ADC. The output from the DAC, VCC/10 and the Bandgap voltage can also be measured by the ADC. 41 8067L–AVR–08/10 XMEGA A1 Figure 24-1. ADC overview Channel A MUX selection Channel B MUX selection Channel C MUX selection Internal inputs Channel D MUX selection Configuration Reference selection Channel A Register Channel B Register Pin inputs ADC Channel C Register Channel D Register Pin inputs 1-64 X Event Trigger Each ADC has four MUX selection registers with a corresponding result register. This means that four channels can be sampled within 1.5 µs without any intervention by the application other than starting the conversion. The results will be available in the result registers. The ADC may be configured for 8- or 12-bit result, reducing the minimum conversion time (propagation delay) from 3.5 µs for 12-bit to 2.5 µs for 8-bit result. ADC conversion results are provided left- or right adjusted with optional ‘1’ or ‘0’ padding. This eases calculation when the result is represented as a signed integer (signed 16-bit number). PORTA and PORTB each has one ADC. Notation of these peripherals are ADCA and ADCB, respectively. 42 8067L–AVR–08/10 XMEGA A1 25. DAC - 12-bit Digital to Analog Converter 25.1 Features • • • • • • • • Two DACs with 12-bit resolution Up to 1 Msps conversion rate for each DAC Flexible conversion range Multiple trigger sources 1 continuous output or 2 Sample and Hold (S/H) outputs for each DAC Built-in offset and gain calibration High drive capabilities Low Power Mode 25.2 Overview The XMEGA A1 devices features two 12-bit, 1 Msps DACs with built-in offset and gain calibration, see Figure 25-1 on page 43. A DAC converts a digital value into an analog signal. The DAC may use an internal 1.0 voltage as the upper limit for conversion, but it is also possible to use the supply voltage or any applied voltage in-between. The external reference input is shared with the ADC reference input. Figure 25-1. DAC overview Configuration Reference selection Channel A Register Channel A DAC Channel B Register Channel B Event Trigger Each DAC has one continuous output with high drive capabilities for both resistive and capacitive loads. It is also possible to split the continuous time channel into two Sample and Hold (S/H) channels, each with separate data conversion registers. A DAC conversion may be started from the application software by writing the data conversion registers. The DAC can also be configured to do conversions triggered by the Event System to have regular timing, independent of the application software. DMA may be used for transferring data from memory locations to DAC data registers. The DAC has a built-in calibration system to reduce offset and gain error when loading with a calibration value from software. PORTA and PORTB each has one DAC. Notation of these peripherals are DACA and DACB. respectively. 43 8067L–AVR–08/10 XMEGA A1 26. AC - Analog Comparator 26.1 Features • Four Analog Comparators • Selectable Power vs. Speed • Selectable hysteresis – 0, 20 mV, 50 mV • Analog Comparator output available on pin • Flexible Input Selection – All pins on the port – Output from the DAC – Bandgap reference voltage. – Voltage scaler that can perform a 64-level scaling of the internal VCC voltage. • Interrupt and event generation on – Rising edge – Falling edge – Toggle • Window function interrupt and event generation on – Signal above window – Signal inside window – Signal below window 26.2 Overview XMEGA A1 features four Analog Comparators (AC). An Analog Comparator compares two voltages, and the output indicates which input is largest. The Analog Comparator may be configured to give interrupt requests and/or events upon several different combinations of input change. Both hysteresis and propagation delays may be adjusted in order to find the optimal operation for each application. A wide range of input selection is available, both external pins and several internal signals can be used. The Analog Comparators are always grouped in pairs (AC0 and AC1) on each analog port. They have identical behavior but separate control registers. Optionally, the state of the comparator is directly available on a pin. PORTA and PORTB each has one AC pair. Notations are ACA and ACB, respectively. 44 8067L–AVR–08/10 XMEGA A1 Figure 26-1. Analog comparator overview Pin inputs Internal inputs + AC0 Pin inputs Internal inputs VCC scaled Interrupt sensitivity control Interrupts Events Pin 0 output Pin inputs Internal inputs + AC1 Pin inputs Internal inputs VCC scaled - 45 8067L–AVR–08/10 XMEGA A1 26.3 Input Selection The Analog comparators have a very flexible input selection and the two comparators grouped in a pair may be used to realize a window function. One pair of analog comparators is shown in Figure 26-1 on page 45. • Input selection from pin – Pin 0, 1, 2, 3, 4, 5, 6 selectable to positive input of analog comparator – Pin 0, 1, 3, 5, 7 selectable to negative input of analog comparator • Internal signals available on positive analog comparator inputs – Output from 12-bit DAC • Internal signals available on negative analog comparator inputs – 64-level scaler of the VCC, available on negative analog comparator input – Bandgap voltage reference – Output from 12-bit DAC 26.4 Window Function The window function is realized by connecting the external inputs of the two analog comparators in a pair as shown in Figure 26-2. Figure 26-2. Analog comparator window function + AC0 Upper limit of window Input signal Interrupt sensitivity control + AC1 Lower limit of window Interrupts Events 46 8067L–AVR–08/10 XMEGA A1 27. OCD - On-chip Debug 27.1 Features • Complete Program Flow Control – Go, Stop, Reset, Step into, Step over, Step out, Run-to-Cursor Debugging on C and high-level language source code level Debugging on Assembler and disassembler level 1 dedicated program address or source level breakpoint for AVR Studio / debugger 4 Hardware Breakpoints Unlimited Number of User Program Breakpoints Unlimited Number of User Data Breakpoints, with break on: – Data location read, write or both read and write – Data location content equal or not equal to a value – Data location content is greater or less than a value – Data location content is within or outside a range – Bits of a data location are equal or not equal to a value • Non-Intrusive Operation – No hardware or software resources in the device are used • High Speed Operation – No limitation on debug/programming clock frequency versus system clock frequency • • • • • • 27.2 Overview The XMEGA A1 has a powerful On-Chip Debug (OCD) system that - in combination with Atmel’s development tools - provides all the necessary functions to debug an application. It has support for program and data breakpoints, and can debug an application from C and high level language source code level, as well as assembler and disassembler level. It has full Non-Intrusive Operation and no hardware or software resources in the device are used. The ODC system is accessed through an external debugging tool which connects to the JTAG or PDI physical interfaces. Refer to “PDI - Program and Debug Interface” on page 48. 47 8067L–AVR–08/10 XMEGA A1 28. PDI - Program and Debug Interface 28.1 Features • • • • • PDI - Program and Debug Interface (Atmel proprietary 2-pin interface) JTAG Interface (IEEE std. 1149.1 compliant) Boundary-scan capabilities according to the IEEE Std. 1149.1 (JTAG) Access to the OCD system Programming of Flash, EEPROM, Fuses and Lock Bits 28.2 Overview The programming and debug facilities are accessed through the JTAG and PDI physical interfaces. The PDI physical interface uses one dedicated pin together with the Reset pin, and no general purpose pins are used. JTAG uses four general purpose pins on PORTB. The PDI is an Atmel proprietary protocol for communication between the microcontroller and Atmel’s or third party development tools. 28.3 IEEE 1149.1 (JTAG) Boundary-scan The JTAG physical layer handles the basic low-level serial communication over four I/O lines named TMS, TCK, TDI, and TDO. It complies to the IEEE Std. 1149.1 for test access port and boundary scan. 28.3.1 Boundary-scan Order Table 29-12 on page 55 shows the Scan order between TDI and TDO when the Boundary-scan chain is selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit scanned out. The scan order follows the pin-out order. Bit 4, 5, 6 and 7 of Port B is not in the scan chain, since these pins constitute the TAP pins when the JTAG is enabled. 28.3.2 Boundary-scan Description Language Files Boundary-scan Description Language (BSDL) files describe Boundary-scan capable devices in a standard format used by automated test-generation software. The order and function of bits in the Boundary-scan Data Register are included in this description. BSDL files are available for ATxmega384/256/192/128/64A1 devices. See Table 29-12 on page 55 for ATxmega384/256/192/128/64A1 Boundary Scan Order. 48 8067L–AVR–08/10 XMEGA A1 29. Pinout and Pin Functions The pinout of XMEGA A1 is shown in “Pinout/Block Diagram” on page 3. In addition to general I/O functionality, each pin may have several functions. This will depend on which peripheral is enabled and connected to the actual pin. Only one of the alternate pin functions can be used at time. 29.1 Alternate Pin Function Description The tables below shows the notation for all pin functions available and describes its function. 29.1.1 Operation/Power Supply VCC AVCC GND Digital supply voltage Analog supply voltage Ground 29.1.2 Port Interrupt functions SYNC ASYNC Port pin with full synchronous and limited asynchronous interrupt function Port pin with full synchronous and full asynchronous interrupt function 29.1.3 Analog functions ACn AC0OUT ADCn DACn AREF Analog Comparator input pin n Analog Comparator 0 Output Analog to Digital Converter input pin n Digital to Analog Converter output pin n Analog Reference input pin 29.1.4 EBI functions An Dn CSn ALEn RE WE BAn CAS CKE CLK DQM Address line n Data line n Chip Select n Address Latch Enable pin n Read Enable External Data Memory Write Bank Address Column Access Strobe SDRAM Clock Enable SDRAM Clock Data Mask Signal/Output Enable (SRAM) (SRAM) (SRAM /SDRAM) (SDRAM) (SDRAM) (SDRAM) (SDRAM) (SDRAM) 49 8067L–AVR–08/10 XMEGA A1 RAS 2P 3P Row Access Strobe 2 Port Interface 3 Port Interface (SDRAM) 29.1.5 Timer/Counter and AWEX functions OCnx OCnx OCnxLS OCnxHS Output Compare Channel x for Timer/Counter n Inverted Output Compare Channel x for Timer/Counter n Output Compare Channel x Low Side for Timer/Counter n Output Compare Channel x High Side for Timer/Counter n 29.1.6 Communication functions SCL SDA SCLIN SCLOUT SDAIN SDAOUT XCKn RXDn TXDn SS MOSI MISO SCK Serial Clock for TWI Serial Data for TWI Serial Clock In for TWI when external driver interface is enabled Serial Clock Out for TWI when external driver interface is enabled Serial Data In for TWI when external driver interface is enabled Serial Data Out for TWI when external driver interface is enabled Transfer Clock for USART n Receiver Data for USART n Transmitter Data for USART n Slave Select for SPI Master Out Slave In for SPI Master In Slave Out for SPI Serial Clock for SPI 29.1.7 Oscillators, Clock and Event TOSCn XTALn CLKOUT EVOUT Timer Oscillator pin n Input/Output for inverting Oscillator pin n Peripheral Clock Output Event Channel 0 Output 29.1.8 Debug/System functions RESET PDI_CLK PDI_DATA TCK Reset pin Program and Debug Interface Clock pin Program and Debug Interface Data pin JTAG Test Clock 50 8067L–AVR–08/10 XMEGA A1 TDI TDO TMS JTAG Test Data In JTAG Test Data Out JTAG Test Mode Select 29.2 Alternate Pin Functions The tables below show the primary/default function for each pin on a port in the first column, the pin number in the second column, and then all alternate pin functions in the remaining columns. The head row shows what peripheral that enable and use the alternate pin functions. Table 29-1. PORT A PIN # Port A - Alternate functions INTERRUPT ADCA POS ADCA NEG ADCA GAINPOS ADCA GAINNEG ACA POS ACA NEG ACA OUT DACA REFA GND AVCC PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 93 94 95 96 97 98 99 100 1 2 SYNC SYNC SYNC/ASYNC SYNC SYNC SYNC SYNC SYNC ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 ADC0 ADC1 ADC2 ADC3 ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 ADC4 ADC5 ADC6 ADC7 AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC0OUT AC5 AC3 AC0 AC1 DAC0 DAC1 AREF Table 29-2. PORT B PIN # Port B - Alternate functions INTERRUPT ADCB POS ADCB NEG ADCB GAINPOS ADCB GAINNEG ACB POS ACB NEG ACB OUT DACB REFB JTAG GND AVCC PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 3 4 5 6 7 8 9 10 11 12 SYNC SYNC SYNC/ASYNC SYNC SYNC SYNC SYNC SYNC ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 ADC0 ADC1 ADC2 ADC3 ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 ADC4 ADC5 ADC6 ADC7 AC0 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC0OUT AC5 AC3 AC0 AC1 DAC0 DAC1 TMS TDI TCK TDO AREF 51 8067L–AVR–08/10 XMEGA A1 Table 29-3. PORT C GND VCC PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PIN # 13 14 15 16 17 18 19 20 21 22 SYNC SYNC SYNC/ASYNC SYNC SYNC SYNC SYNC SYNC OC0A OC0B OC0C OC0D OC0ALS OC0AHS OC0BLS OC0BHS OC0CLS OC0CHS OC0DLS OC0DHS OC1A OC1B XCK1 RXD1 TXD1 XCK0 RXD0 TXD0 SS MOSI MISO SCK CLKOUT EVOUT SDA SCL Port C - Alternate functions INTERRUPT TCC0 AWEXC TCC1 USARTC0 USARTC1 SPIC TWIC CLOCKOUT EVENTOUT Table 29-4. PORT D GND VCC PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PIN # 23 24 25 26 27 28 29 30 31 32 Port D - Alternate functions INTERRUPT TCD0 TCD1 USARTD0 USARTD1 SPID TWID CLOCKOUT EVENTOUT SYNC SYNC SYNC/ASYNC SYNC SYNC SYNC SYNC SYNC OC0A OC0B OC0C OC0D OC1A OC1B XCK1 RXD1 TXD1 XCK0 RXD0 TXD0 SS MOSI MISO SCK SDA SCL CLKOUT EVOUT Table 29-5. PORT E GND VCC PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 PIN # 33 34 35 36 37 38 39 40 41 42 Port E - Alternate functions INTERRUPT TCE0 AWEXE TCE1 USARTE0 USARTE1 SPIE TWIE CLOCKOUT EVENTOUT SYNC SYNC SYNC/ASYNC SYNC SYNC SYNC SYNC SYNC OC0A OC0B OC0C OC0D OC0ALS OC0AHS OC0BLS OC0BHS OC0CLS OC0CHS OC0DLS OC0DHS OC1A OC1B XCK1 RXD1 TXD1 XCK0 RXD0 TXD0 SS MOSI MISO SCK SDA SCL CLKOUT EVOUT 52 8067L–AVR–08/10 XMEGA A1 Table 29-6. PORT F GND VCC PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 PIN # 43 44 45 46 47 48 49 50 51 52 Port F - Alternate functions INTERRUPT TCF0 TCF1 USARTF0 USARTF1 SPIF TWIF SYNC SYNC SYNC/ASYNC SYNC SYNC SYNC SYNC SYNC OC0A OC0B OC0C OC0D OC1A OC1B XCK1 RXD1 TXD1 XCK0 RXD0 TXD0 SS MOSI MISO SCK SDA SCL Table 29-7. PORT H GND VCC PH0 PH1 PH2 PH3 PH4 PH5 PH6 PH7 PIN # 53 54 55 56 57 58 59 60 61 62 Port H - Alternate functions INTERRUPT SDRAM 3P SRAM ALE1 3P SRAM ALE12 3P LPC ALE1 3P LPC ALE1 2P LPC ALE12 2P SYNC SYNC SYNC/ASYNC SYNC SYNC SYNC SYNC SYNC WE CAS RAS DQM BA0 BA1 CKE CLK WE RE ALE1 WE RE ALE1 ALE2 WE RE ALE1 WE RE ALE1 WE RE ALE1 ALE2 CS0/A16 CS1/A17 CS2/A18 CS3/A19 CS0 CS1 CS2 CS3 CS0/A16 CS1/A17 CS2/A18 CS3/A19 CS0 CS1 CS2 CS3 CS0/A16 CS1/A17 CS2/A18 CS3/A19 Table 29-8. PORT J GND VCC PJ0 PJ1 PJ2 PJ3 PJ4 PJ5 PJ6 PJ7 PIN # 63 64 65 66 67 68 69 70 71 72 Port J - Alternate functions INTERRUPT SDRAM 3P SRAM ALE1 3P SRAM ALE12 3P LPC ALE1 3P LPC ALE1 2P LPC ALE12 2P SYNC SYNC SYNC/ASYNC SYNC SYNC SYNC SYNC SYNC D0 D1 D2 D3 A8 A9 A10 A11 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0/A0 D1/A1 D2/A2 D3/A3 D4/A4 D5/A5 D6/A6 D7/A7 D0/A0 D1/A1 D2/A2 D3/A3 D4/A4 D5/A5 D6/A6 D7/A7 D0/A0/A8 D1/A1/A9 D2/A2/A10 D3/A3/A11 D4/A4/A12 D5/A5/A13 D6/A6/A14 D7/A7/A15 53 8067L–AVR–08/10 XMEGA A1 Table 29-9. PORT K GND VCC PK0 PK1 PK2 PK3 PK4 PK5 PK6 PK7 PIN # 73 74 75 76 77 78 79 80 81 82 Port K - Alternate functions INTERRUPT SDRAM 3P SRAM ALE1 3P SRAM ALE12 3P LPC ALE1 3P LPC ALE1 2P LPC ALE12 2P SYNC SYNC SYNC/ASYNC SYNC SYNC SYNC SYNC SYNC A0 A1 A2 A3 A4 A5 A6 A7 A0/A8 A1/A9 A2/A10 A3/A11 A4/A12 A5/A13 A6/A14 A7/A15 A0/A8/A16 A1/A9/A17 A2/A10/A18 A3/A11/A19 A4/A12/A20 A5/A13/A21 A6/A14/A22 A7/A15/A23 A8 A9 A10 A11 A12 A13 A14 A15 Table 29-10. Port Q - Alternate functions PORT Q VCC GND PQ0 PQ1 PQ2 PQ3 PIN # 83 84 85 86 87 88 SYNC SYNC SYNC/ASYNC SYNC TOSC1 TOSC2 INTERRUPT TOSC Table 29-11. Port R- Alternate functions PORT R PDI RESET PRO PR1 PIN # 89 90 91 92 SYNC SYNC INTERRUPT PDI PDI_DATA PDI_CLOCK XTAL2 XTAL1 XTAL 54 8067L–AVR–08/10 XMEGA A1 Table 29-12. ATxmega384/256/192/128/64A1 Boundary Scan Order Bit Number 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 Signal Name PQ3.Bidir PQ3.Control PQ2.Bidir PQ2.Control PQ1.Bidir PQ1.Control PQ0.Bidir PQ0.Control PK7.Bidir PK7.Control PK6.Bidir PK6.Control PK5.Bidir PK5.Control PK4.Bidir PK4.Control PK3.Bidir PK3.Control PK2.Bidir PK2.Control PK1.Bidir PK1.Control PK0.Bidir PK0.Control PJ7.Bidir PJ7.Control PJ6.Bidir PJ6.Control PJ5.Bidir PJ5.Control PJ4.Bidir PJ4.Control PJ3.Bidir PJ3.Control PJ2.Bidir PJ2.Control PJ1.Bidir PJ1.Control PJ0.Bidir PJ0.Control PH7.Bidir PH7.Control PH6.Bidir PH6.Control PH5.Bidir PH5.Control PH4.Bidir PH4.Control PH3.Bidir PH3.Control PH2.Bidir PH2.Control PH1.Bidir PH1.Control PH0.Bidir PH0.Control Module PORT Q PORT K PORT J PORT H 55 8067L–AVR–08/10 XMEGA A1 Bit Number 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 Signal Name PF7.Bidir PF7.Control PF6.Bidir PF6.Control PF5.Bidir PF5.Control PF4.Bidir PF4.Control PF3.Bidir PF3.Control PF2.Bidir PF2.Control PF1.Bidir PF1.Control PF0.Bidir PF0.Control PE7.Bidir PE7.Control PE6.Bidir PE6.Control PE5.Bidir PE5.Control PE4.Bidir PE4.Control PE3.Bidir PE3.Control PE2.Bidir PE2.Control PE1.Bidir PE1.Control PE0.Bidir PE0.Control PD7.Bidir PD7.Control PD6.Bidir PD6.Control PD5.Bidir PD5.Control PD4.Bidir PD4.Control PD3.Bidir PD3.Control PD2.Bidir PD2.Control PD1.Bidir PD1.Control PD0.Bidir PD0.Control PC7.Bidir PC7.Control PC6.Bidir PC6.Control PC5.Bidir PC5.Control PC4.Bidir PC4.Control PC3.Bidir PC3.Control PC2.Bidir PC2.Control PC1.Bidir PC1.Control PC0.Bidir PC0.Control Module PORT F PORT E PORT D PORT C 56 8067L–AVR–08/10 XMEGA A1 Bit Number 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Signal Name PB3.Bidir PB3.Control PB2.Bidir PB2.Control PB1.Bidir PB1.Control PB0.Bidir PB0.Control PA7.Bidir PA7.Control PA6.Bidir PA6.Control PA5.Bidir PA5.Control PA4.Bidir PA4.Control PA3.Bidir PA3.Control PA2.Bidir PA2.Control PA1.Bidir PA1.Control PA0.Bidir PA0.Control PR1.Bidir PR1.Control PR0.Bidir PR0.Control RESET.Observe_Only PDI_DATA.Observe_Only Module PORT B PORT A PORT R RESET PDI Data 57 8067L–AVR–08/10 XMEGA A1 30. Peripheral Module Address Map The address maps show the base address for each peripheral and module in XMEGA A1. For complete register description and summary for each peripheral module, refer to the XMEGA A Manual. Table 30-1. Base Address 0x0000 0x0010 0x0014 0x0018 0x001C 0x0030 0x0040 0x0048 0x0050 0x0060 0x0068 0x0070 0x0078 0x0080 0x0090 0x00A0 0x00B0 0x00C0 0x0100 0x0180 0x01C0 0x0200 0x0240 0x0300 0x0320 0x0380 0x0390 0x0400 0x0440 0x0480 0x0490 0x04A0 0x04B0 0x0600 0x0620 0x0640 0x0660 0x0680 0x06A0 0x06E0 0x0700 0x0720 0x07C0 0x07E0 0x0800 0x0840 0x0880 0x0890 0x08A0 0x08B0 0x08C0 0x08F8 0x0900 0x0940 0x0990 0x09A0 0x09B0 Peripheral Module Address Map Name GPIO VPORT0 VPORT1 VPORT2 VPORT3 CPU CLK SLEEP OSC DFLLRC32M DFLLRC2M PR RST WDT MCU PMIC PORTCFG AES DMA EVSYS NVM ADCA ADCB DACA DACB ACA ACB RTC EBI TWIC TWID TWIE TWIF PORTA PORTB PORTC PORTD PORTE PORTF PORTH PORTJ PORTK PORTQ PORTR TCC0 TCC1 AWEXC HIRESC USARTC0 USARTC1 SPIC IRCOM TCD0 TCD1 HIRESD USARTD0 USARTD1 Description General Purpose IO Registers Virtual Port 0 Virtual Port 1 Virtual Port 2 Virtual Port 3 CPU Clock Control Sleep Controller Oscillator Control DFLL for the 32 MHz Internal RC Oscillator DFLL for the 2 MHz RC Oscillator Power Reduction Reset Controller Watch-Dog Timer MCU Control Programmable Multilevel Interrupt Controller Port Configuration AES Module DMA Controller Event System Non Volatile Memory (NVM) Controller Analog to Digital Converter on port A Analog to Digital Converter on port B Digital to Analog Converter on port A Digital to Analog Converter on port B Analog Comparator pair on port A Analog Comparator pair on port B Real Time Counter External Bus Interface Two Wire Interface on port C Two Wire Interface on port D Two Wire Interface on port E Two Wire Interface on port F Port A Port B Port C Port D Port E Port F Port H Port J Port K Port Q Port R Timer/Counter 0 on port C Timer/Counter 1 on port C Advanced Waveform Extension on port C High Resolution Extension on port C USART 0 on port C USART 1 on port C Serial Peripheral Interface on port C Infrared Communication Module Timer/Counter 0 on port D Timer/Counter 1 on port D High Resolution Extension on port D USART 0 on port D USART 1 on port D 58 8067L–AVR–08/10 XMEGA A1 Base Address 0x09C0 0x0A00 0x0A40 0x0A80 0x0A90 0x0AA0 0x0AB0 0x0AC0 0x0B00 0x0B40 0x0B90 0x0BA0 0x0BB0 0x0BC0 Name SPID TCE0 TCE1 AWEXE HIRESE USARTE0 USARTE1 SPIE TCF0 TCF1 HIRESF USARTF0 USARTF1 SPIF Description Serial Peripheral Interface on port D Timer/Counter 0 on port E Timer/Counter 1 on port E Advanced Waveform Extension on port E High Resolution Extension on port E USART 0 on port E USART 1 on port E Serial Peripheral Interface on port E Timer/Counter 0 on port F Timer/Counter 1 on port F High Resolution Extension on port F USART 0 on port F USART 1 on port F Serial Peripheral Interface on port F 59 8067L–AVR–08/10 XMEGA A1 31. Instruction Set Summary Mnemonics Operands Description Arithmetic and Logic Instructions ADD ADC ADIW SUB SUBI SBC SBCI SBIW AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER MUL MULS MULSU FMUL FMULS FMULSU DES Rd, Rr Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd, K Rd, K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd Rd Rd,K Rd,K Rd Rd Rd Rd Rd Rd,Rr Rd,Rr Rd,Rr Rd,Rr Rd,Rr Rd,Rr K Add without Carry Add with Carry Add Immediate to Word Subtract without Carry Subtract Immediate Subtract with Carry Subtract Immediate with Carry Subtract Immediate from Word Logical AND Logical AND with Immediate Logical OR Logical OR with Immediate Exclusive OR One’s Complement Two’s Complement Set Bit(s) in Register Clear Bit(s) in Register Increment Decrement Test for Zero or Minus Clear Register Set Register Multiply Unsigned Multiply Signed Multiply Signed with Unsigned Fractional Multiply Unsigned Fractional Multiply Signed Fractional Multiply Signed with Unsigned Data Encryption Rd Rd Rd Rd Rd Rd Rd Rd + 1:Rd Rd Rd Rd Rd Rd Rd Rd Rd Rd Rd Rd Rd Rd Rd R1:R0 R1:R0 R1:R0 R1:R0 R1:R0 R1:R0 if (H = 0) then R15:R0 else if (H = 1) then R15:R0 Branch Instructions RJMP IJMP EIJMP JMP RCALL ICALL EICALL k k k Relative Jump Indirect Jump to (Z) Extended Indirect Jump to (Z) Jump Relative Call Subroutine Indirect Call to (Z) Extended Indirect Call to (Z) PC PC(15:0) PC(21:16) PC(15:0) PC(21:16) PC PC PC(15:0) PC(21:16) PC(15:0) PC(21:16) ← ← ← ← ← ← ← ← ← ← ← PC + k + 1 Z, 0 Z, EIND k PC + k + 1 Z, 0 Z, EIND None None None None None None None 2 2 2 3 2 / 3(1) 2 / 3(1) 3(1) ← ← ← ← ← ← ← ← ← ← ← ← ← ← ← ← ← ← ← ← ← ← ← ← ← ← ← ← ← ← Rd + Rr Rd + Rr + C Rd + 1:Rd + K Rd - Rr Rd - K Rd - Rr - C Rd - K - C Rd + 1:Rd - K Rd • Rr Rd • K Rd v Rr Rd v K Rd ⊕ Rr $FF - Rd $00 - Rd Rd v K Rd • ($FFh - K) Rd + 1 Rd - 1 Rd • Rd Rd ⊕ Rd $FF Rd x Rr (UU) Rd x Rr (SS) Rd x Rr (SU) Rd x Rr