ATtiny48-MUR

Features • High Performance, Low Power AVR® 8-Bit Microcontroller • Advanced RISC Architecture – 123 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation High Endurance Non-volatile Memory Segments – 4K/8K Bytes of In-System Self-Programmable Flash Program Memory – 64/64 Bytes EEPROM – 256/512 Bytes Internal SRAM – Write/Erase Cycles: 10,000 Flash/100,000 EEPROM – Data Retention: 20 years at 85°C / 100 years at 25°C – Programming Lock for Software Security Peripheral Features – One 8-bit Timer/Counter with Separate Prescaler and Compare Mode – One 16-bit Timer/Counter with Prescaler, and Compare and Capture Modes – 6- or 8-channel 10-bit ADC – Master/Slave SPI Serial Interface – Byte-oriented 2-wire Serial Interface (Philips I2C Compatible) – Programmable Watchdog Timer with Separate On-Chip Oscillator – On-Chip Analog Comparator – Interrupt and Wake-up on Pin Change Special Microcontroller Features – debugWIRE On-Chip Debug System – In-System Programmable via SPI Port – Power-On Reset and Programmable Brown-Out Detection – Internal Calibrated Oscillator – External and Internal Interrupt Sources – Three Sleep Modes: Idle, ADC Noise Reduction and Power-Down – On-Chip Temperature Sensor I/O and Packages – 24 Programmable I/O Lines: • 28-pin PDIP • 28-pad QFN/MLF – 28 Programmable I/O Lines: • 32-lead TQFP • 32-pad QFN/MLF • 32-ball UFBGA Operating Voltage: – 1.8 – 5.5V Temperature Range: – -40°C to +85°C Speed Grade: – 0 – 4 MHz @ 1.8 – 5.5V – 0 – 8 MHz @ 2.7 – 5.5V – 0 – 12 MHz @ 4.5 – 5.5V Low Power Consumption – Active Mode: 1 MHz, 1.8V: 240 µA – Power-Down Mode: 0.1 µA at 1.8V • • 8-bit Microcontroller with 4/8K Bytes In-System Programmable Flash ATtiny48/88 Preliminary Summary • • • • • • Rev. 8008FS–AVR–06/10 1. Pin Configurations Figure 1-1. Pinout of ATtiny48/88 TQFP Top View PD2 (INT0/PCINT18) PD1 (PCINT17) PD0 (PCINT16) PC6 (RESET/PCINT14) PC5 (ADC5/SCL/PCINT13) PC4 (ADC4/SDA/PCINT12) PC3 (ADC3/PCINT11) PC2 (ADC2/PCINT10) PDIP (PCINT14/RESET) PC6 (PCINT16) PD0 (PCINT17) PD1 (PCINT18/INT0) PD2 (PCINT19/INT1) PD3 (PCINT20/T0) PD4 VCC GND (PCINT6/CLKI) PB6 (PCINT7) PB7 (PCINT21/T1) PD5 (PCINT22/AIN0) PD6 (PCINT23/AIN1) PD7 (PCINT0/CLKO/ICP1) PB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PC5 (ADC5/SCL/PCINT13) PC4 (ADC4/SDA/PCINT12) PC3 (ADC3/PCINT11) PC2 (ADC2/PCINT10) PC1 (ADC1/PCINT9) PC0 (ADC0/PCINT8) GND PC7 (PCINT15) AVCC PB5 (SCK/PCINT5) PB4 (MISO/PCINT4) PB3 (MOSI/PCINT3) PB2 (SS/OC1B/PCINT2) PB1 (OC1A/PCINT1) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 (PCINT19/INT1) PD3 (PCINT20/T0) PD4 (PCINT26) PA2 VCC GND (PCINT27) PA3 (PCINT6/CLKI) PB6 (PCINT7) PB7 1 2 3 4 5 6 7 8 PC1 (ADC1/PCINT9) PC0 (ADC0/PCINT8) PA1 (ADC7/PCINT25) GND PC7 (PCINT15) PA0 (ADC6/PCINT24) AVCC PB5 (SCK/PCINT5) (PCINT21/T1) PD5 (PCINT22/AIN0) PD6 (PCINT23/AIN1) PD7 (PCINT0/CLKO/ICP1) PB0 (PCINT1/OC1A) PB1 (PCINT2/SS/OC1B) PB2 (PCINT3/MOSI) PB3 (PCINT4/MISO) PB4 32 MLF Top View PD2 (INT0/PCINT18) PD1 (PCINT17) PD0 (PCINT16) PC6 (RESET/PCINT14) PC5 (ADC5/SCL/PCINT13) PC4 (ADC4/SDA/PCINT12) PC3 (ADC3/PCINT11) 28 27 26 25 24 23 22 32 31 30 29 28 27 26 25 PD2 (INT0/PCINT18) PD1 (PCINT17) PD0 (PCINT16) PC6 (RESET/PCINT14) PC5 (ADC5/SCL/PCINT13) PC4 (ADC4/SDA/PCINT12) PC3 (ADC3/PCINT11) PC2 (ADC2/PCINT10) 28 MLF Top View (PCINT19/INT1) PD3 (PCINT20/T0) PD4 VCC GND (PCINT6/CLKI) PB6 (PCINT7) PB7 (PCINT21/T1) PD5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 21 20 19 18 17 16 15 PC2 (ADC2/PCINT10) PC1 (ADC1/PCINT9) PC0 (ADC0/PCINT8) GND PC7 (PCI NT15) AVCC PB5 (SCK/PCINT5) (PCINT19/INT1) PD3 (PCINT20/T0) PD4 (PCINT26) PA2 VCC GND (PCINT27) PA3 (PCINT6/CLKI) PB6 (PCINT7) PB7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 PC1 (ADC1/PCINT9) PC0 (ADC0/PCINT8) PA1 (ADC7/PCINT25) GND PC7 (PCINT15) PA0 (ADC6/PCINT24) AVCC PB5 (SCK/PCINT5) (PCINT22/AIN0) PD6 (PCINT23/AIN1) PD7 (PCINT0/CLKO/ICP1) PB0 (PCINT1/OC1A) PB1 (PCINT2/SS/OC1B) PB2 (PCINT3//MOSI) PB3 (PCINT4/MISO) PB4 NOTE: Bottom pad should be soldered to ground. NOTE: Bottom pad should be soldered to ground. Table 1-1. 1 A B C D E F 32UFBGA - Pinout ATtiny48/88 2 PD1 PD4 PA2 PA3 PD6 PD5 PB0 PD7 PB2 PB1 3 PC6 PD0 4 PC4 PC5 5 PC2 PC3 PA1 PC7 AVDD PB3 6 PC1 PC0 GND PA0 PB5 PB4 PD2 PD3 GND VDD PB6 PB7 2 ATtiny48/88 8008F–AVR–06/10 (PCINT21/T1) PD5 (PCINT22/AIN0) PD6 (PCINT23/AIN1) PD7 (PCINT0/CLKO/ICP1) PB0 (PCINT1/OC1A) PB1 (PCINT2/SS/OC1B) PB2 (PCINT3/MOSI) PB3 (PCINT4/MISO) PB4 ATtiny48/88 1.1 1.1.1 Pin Descriptions VCC Digital supply voltage. 1.1.2 GND Ground. 1.1.3 Port A (PA3:0) (in 32-lead TQFP and 32-pad QFN/MLF packages, only) Port A is a 4-bit bi-directional I/O port with internal pull-up resistors (selected for each bit) in 32lead TQFP and 32-pad QFN/MLF package. The PA[3:0] output buffers have symmetrical drive characteristics with both sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B (PB7:0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Depending on the clock selection fuse settings, PB6 can be used as input to the internal clock operating circuit. The various special features of Port B are elaborated in “Alternate Functions of Port B” on page 67 and “System Clock and Clock Options” on page 25. 1.1.4 1.1.5 Port C (PC7, PC5:0) Port C is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The PC7 and PC[5:0] output buffers have symmetrical drive characteristics with both sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. PC6/RESET If the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that the electrical characteristics of PC6 differ from those of the other pins of Port C. If the RSTDISBL Fuse is unprogrammed, PC6 is used as a reset input. A low level on this pin for longer than the minimum pulse width will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 21-3 on page 207. Shorter pulses are not guaranteed to generate a reset. The various special features of Port C are elaborated in “Alternate Functions of Port C” on page 70. 1.1.6 1.1.7 Port D (PD7:0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The PD[7:4] output buffers have symmetrical drive characteristics with both sink and source capabilities, while the PD[3:0] output buffers have high sink capabilities. As inputs, Port D pins that are 3 8008F–AVR–06/10 externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. The various special features of Port D are elaborated in “Alternate Functions of Port D” on page 73. 1.1.8 AVCC AVCC is the supply voltage pin for the A/D converter and a selection of I/O pins. This pin should be externally connected to VCC even if the ADC is not used. If the ADC is used, it is recommended this pin is connected to VCC through a low-pass filter, as described in “Analog Noise Canceling Techniques” on page 169. The following pins receive their supply voltage from AVCC: PC7, PC[5:0] and (in 32-lead packages) PA[1:0]. All other I/O pins take their supply voltage from VCC. 4 ATtiny48/88 8008F–AVR–06/10 ATtiny48/88 2. Overview The ATtiny48/88 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny48/88 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Figure 2-1. Block Diagram GND VCC Watchdog Timer Watchdog Oscillator Power Supervision POR / BOD & RESET debugWIRE Program Logic Oscillator Circuits / Clock Generation Flash SRAM CPU EEPROM 8bit T/C 0 16bit T/C 1 A/D Conv. 2 DATABUS 6 Internal Bandgap Analog Comp. SPI TWI PORT D (8) PORT B (8) PORT C (8) PORT A (4) RESET CLKI PD[0:7] PB[0:7] PC[0:7] PA[0:3] (in TQFP and MLF) The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. 5 8008F–AVR–06/10 The ATtiny48/88 provides the following features: 4/8K bytes of In-System Programmable Flash, 64/64 bytes EEPROM, 256/512 bytes SRAM, 24 general purpose I/O lines (28 I/Os in 32-lead TQFP and 32-pad QFN/MLF packages), 32 general purpose working registers, two flexible Timer/Counters with compare modes, internal and external interrupts, a byte-oriented 2-wire serial interface, an SPI serial port, a 6-channel 10-bit ADC (8 channels in 32-lead TQFP and 32pad QFN/MLF packages), a programmable Watchdog Timer with internal oscillator, and three software selectable power saving modes. Idle mode stops the CPU while allowing Timer/Counters, 2-wire serial interface, SPI port, and interrupt system to continue functioning. Power-down mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset. ADC Noise Reduction mode stops the CPU and all I/O modules except ADC, and helps to minimize switching noise during ADC conversions. The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, by a conventional non-volatile memory programmer, or by an on-chip boot program running on the AVR core. The boot program can use any interface to download the application program in the Flash memory. By combining an 8-bit RISC CPU with In-System SelfProgrammable Flash on a monolithic chip, the Atmel ATtiny48/88 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATtiny48/88 AVR is supported by a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators and evaluation kits. 2.2 Comparison Between ATtiny48 and ATtiny88 The ATtiny48 and ATtiny88 differ only in memory sizes. Table 2-1 summarizes the different memory sizes for the two devices. Table 2-1. Device ATtiny48 ATtiny88 Memory Size Summary Flash 4K Bytes 8K Bytes EEPROM 64 Bytes 64 Bytes RAM 256 Bytes 512 Bytes 6 ATtiny48/88 8008F–AVR–06/10 ATtiny48/88 3. General Information 3.1 Resources A comprehensive set of development tools, application notes and datasheets are available for download at http://www.atmel.com/avr. 3.2 About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details. For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. 3.3 Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. 3.4 Disclaimer Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized. 7 8008F–AVR–06/10 4. Register Summary Address (0xFF) (0xFE) (0xFD) (0xFC) (0xFB) (0xFA) (0xF9) (0xF8) (0xF7) (0xF6) (0xF5) (0xF4) (0xF3) (0xF2) (0xF1) (0xF0) (0xEF) (0xEE) (0xED) (0xEC) (0xEB) (0xEA) (0xE9) (0xE8) (0xE7) (0xE6) (0xE5) (0xE4) (0xE3) (0xE2) (0xE1) (0xE0) (0xDF) (0xDE) (0xDD) (0xDC) (0xDB) (0xDA) (0xD9) (0xD8) (0xD7) (0xD6) (0xD5) (0xD4) (0xD3) (0xD2) (0xD1) (0xD0) (0xCF) (0xCE) (0xCD) (0xCC) (0xCB) (0xCA) (0xC9) (0xC8) (0xC7) (0xC6) (0xC5) (0xC4) (0xC3) (0xC2) (0xC1) (0xC0) (0xBF) Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Bit 7 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Bit 6 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Bit 5 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Bit 4 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Bit 3 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Bit 2 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Bit 1 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Bit 0 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Page 8 ATtiny48/88 8008F–AVR–06/10 ATtiny48/88 Address (0xBE) (0xBD) (0xBC) (0xBB) (0xBA) (0xB9) (0xB8) (0xB7) (0xB6) (0xB5) (0xB4) (0xB3) (0xB2) (0xB1) (0xB0) (0xAF) (0xAE) (0xAD) (0xAC) (0xAB) (0xAA) (0xA9) (0xA8) (0xA7) (0xA6) (0xA5) (0xA4) (0xA3) (0xA2) (0xA1) (0xA0) (0x9F) (0x9E) (0x9D) (0x9C) (0x9B) (0x9A) (0x99) (0x98) (0x97) (0x96) (0x95) (0x94) (0x93) (0x92) (0x91) (0x90) (0x8F) (0x8E) (0x8D) (0x8C) (0x8B) (0x8A) (0x89) (0x88) (0x87) (0x86) (0x85) (0x84) (0x83) (0x82) (0x81) (0x80) (0x7F) (0x7E) (0x7D) Name TWHSR TWAMR TWCR TWDR TWAR TWSR TWBR Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved OCR1BH OCR1BL OCR1AH OCR1AL ICR1H ICR1L TCNT1H TCNT1L Reserved TCCR1C TCCR1B TCCR1A DIDR1 DIDR0 Reserved Bit 7 – TWAM6 TWINT TWA6 TWS7 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Bit 6 – TWAM5 TWEA TWA5 TWS6 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Bit 5 – TWAM4 TWSTA TWA4 TWS5 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Timer/Counter1 Bit 4 – TWAM3 TWSTO TWA3 TWS4 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Bit 3 – TWAM2 TWWC TWA2 TWS3 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Bit 2 – TWAM1 TWEN TWA1 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Bit 1 – TWAM0 – TWA0 TWPS1 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Bit 0 TWHS – TWIE TWGCE TWPS0 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – Page 157 157 154 156 156 155 154 2-wire Serial Interface Data Register 2-wire Serial Interface Bit Rate Register – Output Compare Register B High Byte Timer/Counter1 – Output Compare Register B Low Byte Timer/Counter1 – Output Compare Register A High Byte Timer/Counter1 – Output Compare Register A Low Byte Timer/Counter1 – Input Capture Register High Byte Timer/Counter1 – Input Capture Register Low Byte Timer/Counter1 – Counter Register High Byte Timer/Counter1 – Counter Register Low Byte – – – COM1B1 – ADC5D – – – WGM13 COM1B0 – ADC4D – – – WGM12 – – ADC3D – – – CS12 – – ADC2D – 112 112 112 112 112 112 111 111 – – CS11 WGM11 AIN1D ADC1D – – – CS10 WGM10 AIN0D ADC0D – 111 110 108 160 177 – FOC1A ICNC1 COM1A1 – ADC7D – – FOC1B ICES1 COM1A0 – ADC6D – 9 8008F–AVR–06/10 Address (0x7C) (0x7B) (0x7A) (0x79) (0x78) (0x77) (0x76) (0x75) (0x74) (0x73) (0x72) (0x71) (0x70) (0x6F) (0x6E) (0x6D) (0x6C) (0x6B) (0x6A) (0x69) (0x68) (0x67) (0x66) (0x65) (0x64) (0x63) (0x62) (0x61) (0x60) 0x3F (0x5F) 0x3E (0x5E) 0x3D (0x5D) 0x3C (0x5C) 0x3B (0x5B) 0x3A (0x5A) 0x39 (0x59) 0x38 (0x58) 0x37 (0x57) 0x36 (0x56) 0x35 (0x55) 0x34 (0x54) 0x33 (0x53) 0x32 (0x52) 0x31 (0x51) 0x30 (0x50) 0x2F (0x4F) 0x2E (0x4E) 0x2D (0x4D) 0x2C (0x4C) 0x2B (0x4B) 0x2A (0x4A) 0x29 (0x49) 0x28 (0x48) 0x27 (0x47) 0x26 (0x46) 0x25 (0x45) 0x24 (0x44) 0x23 (0x43) 0x22 (0x42) 0x21 (0x41) 0x20 (0x40) 0x1F (0x3F) 0x1E (0x3E) 0x1D (0x3D) 0x1C (0x3C) 0x1B (0x3B) Name ADMUX ADCSRB ADCSRA ADCH ADCL Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved TIMSK1 TIMSK0 PCMSK2 PCMSK1 PCMSK0 PCMSK3 EICRA PCICR Reserved OSCCAL Reserved PRR Reserved Reserved CLKPR WDTCSR SREG SPH SPL Reserved Reserved Reserved Reserved Reserved SPMCSR Reserved MCUCR MCUSR SMCR Reserved DWDR ACSR Reserved SPDR SPSR SPCR GPIOR2 GPIOR1 Reserved OCR0B OCR0A TCNT0 TCCR0A Reserved GTCCR Reserved EEARL EEDR EECR GPIOR0 EIMSK EIFR PCIFR Bit 7 – – ADEN Bit 6 REFS0 ACME ADSC Bit 5 ADLAR – ADATE Bit 4 – – ADIF Bit 3 MUX3 – ADIE Bit 2 MUX2 ADTS2 ADPS2 Bit 1 MUX1 ADTS1 ADPS1 Bit 0 MUX0 ADTS0 ADPS0 Page 173 159, 176 174 176 176 ADC Data Register High byte ADC Data Register Low byte – – – – – – – – – – PCINT23 PCINT15 PCINT7 – – – – – PRTWI – – CLKPCE WDIF I – SP7 – – – – – – – – – – – ACD – SPIF SPIE BODS – – – ACBG – WCOL SPE BODSE – – – ACO – – DORD PUD – – – – – – – – – – – – PCINT22 PCINT14 PCINT6 – – – – – – – – – WDIE T – SP6 – – – – – RWWSB – – – – – – – – ICIE1 – PCINT21 PCINT13 PCINT5 – – – – PRTIM0 – – – WDP3 H – SP5 – – – – – – – – – – – – – – – – PCINT20 PCINT12 PCINT4 – – – – – – – – WDCE S – SP4 – – – – – CTPB – – – – – – – – – – PCINT19 PCINT11 PCINT3 PCINT27 ISC11 PCIE3 – – PRTIM1 – – CLKPS3 WDE V – SP3 – – – – – RFLB – – WDRF – – – – – – – – – OCIE1B OCIE0B PCINT18 PCINT10 PCINT2 PCINT26 ISC10 PCIE2 – – PRSPI – – CLKPS2 WDP2 N – SP2 – – – – – PGWRT – – BORF SM1 – ACIC – – CPHA – – – – – – – – OCIE1A OCIE0A PCINT17 PCINT9 PCINT1 PCINT25 ISC01 PCIE1 – – – – – CLKPS1 WDP1 Z SP9 SP1 – – – – – PGERS – – EXTRF SM0 – ACIS1 – – SPR1 – – – – – – – – TOIE1 TOIE0 PCINT16 PCINT8 PCINT0 PCINT24 ISC00 PCIE0 – 112 85 56 56 57 57 53 55 30 Oscillator Calibration Register – PRADC – – CLKPS0 WDP0 C SP8 SP0 – – – – – SELFPRGEN – – PORF SE – 37 31 47 9 12 12 185 37, 75 47 36 179 – – debugWire Data Register ACI – – MSTR ACIE – SPI Data Register – CPOL ACIS0 – 159 126 SPI2X SPR0 125 124 24 24 General Purpose I/O Register 2 General Purpose I/O Register 1 – – – – – – – – Timer/Counter0 Output Compare Register B Timer/Counter0 Output Compare Register A Timer/Counter0 (8-bit) – – TSM – – – – – – – – – – – – – CTC0 – – – CS02 – – – CS01 – – – CS00 – PSRSYNC – 85 84 84 83 116 22 22 EEPROM Address Register Low Byte EEPROM Data Register – – – – – – – – EEPM1 – – – EEPM0 – – – EERIE – – PCIF3 EEMPE – – PCIF2 EEPE INT1 INTF1 PCIF1 EERE INT0 INTF0 PCIF0 General Purpose I/O Register 0 22 24 54 54 55 10 ATtiny48/88 8008F–AVR–06/10 ATtiny48/88 Address 0x1A (0x3A) 0x19 (0x39) 0x18 (0x38) 0x17 (0x37) 0x16 (0x36) 0x15 (0x35) 0x14 (0x34) 0x13 (0x33) 0x12 (0x32) 0x11 (0x31) 0x10 (0x30) 0x0F (0x2F) 0x0E (0x2E) 0x0D (0x2D) 0x0C (0x2C) 0x0B (0x2B) 0x0A (0x2A) 0x09 (0x29) 0x08 (0x28) 0x07 (0x27) 0x06 (0x26) 0x05 (0x25) 0x04 (0x24) 0x03 (0x23) 0x02 (0x22) 0x01 (0x21) 0x00 (0x20) Name Reserved Reserved Reserved Reserved TIFR1 TIFR0 Reserved Reserved PORTCR Reserved Reserved Reserved PORTA DDRA PINA PORTD DDRD PIND PORTC DDRC PINC PORTB DDRB PINB Reserved Reserved Reserved Bit 7 – – – – – – – – BBMD – – – – – – PORTD7 DDD7 PIND7 PORTC7 DDC7 PINC7 PORTB7 DDB7 PINB7 – – – Bit 6 – – – – – – – – BBMC – – – – – – PORTD6 DDD6 PIND6 PORTC6 DDC6 PINC6 PORTB6 DDB6 PINB6 – – – Bit 5 – – – – ICF1 – – – BBMB – – – – – – PORTD5 DDD5 PIND5 PORTC5 DDC5 PINC5 PORTB5 DDB5 PINB5 – – – Bit 4 – – – – – – – – BBMA – – – – – – PORTD4 DDD4 PIND4 PORTC4 DDC4 PINC4 PORTB4 DDB4 PINB4 – – – Bit 3 – – – – – – – – PUDD – – – PORTA3 DDA3 PINA3 PORTD3 DDD3 PIND3 PORTC3 DDC3 PINC3 PORTB3 DDB3 PINB3 – – – Bit 2 – – – – OCF1B OCF0B – – PUDC – – – PORTA2 DDA2 PINA2 PORTD2 DDD2 PIND2 PORTC2 DDC2 PINC2 PORTB2 DDB2 PINB2 – – – Bit 1 – – – – OCF1A OCF0A – – PUDB – – – PORTA1 DDA1 PINA1 PORTD1 DDD1 PIND1 PORTC1 DDC1 PINC1 PORTB1 DDB1 PINB1 – – – Bit 0 – – – – TOV1 TOV0 – – PUDA – – – PORTA0 DDA0 PINA0 PORTD0 DDD0 PIND0 PORTC0 DDC0 PINC0 PORTB0 DDB0 PINB0 – – – Page 113 85 75 76 76 76 77 77 77 76 76 77 76 76 76 Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 – 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 – 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The ATtiny48/88 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 – 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. 11 8008F–AVR–06/10 5. Instruction Set Summary Mnemonics ADD ADC ADIW SUB SUBI SBC SBCI SBIW AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER RJMP IJMP RCALL ICALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC BRIE BRID SBI CBI LSL LSR ROL ROR Rd,Rr Rd,Rr Rd,Rr Rd,K Rr, b Rr, b P, b P, b s, k s, k k k k k k k k k k k k k k k k k k k P,b P,b Rd Rd Rd Rd k Operands Rd, Rr Rd, Rr Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd Rd Rd,K Rd,K Rd Rd Rd Rd Rd k Add two Registers Description Rd ← Rd + Rr Operation Flags Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None None None None None None I None Z, N,V,C,H Z, N,V,C,H Z, N,V,C,H None None None None None None None None None None None None None None None None None None None None None None None None None None Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V #Clocks 1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 3 3 4 4 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 2 2 1 1 1 1 ARITHMETIC AND LOGIC INSTRUCTIONS Add with Carry two Registers Add Immediate to Word Subtract two Registers Subtract Constant from Register Subtract with Carry two Registers Subtract with Carry Constant from Reg. Subtract Immediate from Word Logical AND Registers Logical AND Register and Constant Logical OR Registers Logical OR Register and Constant Exclusive OR Registers One’s Complement Two’s Complement Set Bit(s) in Register Clear Bit(s) in Register Increment Decrement Test for Zero or Minus Clear Register Set Register Relative Jump Indirect Jump to (Z) Relative Subroutine Call Indirect Call to (Z) Subroutine Return Interrupt Return Compare, Skip if Equal Compare Compare with Carry Compare Register with Immediate Skip if Bit in Register Cleared Skip if Bit in Register is Set Skip if Bit in I/O Register Cleared Skip if Bit in I/O Register is Set Branch if Status Flag Set Branch if Status Flag Cleared Branch if Equal Branch if Not Equal Branch if Carry Set Branch if Carry Cleared Branch if Same or Higher Branch if Lower Branch if Minus Branch if Plus Branch if Greater or Equal, Signed Branch if Less Than Zero, Signed Branch if Half Carry Flag Set Branch if Half Carry Flag Cleared Branch if T Flag Set Branch if T Flag Cleared Branch if Overflow Flag is Set Branch if Overflow Flag is Cleared Branch if Interrupt Enabled Branch if Interrupt Disabled Set Bit in I/O Register Clear Bit in I/O Register Logical Shift Left Logical Shift Right Rotate Left Through Carry Rotate Right Through Carry Rd ← Rd + Rr + C Rdh:Rdl ← Rdh:Rdl + K Rd ← Rd - Rr Rd ← Rd - K Rd ← Rd - Rr - C Rd ← Rd - K - C Rdh:Rdl ← Rdh:Rdl - K Rd ← Rd • Rr Rd ← Rd • K Rd ← Rd v Rr Rd ← Rd v K Rd ← Rd ⊕ Rr Rd ← 0xFF − Rd Rd ← 0x00 − Rd Rd ← Rd v K Rd ← Rd • (0xFF - K) Rd ← Rd + 1 Rd ← Rd − 1 Rd ← Rd • Rd Rd ← Rd ⊕ Rd Rd ← 0xFF PC ← PC + k + 1 PC ← Z PC ← PC + k + 1 PC ← Z PC ← STACK PC ← STACK if (Rd = Rr) PC ← PC + 2 or 3 Rd − Rr Rd − Rr − C Rd − K if (Rr(b)=0) PC ← PC + 2 or 3 if (Rr(b)=1) PC ← PC + 2 or 3 if (P(b)=0) PC ← PC + 2 or 3 if (P(b)=1) PC ← PC + 2 or 3 if (SREG(s) = 1) then PC←PC+k + 1 if (SREG(s) = 0) then PC←PC+k + 1 if (Z = 1) then PC ← PC + k + 1 if (Z = 0) then PC ← PC + k + 1 if (C = 1) then PC ← PC + k + 1 if (C = 0) then PC ← PC + k + 1 if (C = 0) then PC ← PC + k + 1 if (C = 1) then PC ← PC + k + 1 if (N = 1) then PC ← PC + k + 1 if (N = 0) then PC ← PC + k + 1 if (N ⊕ V= 0) then PC ← PC + k + 1 if (N ⊕ V= 1) then PC ← PC + k + 1 if (H = 1) then PC ← PC + k + 1 if (H = 0) then PC ← PC + k + 1 if (T = 1) then PC ← PC + k + 1 if (T = 0) then PC ← PC + k + 1 if (V = 1) then PC ← PC + k + 1 if (V = 0) then PC ← PC + k + 1 if ( I = 1) then PC ← PC + k + 1 if ( I = 0) then PC ← PC + k + 1 I/O(P,b) ← 1 I/O(P,b) ← 0 Rd(n+1) ← Rd(n), Rd(0) ← 0 Rd(n) ← Rd(n+1), Rd(7) ← 0 Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7) Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) BRANCH INSTRUCTIONS BIT AND BIT-TEST INSTRUCTIONS 12 ATtiny48/88 8008F–AVR–06/10 ATtiny48/88 Mnemonics ASR SWAP BSET BCLR BST BLD SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH CLH DATA TRANSFER INSTRUCTIONS MOV MOVW LDI LD LD LD LD LD LD LDD LD LD LD LDD LDS ST ST ST ST ST ST STD ST ST ST STD STS LPM LPM LPM SPM IN OUT PUSH POP NOP SLEEP WDR BREAK Rd, P P, Rr Rr Rd Rd, Z Rd, Z+ Rd, Rr Rd, Rr Rd, K Rd, X Rd, X+ Rd, - X Rd, Y Rd, Y+ Rd, - Y Rd,Y+q Rd, Z Rd, Z+ Rd, -Z Rd, Z+q Rd, k X, Rr X+, Rr - X, Rr Y, Rr Y+, Rr - Y, Rr Y+q,Rr Z, Rr Z+, Rr -Z, Rr Z+q,Rr k, Rr Move Between Registers Copy Register Word Load Immediate Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Direct from SRAM Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Direct to SRAM Load Program Memory Load Program Memory Load Program Memory and Post-Inc Store Program Memory In Port Out Port Push Register on Stack Pop Register from Stack No Operation Sleep Watchdog Reset Break (see specific descr. for Sleep function) (see specific descr. for WDR/timer) For On-chip Debug Only Rd ← Rr Rd+1:Rd ← Rr+1:Rr Rd ← K Rd ← (X) Rd ← (X), X ← X + 1 X ← X - 1, Rd ← (X) Rd ← (Y) Rd ← (Y), Y ← Y + 1 Y ← Y - 1, Rd ← (Y) Rd ← (Y + q) Rd ← (Z) Rd ← (Z), Z ← Z+1 Z ← Z - 1, Rd ← (Z) Rd ← (Z + q) Rd ← (k) (X) ← Rr (X) ← Rr, X ← X + 1 X ← X - 1, (X) ← Rr (Y) ← Rr (Y) ← Rr, Y ← Y + 1 Y ← Y - 1, (Y) ← Rr (Y + q) ← Rr (Z) ← Rr (Z) ← Rr, Z ← Z + 1 Z ← Z - 1, (Z) ← Rr (Z + q) ← Rr (k) ← Rr R0 ← (Z) Rd ← (Z) Rd ← (Z), Z ← Z+1 (Z) ← R1:R0 Rd ← P P ← Rr STACK ← Rr Rd ← STACK None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 1 1 2 2 1 1 1 N/A Operands Rd Rd s s Rr, b Rd, b Arithmetic Shift Right Swap Nibbles Flag Set Flag Clear Description Operation Rd(n) ← Rd(n+1), n=0..6 Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0) SREG(s) ← 1 SREG(s) ← 0 T ← Rr(b) Rd(b) ← T C←1 C←0 N←1 N←0 Z←1 Z←0 I←1 I←0 S←1 S←0 V←1 V←0 T←1 T←0 H←1 H←0 Flags Z,C,N,V None SREG(s) SREG(s) T None C C N N Z Z I I S S V V T T H H #Clocks 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit Store from Register to T Bit load from T to Register Set Carry Clear Carry Set Negative Flag Clear Negative Flag Set Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Set Signed Test Flag Clear Signed Test Flag Set Twos Complement Overflow. Clear Twos Complement Overflow Set T in SREG Clear T in SREG Set Half Carry Flag in SREG Clear Half Carry Flag in SREG MCU CONTROL INSTRUCTIONS 13 8008F–AVR–06/10 6. Ordering Information 6.1 ATtiny48 Speed (MHz) Power Supply Ordering Code(1) ATtiny48-MMU ATtiny48-MMH ATtiny48-MMHR ATtiny48-PU ATtiny48-AU ATtiny48-AUR ATtiny48-CCU ATtiny48-CCUR ATtiny48-MU ATtiny48-MUR Package(2) 28M1 28M1 28M1 28P3 32A 32A 32CC1 32CC1 32M1-A 32M1-A Operational Range 12 1.8 – 5.5 Industrial (-40°C to +85°C)(3) Notes: 1. Code indicators: – H: NiPdAu lead finish – U: matte tin – R: tape & reel 2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazardous Substances (RoHS). 3. These devices can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. Package Type 28M1 28P3 32A 32CC1 32M1-A 28-pad, 4 x 4 x 1.0 body, Lead Pitch 0.45 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP) 32-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP) 32-ball (6 x 6 Array), 0.50 mm Pitch, 4 x 4 x 0.6 mm, Ultra Thin, Fine-Pitch Ball Grid Array Package (UFBGA) 32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 14 ATtiny48/88 8008F–AVR–06/10 ATtiny48/88 6.2 ATtiny88 Speed (MHz) Power Supply Ordering Code(1) ATtiny88-MMU ATtiny88-MMH ATtiny88-MMHR ATtiny88-PU ATtiny88-AU ATtiny88-AUR ATtiny88-CCU ATtiny88-CCUR ATtiny88-MU ATtiny88-MUR Package(2) 28M1 28M1 28M1 28P3 32A 32A 32CC1 32CC1 32M1-A 32M1-A Operational Range 12 1.8 – 5.5 Industrial (-40°C to +85°C)(3) Notes: 1. Code indicators: – H: NiPdAu lead finish – U: matte tin – R: tape & reel 2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazardous Substances (RoHS). 3. These devices can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. Package Type 28M1 28P3 32A 32CC1 32M1-A 28-pad, 4 x 4 x 1.0 body, Lead Pitch 0.45 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP) 32-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP) 32-ball (6 x 6 Array), 0.50 mm Pitch, 4 x 4 x 0.6 mm, Ultra Thin, Fine-Pitch Ball Grid Array Package (UFBGA) 32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 15 8008F–AVR–06/10 7. Packaging Information 7.1 28M1 D C 1 2 3 Pin 1 ID E SIDE VIEW TOP VIEW A A1 y K D2 1 0.45 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A MIN 0.80 0.00 0.17 NOM 0.90 0.02 0.22 0.20 REF 3.95 2.35 3.95 2.35 4.00 2.40 4.00 2.40 0.45 0.35 0.00 0.20 0.40 – – 0.45 0.08 – 4.05 2.45 4.05 2.45 MAX 1.00 0.05 0.27 NOTE R 0.20 2 3 E2 b A1 b C D L e 0.4 Ref (4x) BOTTOM VIEW D2 E E2 e L y Note: The terminal #1 ID is a Laser-marked Feature. K 10/24/08 Package Drawing Contact: packagedrawings@atmel.com TITLE 28M1, 28-pad, 4 x 4 x 1.0 mm Body, Lead Pitch 0.45 mm, 2.4 x 2.4 mm Exposed Pad, Thermally Enhanced Plastic Very Thin Quad Flat No Lead Package (VQFN) GPC ZBV DRAWING NO. 28M1 REV. B 16 ATtiny48/88 8008F–AVR–06/10 ATtiny48/88 7.2 28P3 D PIN 1 E1 A SEATING PLANE L B1 e E B B2 A1 (4 PLACES) C eB 0º ~ 15º REF SYMBOL A A1 D E E1 B COMMON DIMENSIONS (Unit of Measure = mm) MIN – 0.508 34.544 7.620 7.112 0.381 1.143 0.762 3.175 0.203 – NOM – – – – – – – – – – – MAX 4.5724 – 34.798 8.255 7.493 0.533 1.397 1.143 3.429 0.356 10.160 Note 1 Note 1 NOTE Note: 1. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). B1 B2 L C eB e 2.540 TYP 09/28/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 28P3, 28-lead (0.300"/7.62 mm Wide) Plastic Dual Inline Package (PDIP) DRAWING NO. 28P3 REV. B R 17 8008F–AVR–06/10 7.3 32A PIN 1 B PIN 1 IDENTIFIER e E1 E D1 D C 0˚~7˚ A1 L COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E MIN – 0.05 0.95 8.75 6.90 8.75 6.90 0.30 0.09 0.45 NOM – – 1.00 9.00 7.00 9.00 7.00 – – – 0.80 TYP MAX 1.20 0.15 1.05 9.25 7.10 9.25 7.10 0.45 0.20 0.75 Note 2 Note 2 NOTE A2 A Notes: 1. This package conforms to JEDEC reference MS-026, Variation ABA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. E1 B C L e 10/5/2001 2325 Orchard Parkway San Jose, CA 95131 TITLE 32A, 32-lead, 7 x 7 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) DRAWING NO. 32A REV. B R 18 ATtiny48/88 8008F–AVR–06/10 ATtiny48/88 7.4 32CC1 12 A B C D E F 34 5 6 0.08 Pin#1 ID D SIDE VIEW b1 A1 E TOP VIEW A A2 E1 e 12 F E D C B A e SYMBOL 34 5 6 32-Øb COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX NOTE D1 A A1 A2 b b1 D – 0.12 0.25 0.25 3.90 3.90 – – 0.38 REF 0.30 – 4.00 2.50 BSC 4.00 2.50 BSC 0.50 BSC 0.60 – 0.35 – 4.10 4.10 1 2 A1 BALL CORNER BOTTOM VIEW D1 E E1 Note1: Dimension “b” is measured at the maximum ball dia. in a plane parallel to the seating plane. Note2: Dimension “b1” is the solderable surface defined by the opening of the solder resist layer. e Package Drawing Contact: packagedrawings@atmel.com TITLE 32CC1, 32-ball (6 x 6 Array), 4 x 4 x 0.6 mm package, ball pitch 0.50 mm, Ultra Thin, Fine-Pitch Ball Grid Array (UFBGA) GPC CAG 07/06/10 DRAWING NO. REV. 32CC1 B 19 8008F–AVR–06/10 7.5 32M1-A D D1 1 2 3 0 Pin 1 ID E1 E SIDE VIEW TOP VIEW A2 A3 A1 K P D2 A 0.08 C COMMON DIMENSIONS (Unit of Measure = mm) MIN 0.80 – – NOM 0.90 0.02 0.65 0.20 REF 0.18 4.90 4.70 2.95 4.90 4.70 2.95 0.23 5.00 4.75 3.10 5.00 4.75 3.10 0.50 BSC 0.30 – – 0.20 – 0.40 – – 0.50 0.60 o 12 – 0.30 5.10 4.80 3.25 5.10 4.80 3.25 MAX 1.00 0.05 1.00 NOTE SYMBOL A P Pin #1 Notch (0.20 R) 1 2 3 A1 A2 A3 E2 b K D D1 D2 E b e L E1 E2 e L P BOTTOM VIEW 0 Note: JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2. K 5/25/06 2325 Orchard Parkway San Jose, CA 95131 TITLE 32M1-A, 32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm, 3.10 mm Exposed Pad, Micro Lead Frame Package (MLF) DRAWING NO. 32M1-A REV. E R 20 ATtiny48/88 8008F–AVR–06/10 ATtiny48/88 8. Errata 8.1 8.1.1 ATtiny48 Rev. C No known errata. 8.1.2 Rev. B Not sampled. 8.1.3 Rev. A Not sampled. 21 8008F–AVR–06/10 8.2 8.2.1 ATtiny88 Rev. C No known errata. 8.2.2 Rev. B No known errata. 8.2.3 Rev. A Not sampled. 22 ATtiny48/88 8008F–AVR–06/10 ATtiny48/88 9. Datasheet Revision History Please note that page references in this section refer to the current revision of this document. 9.1 Rev. 8008F - 06/10 1. Updated notes 1 and 10 in table in Section 21.2 “DC Characteristics” on page 204. 2. Updated package drawing in Section 7.4 “32CC1” on page 19. 3. Updated bit syntax throughout the datasheet, e.g. from CS02:0 to CS0[2:0]. 9.2 Rev. 8008E - 05/10 1. Section 4. “Register Summary” on page 8, added SPH at address 0x3E. 2. Section 7.1 “28M1” on page 16 updated with correct package drawing. 9.3 Rev. 8008D - 03/10 1. Separated Typical Characteristic plots, added Section 22.2 “ATtiny88” on page 247. 2. Updated: – Section 1.1 “Pin Descriptions” on page 3, Port D, adjusted texts ‘sink and source’ and ‘high sink’. – Table 6-3 on page 28 adjusted, to fix TBD. – Section 6.4 “128 kHz Internal Oscillator” on page 28 adjusted, to fix TBD. – Section 8.4 “Watchdog Timer” on page 43, updated. – Section 21.2 “DC Characteristics” on page 204, updated TBD in notes 5 and 8. 3. Added: – UFBGA package (32CC1) in, “Features” on page 1, “Pin Configurations” on page 2, Section 6. “Ordering Information” on page 14, and Section 7. “Packaging Information” on page 16 – Addresses in all Register Desc. tables, with cross-references to Register Summary – Tape and reel in Section 6. “Ordering Information” on page 14 9.4 Rev. 8008C - 03/09 1. Updated sections: – “Features” on page 1 – “Reset and Interrupt Handling” on page 13 – “EECR – EEPROM Control Register” on page 22 – “Features” on page 127 – “Bit Rate Generator Unit” on page 133 – “TWBR – TWI Bit Rate Register” on page 154 – “TWHSR – TWI High Speed Register” on page 157 – “Analog Comparator” on page 158 – “Overview” on page 161 – “Operation” on page 162 – “Starting a Conversion” on page 163 23 8008F–AVR–06/10 – “Programming the Lock Bits” on page 198 – “Absolute Maximum Ratings*” on page 204 – “DC Characteristics” on page 204 – “Speed” on page 206 – “Register Summary” on page 8 2. Added sections – “High-Speed Two-Wire Interface Clock – clkTWIHS” on page 26 – “Analog Comparator Characteristics” on page 208 3. Updated Figure 6-1 on page 25. 4. Updated order codes on page 14 and page 15 to reflect changes in leadframe composition. 9.5 Rev. 8008B - 06/08 1. Updated introduction of “I/O-Ports” on page 58. 2. Updated “DC Characteristics” on page 204. 3. Added “Typical Charateristics” on page 218. 9.6 Rev. 8008A - 06/08 1. Initial revision. 24 ATtiny48/88 8008F–AVR–06/10 ATtiny48/88 25 8008F–AVR–06/10 Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 International Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Product Contact Web Site www.atmel.com Technical Support avr@atmel.com Sales Contact www.atmel.com/contacts Literature Requests www.atmel.com/literature Disclaimer: T he information in this document is provided in connection with Atmel products. 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