PC107AMZFU100L

Features • Processor Bus Frequency up to 100 MHz • 64- or 32-bit Data Bus and 32-bit Address Bus • Provides Support for Either Asynchronous SRAM, Burst SRAM, or Pipelined Burst SRAM Compliant with PCI Specification, Revision 2.1 PCI Interface Operates up to 66 MHz/5.0V Compatible IEEE 1149.1 Compliant, JTAG Boundary-scan Interface PD Max = 1W (66 MHz), Full Operating Conditions Nap, Doze and Sleep Modes for Power Savings Two-channel Integrated DMA Controller Message Unit – Intelligent Input/Output (Two-wire Interface) Message Controller – Two Door Bell Registers – Inbound and Outbound Messaging Registers • Inter-integrated Circuit (Two-wire Interface) Controller, Full Master/Slave Support • Embedded Programmable Interrupt Controller (EPIC) – Five Hardware Interrupts (IRQs) or 16 Serial Interrupts – Four Programmable Timers • • • • • • • PCI Bridge Memory Controller PC107A Preliminary Specification β-site Description The PC107A PCI Bridge/Integrated Memory Controller provides a bridge between the Peripheral Component Interconnect, (PCI) bus and PowerPC 603e™, PowerPC 740™, PowerPC 750™ or PC7400 microprocessors. PCI support allows system designers to design systems quickly using peripherals already designed for PCI and other standard interfaces available in the personal computer hardware environment. The PC107A provides many other necessities for embedded applications including a high-performance memory controller and dual processor support, 2-channel flexible DMA controller, an interrupt controller, an I2O-ready message unit, an inter-integrated circuit controller (Two-wire Interface), and low skew clock drivers. The PC107A contains an Embedded Programmable Interrupt Controller (EPIC) featuring five hardware interrupts (IRQ’s) as well as sixteen serial interrupts along with four timers. The PC107A uses an advanced, 2.5V HiP3 process technology and is fully compatible with TTL devices. ZF PBGA 503 Flip-chip Plastic Ball Grid Array GH suffix HITCE 503 Ceramic Ball Grid Array Screening This product is manufactured in full compliance with: • • • • PBGA upscreenings based upon Atmel standards Full military temperature range (Tj = -55°C, +125°C) Industrial temperature range (Tj = -40°C, +110°C) HiTCE (TBC) Rev. 2137C–HIREL–03/04 2137C–HIREL–03/04 General Description Simplified Block Diagram The PC107A integrates a PCI bridge, memory controller, DMA controller, EPIC interrupt controller/timers, a message unit with an Intelligent Input/Output (I2O) message controller, and an Inter-integrated Circuit (two-wire interface) controller. The integration reduces the overall packaging requirements and the number of discrete devices required for an embedded system. Figure 1 shows the major functional units within the PC107A. Note that this is a conceptual block diagram intended to show the basic features rather than an attempt to show how these features are physically implemented. Figure 1. PC107A Block Diagram Additional features: • Programmable I/O • with Watchpoint • JTAG/COP Interface • Power Management Data Bus (64- or 32-bit) with 8-bit Parity or ECC Memory/ROM/ Port X Control/ Address MPC107 60x Bus Interface (64- or 32-Bit Data Bus) Peripheral Logic Block Message Unit (with I2O) DMA Controller Address (32-Bit) Data (64-Bit) Data Path ECC Controller Memory Controller Configuration Registers I2C I2C Controller EPIC Interrupt Controller /Timers PCI Bus Interface Unit Address Translator PCI Arbiter DLL PLL Fanout Buffers Central Control Unit SDRAM_SYNC_IN SDRAM Clocks CPU Clocks PCI_SYNC_IN PCI Bus Clocks 5 IRQs/ 16 Serial Interrupts 32-Bit PCI Interface Five Request/Grant Pairs OSC_IN 2 PC107A [Preliminary] 2137C–HIREL–03/04 PC107A [Preliminary] General Parameters The following list provides a summary of the general parameters of the PC107A: Technology Die size Transistor count Logic design Package Core power supply I/O power supply Features 0.29 µm CMOS, five-layer metal 50 mm2 0.96 million Fully-static Surface mount 503 Plastic Ball Grid Array (C4/PBGA) 2.5 ±5% V DC (nominal; see Table 3 on page 12 for recommended operating conditions) 3.0 to 3.6V DC The PC107A provides an integrated high-bandwidth, high-performance interface between up to two 60x processors, the PCI bus, and main memory. This section summarizes the features of the PC107A. Major features of the PC107A are as follows: • Memory Interface – – – – – – – – – – – – • 64-/32-bit 100 MHz bus Programmable timing supporting either FPM DRAM, EDO DRAM or SDRAM High-bandwidth bus (32-/64-bit data bus) to DRAM Supports one to eight banks of 4-, 16-, 64-, or 128-Mbit memory devices, and up to four banks of 256 Mbit SDRAM devices Supports 1M byte to 1 Gbyte DRAM memory 144M bytes of ROM space 8-, 32-, or 64-bit ROM Write buffering for PCI and processor accesses Supports normal parity, read-modify-write (RMW), or ECC Data-path buffering between memory interface and processor Low-voltage TTL logic (LVTTL) interfaces Port X: 8-, 32-, or 64-bit general-purpose I/O port using ROM controller interface with programmable address strobe timing PCI 2.1-compliant PCI 5.0V tolerance Support for PCI locked accesses to memory Support for accesses to PCI memory, I/O, and configuration spaces Selectable big- or little-endian operation Store gathering of processor-to-PCI write and PCI-to-memory write accesses Memory prefetching of PCI read accesses Selectable hardware-enforced coherency PCI bus arbitration unit (five request/grant pairs) PCI agent mode capability Address translation unit Some internal configuration registers accessible from PCI 32-bit PCI Interface Operating up to 66 MHz – – – – – – – – – – – – • Two-channel Integrated DMA Controller (Writes to ROM/Port × Not Supported) 3 2137C–HIREL–03/04 – – – – – – – • – – – – • • Supports direct mode or chaining mode (automatic linking of DMA transfers) Supports scatter gathering-read or write discontinuous memory Interrupt on completed segment, chain, and error Local-to-local memory PCI-to-PCI memory PCI-to-local memory PCI memory-to-local memory Two doorbell registers An extended doorbell register mechanism that facilitates interprocessor communication through interrupts in a dual-local-processor system Two inbound and two outbound messaging registers I2O message controller Message Unit Two-wire Interface Controller with Full Master/Slave Support (Except Broadcast All) Embedded Programmable Interrupt Controller (EPIC) – – Five hardware interrupts (IRQs) or 16 serial interrupts Four programmable timers • • • • • • Integrated PCI Bus, CPU, and SDRAM Clock Generation Programmable PCI Bus, 60x, and Memory Interface Output Drivers Dynamic Power Management – Supports 60x Nap, Doze, and Sleep Modes Programmable Input and Output Signals with Watchpoint Capability Built-in PCI Bus Performance Monitor Facility Debug Features – – Error injection/capture on data path IEEE 1149.1 (JTAG)/test interface Supports up to two PowerPCTM microprocessors with 60x bus interface Supports various operating frequencies and bus divider ratios 32-bit address bus, 64/32-bit data bus supported at 100 MHz Supports full memory coherency Supports optional local bus slave Decoupled address and data buses for pipelining of 60x accesses Store gathering on 60x-to-PCI writes Concurrent transactions on 60x and PCI buses supported • Processor Interface – – – – – – – – 4 PC107A [Preliminary] 2137C–HIREL–03/04 PC107A [Preliminary] Pin Assignments Pinout Listings Table 1 provides the pinout listing for the PC107A, 503 PBGA package. Table 1. PC107A Pinout Listing Signal Name Package Pin Number Pin Type 60x Processor Interface Signals AE22, AE16, AA14, AE17, AD21, AD14, AD20, AB16, AB20, AB15, AA20, AD13, Y15, AE12, AD15, AB9, AB14, AA8, AC13, Y12, Y11, AE15, AE13, AA16, Y13, AB8, AD12, AE10, AB13, Y9, Y8, AD9 AC7 Y7 AE11 AD11 AB17 Y14 AD16 AC10 AD10 AB10 P1, R1, P2, T4, T1, T3, R4, P6, U6, V5, V2, T5, U1, R6, W1, V4, W2, U4, T2, V6, W3, W5, Y1, Y2, Y4, Y5, AA1, AA2, AA4, AB1, AB3, AB4 AA7, W6, AB6, AA6, AB5, AC4, AD3, AB7, AE1, W4, N6, M1, N3, N4, N5, N1, M2, R2, V1, P5, P4, N2, U2, AE4, AE6, AE2, AE3, AE7, AD5, AB2, AC2, AC1 AE9, AD6, AD8, AD1, AE8, AD7, AD4, AE5 AD17 Y17 AE14 AE21 AB11 AA10 AE19, AD18, AB18 AD19, AC19, AB19, AA19, AA18 Supply Voltage Output Driver Type Notes A[0–31] I/O BVDD DRV_CPU (4) AACK ARTRY BG0 BG1 BR0 BR1 CI DBG0 DBG1 DBGLB Output I/O Output Output Input Input I/O Output Output Output BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD DRV_CPU DRV_CPU DRV_CPU DRV_CPU – – DRV_CPU DRV_MEM_ADDR DRV_MEM_ADDR DRV_MEM_ADDR (10) (15) DH[0–31] I/O BVDD DRV_CPU (4) DL[0–31] I/O BVDD DRV_CPU (4) DP[0–7] GBL LBCLAIM TA TBST TEA TS TSIZ[0–2] TT[0–4] I/O I/O Input I/O I/O Output I/O I/O I/O BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD DRV_CPU DRV_CPU (4) DRV_CPU DRV_CPU DRV_CPU DRV_CPU DRV_CPU DRV_CPU (15) (15) (4) (4) 5 2137C–HIREL–03/04 Table 1. PC107A Pinout Listing (Continued) Signal Name WT Package Pin Number AC16 Pin Type I/O PCI Interface Signals N23, N21, M20, M21, M22, M24, M25, L20, L22, K25, K24, K23, K21, J20, J24, J25, H20, F24, E25, F21, E24, E22, D25, A25, B25, A23, B23, B22, C22, C25, D23, D21 L24, J22, G22, A24, G23 G20 T24, P22, P21, R22, N20 L25 V21 H24 G21 G24 G25 W25, V25, U25, T25, T23 F25 H21 H25 Supply Voltage BVDD Output Driver Type DRV_CPU Notes AD[31–0] I/O OVDD DRV_PCI (4)(11) C/BE[3–0] DEVSEL FRAME GNT[4–0] IDSEL INTA IRDY LOCK PAR PERR REQ[4–0] SERR STOP TRDY I/O I/O I/O Output Input Output I/O Input I/O I/O Input I/O I/O I/O Memory Interface Signals OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD DRV_PCI DRV_PCI DRV_PCI DRV_PCI – DRV_PCI DRV_PCI – DRV_PCI DRV_PCI – DRV_PCI DRV_PCI DRV_PCI (4)(11) (6)(11) (6)(11) (4)(11) (6)(11)(12) (6)(11) (6) (11) (6)(11)(13) (10) (6)(11)(12) (6)(11) (6)(11) AS CAS/DQM[0–7] CKE FOE A4 A2, B1, A11, A10, B3, C2, F12, D11 A12 A13 M6, L4, L6, K2, K4, K5, J4, J6, H4, H5, G3, G5, G6, F5, F1, E1, B14, D15, B15, E16, D16, C16, D18, D17, B17, F18, E19, E20, B19, B20, B21, A22 M5, L1, L2, K1, K3, J1, J2, H1, H2, H6, G2, G4, F4, G1, F2, E2, F14, F15, A16, F17, B16, A17, A18, A19, B18, E18, D19, F19, A20, C19, D20, A21 D2, C1, A15, A14, D1, D3, F13, C13 E6, C4, D5, E4, C10, F11, B10, B11 D10 B9 B5 Output Output Output I/O GVDD GVDD GVDD GVDD DRV_MEM_ADDR DRV_MEM_ADDR DRV_MEM_ADDR DRV_MEM_ADDR (4) (1) (1)(2) MDH[0–31] I/O GVDD DRV_MEM_DATA (4) MDL[0–31] I/O GVDD DRV_MEM_DATA (3)(4) PAR/AR[0–7] RAS/CS[0–7] RCS0 RCS1 RCS2 I/O Output I/O Output Output GVDD GVDD GVDD GVDD GVDD DRV_MEM_DATA DRV_MEM_ADDR DRV_MEM_ADDR DRV_MEM_DATA DRV_MEM_ADDR (4) (4) (1)(2) 6 PC107A [Preliminary] 2137C–HIREL–03/04 PC107A [Preliminary] Table 1. PC107A Pinout Listing (Continued) Signal Name RCS3 SDBA0 SDBA1 SDCAS SDMA[13–0] SDRAS WE Package Pin Number D7 A9 A8 D4 E10, F9, D9, F8, E8, D8, B8, E7, C7, B7, A7, B6, A6, A5 B4 A3 Pin Type Output Output Output Output Output Output Output EPIC Control Signals INT IRQ_0 / S_INT IRQ_1 / S_CLK IRQ_2 / S_RST IRQ_3 / S_FRAME IRQ_4/ L_INT Y22 U24 C24 T21 U20 V22 Output Input I/O I/O I/O I/O Two-wire Interface Control Signals SCL SDA AB25 AB24 I/O I/O Clock Signals CKO CPU_CLK[0–2] OSC_IN PCI_CLK[0–4] PCI_SYNC_IN PCI_SYNC_OUT SDRAM_CLK[0–3] SDRAM_SYNC_IN SDRAM_SYNC_OUT V20 AA12, AA13, AB12 U22 R25, P24, R24, N24, N25 P20 P25 D14, D13, E12, E14 E13 D12 Output Output Input Output Input Output Output Input Output Miscellaneous Signals HRESET HRESET_CPU MCP NMI QACK QREQ SRESET AA23 AB21 AE20 AC25 AE18 M4 Y18 Input Output Output Input Output Input Output OVDD BVDD OVDD OVDD BVDD BVDD BVDD – DRV_CPU DRV_CPU – DRV_CPU – DRV_CPU (10) (10) (10)(12) (12)(16) Supply Voltage GVDD GVDD GVDD GVDD GVDD GVDD GVDD Output Driver Type DRV_MEM_ADDR DRV_MEM_ADDR DRV_MEM_ADDR DRV_MEM_ADDR DRV_MEM_ADDR DRV_MEM_ADDR DRV_MEM_ADDR Notes (1)(2) (1) (4)(5) (1) OVDD OVDD OVDD OVDD OVDD OVDD DRV_CPU – DRV_PCI DRV_PCI DRV_PCI DRV_PCI (16) OVDD OVDD DRV_CPU DRV_CPU (8)(12) (8)(12) OVDD BVDD OVDD OVDD OVDD OVDD GVDD GVDD GVDD DRV_PCI DRV_MEM_ADDR – DRV_MEM_ADDR – DRV_MEM_ADDR DRV_MEM_ADDR – DRV_MEM_ADDR (4) (4) (4) 7 2137C–HIREL–03/04 Table 1. PC107A Pinout Listing (Continued) Signal Name Package Pin Number Pin Type Test/Configuration Signals PLL_CFG[0–3] TCK TDI TDO TEST TEST1 TEST2 TMS TRIG_IN TRIG_OUT TRST AC22, AD23, AD22, AE23 W24 Y25 W23 AA25 V24 D6 Y24 W22 W21 AA24 Input Input Input Output Input Input Input Input Input Output Input Power and Ground Signals AVDD AE24 AA21, AB22, AC11, AC14, AC17, AC20, AC23, AC3, AC5, AC8, AD24, AE25, C12, C15, C18, C21, C23, C3, C6, C9, E3, F10, F16, F20, F23, F6, G11, G13, G15, G18, G8, H19, H3, H7, J23, K20, K6, L19, L3, L7, M23, N19, N7, P3, R19, R23, R7, T20, T6, U3, V19, V23, V7, W11, W13, W15, W18, W8, Y10, Y16, Y19, Y20, Y3, Y6 B2, C5, C8, C11, C14, C17, C20, E5, E9, E11, E15, E17, F3, G7, G9, G12, G14, G17, G19, J3, J5, J7, L5, M3, M7 F7 D22, F22, H22, K22, N22, T22 B24, E21, E23, H23, J19, J21, L21, L23, M19, P19, P23, R21, U19, U21, U23, Y23 P7, R3, R5, U5, U7, V3, W7, W9, W12, W14, W17, AA3, AA5, AA9, AA11, AA15, AA17, AC6, AC9, AC12, AC15, AC18, AC21, AD2 K19, W16, T19, G10, G16, K7, T7, W10, W19, W20, Y21, AA22, AB23, AC24, AD25 Input – – OVDD OVDD OVDD OVDD OVDD OVDD GVDD OVDD OVDD OVDD OVDD – – – DRV_PCI – – – – – DRV_CPU – (10) (7)(10)(14) (7)(10) (8) (9) (7)(10) (2)(4) (7)(10) (7)(10) Supply Voltage Output Driver Type Notes GND Input – – GVDD LAVDD LVDD OVDD Input Input Input Input – – – – – – – – BVDD Input – – VDD Input – – Manufacturing Pins FTP[2–3] MTP[1–2] R20, D24 B12, B13 I/O I/O OVDD GVDD DRV_PCI DRV_MEM_ADDR (4)(8) (4)(9) 8 PC107A [Preliminary] 2137C–HIREL–03/04 PC107A [Preliminary] Notes: 1. This pin has an internal pull-up resistor which is enabled only when the PC107A is in the reset state. The value of the internal pull-up resistor is not guaranteed, but is sufficient to ensure that a logic "1" is read into configuration bits during reset. 2. This pin is a reset configuration pin. 3. MDL[0] is a reset configuration pin and has an internal pull-up resistor which is enabled only when the MPC107 is in the reset state.The value of the internal pull-up resistor is not guaranteed, but is sufficient to insure that a logic '1' is read into configuration bits during reset. 4. Multi-pin signals such as AD[0–31] or DL[0–31] have their physical package pin numbers listed in order corresponding to the signal names. Ex: AD0 is on pin D21, AD1 is on pin D23,... AD31 is on pin N23. 5. SDMA[10–1] are reset configuration pins and have internal pull-up resistors which are enabled only when the MPC107 is in the reset state.The values of the internal pull-up resistors is not guaranteed, but are sufficient to ensure that logic "1"s are read into the configuration bits during reset. 6. Recommend a weak pull-up resistor (2 kΩ– 10 kΩ) be placed on this PCI control pin to LVDD. 7. VIH and VIL for these signals are the same as the PCI VIH and VIL entries in Table 7, “DC Electrical Specifications.” 8. Recommend a weak pull-up resistor (2 kΩ – 10 kΩ) be placed on this pin to OVDD. 9. Recommend a weak pull-up resistor (2 kΩ – 10 kΩ) be placed on this pin to GVDD. 10. This pin has an internal pull-up resistor; the value of the internal pull-up resistor is not guaranteed, but is sufficient to prevent unused inputs from floating. 11. This pin is affected by programmable PCI_HOLD_DEL parameter, see “PCI Signal Output Hold Timing” on page 29.” 12. This pin is an open drain signal. 13. This pin is a sustained tri-state pin as defined by the PCI Local Bus Specification. 14. See “Connection Recommendations” on page 43 for additional information on this pin. 15. A weak pull-up resistor is recommend (2 kΩ – 10 kΩ) to be placed on this pin to BVDD. 16. If BVDD = 2.5V ±5%, this microprocessor interface pin needs to be DC voltage level shifted from OVDD (3.3 ±0.3V) to 2.5V ±5%; this can typically be accomplished with a two resistor voltage divider circuit since the signal is an output only signal. 9 2137C–HIREL–03/04 Signal Description Figure 2. PC107A Microprocessor Signal Groups AS CAS/DQM[0-7] CKE FOE MDH[0-31] MDL[0-31] PAR/AR[0-7] RAS/CS[0-7] RCS0 RCS1 1 8 1 1 32 32 8 8 1 1 1 1 1 SDBA0 SDBA1 SDcAS SDMA[13-0] SDRAS WE 1 1 1 14 1 1 32 1 1 1 1 1 1 1 1 1 1 32 32 8 1 1 1 1 1 1 INT IRQ_0/S_INT IRQ_1/S_CLK IRQ2_2/S_RST IRQ_3/S_FRAME IRQ_4/L_INT 1 1 1 1 1 1 32 4 1 SCL 1 1 AD[0-31] C/BE[0-3] DEVSEL FRAME GNT[0-4] IDSEL INTA IRDY LOCK PAR PERR REQ[0-4] SERR STOP A[0-31] AACK ARTRY BG0 BG1 BR0 BR1 CI DBG0 DBG1 DBGLB DLL[0-31] DL[0-31] DL[0-7] GBL LBCLAIM TA TBST TEA TS TSIZ[0-2] TT[0-4] WT Memory Interface Signals RCS2 RCS3 60x Processor Interface Signals 3 5 1 EPIC Control Signals Two-wire Interface Control Signals 1 5 1 SDA CKO CPUCLK[0-2] OSC_IN PCI_CLK[0-4] 1 3 1 5 1 1 4 1 1 1 1 1 1 6 1 1 1 PCI Interface Signals Clock Signals PCI_SYNC_IN PCI_SYNC_OUT SDRAM_CLK[0-3] SDRAM_SYNC_IN SDRAM_SYNC_OUT 1 HRESET HRESET_CPU MCP TRDY 1 1 1 1 1 1 1 4 1 1 1 1 1 1 PLL_CFG[0-3] TCK TDI TDO TEST TEST1 TEST2 TMS TRIG_IN TRIG_OUT TRST Miscellaneous Signals NMI QACK QREQ SRESET Test/Configuration Signals AVdd GND GVdd 1 64 25 1 6 16 24 15 1 1 1 1 Power and Ground Signals LAVdd LVdd OVdd BVdd Vdd 2 2 FTP[2-3] MTP[1-2] Manufacturing Pins 10 PC107A [Preliminary] 2137C–HIREL–03/04 PC107A [Preliminary] Detailed Specification Scope Applicable Documents Requirements General Design and Construction Terminal Connections Absolute Maximum Ratings The terminal connections are shown in Table 1, “PC107A Pinout Listing,” on page 5. The tables in this section describe the PC107A DC electrical characteristics. Table 2 provides the absolute maximum ratings. Table 2. Absolute Maximum Ratings Symbol VDD GVDD BVDD OVDD AVDD/LAVDD LVDD VIN TJ TSTG Notes: Characteristic(1) Supply Voltage – Core Supply Voltage – Memory Bus Drivers Supply Voltage – Processor Bus Drivers Supply Voltage – PCI and Standard I/O Buffers Supply Voltage – PLLs and DLL Supply Voltage – PCI Reference Input Voltage (2) This drawing describes the specific requirements for the PC107A, in compliance with Atmel standard screening. 1. MIL-STD-883: Test methods and procedures for electronics. 2. SQ32S0100.0: Quality levels for supplied components. The microcircuits are in accordance with the applicable documents and as specified herein. Value -0.3 to 2.75 -0.3 to 3.6 -0.3 to 3.6 -0.3 to 3.6 -0.3 to 2.75 -0.3 to 5.4 -0.3 to 3.6 -55 to 125 -55 to 150 Unit V V V V V V V °C °C Operational Die-Junction Temperature Range Storage Temperature Range 1. Functional and tested operating conditions are given in Table 3. Absolute maximum ratings are stress ratings only and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. PCI inputs with LVDD = 5V ± 5% V DC may be correspondingly stressed at voltages exceeding LVDD + 0.5V DC. 11 2137C–HIREL–03/04 Recommended Operating Conditions Table 3 provides the recommended operating conditions for the PC107A. Table 3. Recommended Operating Conditions Symbol VDD GVDD BVDD OVDD AVDD LAVDD LVDD Characteristic Supply Voltage Supply Voltages for Memory Bus Drivers Supply Voltages for Processor Bus Drivers I/O Buffer supply for PCI and Standard PLL Supply Voltage DLL Supply Voltage PCI Reference PCI Inputs VIN TJ Notes: Input Voltage All Other Inputs Die-Junction Temperature 0 to 3.6 -55°C to 125°C V °C Recommended Value 2.5 ±5% 3.3 ±5% 3.3 ±5% 2.5 ±5% 3.3 ±0.3 2.5 ±5% 2.5 ±5% 5.0 ±5% 3.3 ±0.3 0 to 3.6 or 5.75 Unit V V V V V V V V V Notes (4) (6) (6) (4) (5) (5) (7)(8) (7)(8) (1)(2) (3) 1. PCI pins are designed to withstand LVDD + 0.5V DC when LVDD is connected to a 5.0V DC power supply. 2. PCI pins are designed to withstand LVDD + 0.5V DC when LVDD is connected to a 3.3V DC power supply. 3. Input voltage (VIN) must not be greater than the supply voltage (VDD/AVDD/LAVDD) by more than 2.5V at all times, including during power-on reset. 4. OVDD must not exceed VDD/AVDD/LAVDD by more than 1.8V at any time, including during power-on reset. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 5. VDD/AVDD/LAVDD must not exceed OVDD by more than 0.6V at any time, including during power-on reset. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 6. BVDD/GVDD must not exceed VDD/AVDD/LAVDD by more than 1.8V at any time, including during power-on reset. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 7. LVDD must not exceed VDD/AVDD/LAVDD by more than 5.4V at any time including during power-on reset. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences 8. LVDD must not exceed OVDD by more than 3.6V at any time, including during power-on reset. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. Cautions: 12 PC107A [Preliminary] 2137C–HIREL–03/04 PC107A [Preliminary] Figure 3 shows the supply voltage sequencing and separation cautions. Figure 3. Supply Voltage Sequencing and Separation Cautions DC Power Supply Voltage 5V 9 8 See Note 1 below. LVDD at 5V 3.3V 2.5V 6 9 8 5.7 OVDD/BVDD/GVDD(LVDD at 3.3V ----) VDD/AVDD/LAVDD Vdd Stable 100 µs PLL Relock Time (3) 0 Voltage Regulator Delay (2) Power Supply Ramp Up (2) HRESET asserted 255 external memory Clock cycles (3) Time Reset Configuration Pins 9 external memory clock cycles setup time (4) VM = 1.4V HRESET Maximum rise time must be less than one external memory clock cycle (5) HRESET_CPU Notes: 1. Numbers associated with waveform separations correspond to caution numbers listed in Table 3, “Recommended Operating Conditions,” on page 12. 2. Refer to “Power Supply Voltage Sequencing” on page 42 for additional information. 3. Refer to Table 10 on page 25 for additional information on PLL Relock and reset signal assertion timing requirements. 4. Refer to Table 11 on page 26 for additional information on reset configuration pin setup timing requirements. 5. HRESET must transition from a logic 0 to a logic 1 in less than one SDRAM_SYNC_IN clock cycle for the device to be in the non-reset state. 6. HRESET_CPU negates 217 memory clock cycles after HRESET negates. 6 VM = 1.4V 13 2137C–HIREL–03/04 Figure 4 shows the undershoot and overshoot voltage of the memory interface of the PC107A. Figure 4. Overshoot/Undershoot Voltage 4V VIH GVdd +5% GVdd VIL Gnd Gnd - 0.3V Gnd - 1.0V Not to exceed 10% of tSDRAM_CLK Figure 5 and Figure 6 show the undershoot/overshoot voltage of the PCI interface for 3.3 and 5V signals, respectively. Figure 5. Maximum AC Waveforms for 3.3V Signaling 11 ns (Min) +7.1V Overvoltage Waveform 0V 4 ns (Max) 62.5 ns +3.6V Undervoltage Waveform -3.5V 7.1V p-to-p (Min) 7.1V p-to-p (Min) 4 ns (Max) 14 PC107A [Preliminary] 2137C–HIREL–03/04 PC107A [Preliminary] Figure 6. Maximum AC Waveforms for 3.3V Signaling 11 ns (Min) +7.1V Overvoltage Waveform 0V 4 ns (Max) 62.5 ns +3.6V Undervoltage Waveform – -3.5V 7.1V p-to-p (Min) 7.1V p-to-p (Min) 4 ns (Max) Thermal Information Package Characteristics Table 4 provides the package thermal characteristics for the PC107A. Table 4. FC-PBGA Package Thermal Characteristics Symbol RθJA RθJMA RθJMA RθJMA RθJB RθJC Notes: Characteristic(1) Junction-to-ambient natural convection (Single-layer board-1s) (1)(2) Value 30 26 25 22 20 < 0.1 Unit °C/W °C/W °C/W °C/W °C/W °C/W Junction-to-ambient natural convection(1)(3) (Four-layer board-2s2p) Junction-to-ambient (at 200 ft/min)(1)(3) (Single-layer board-1s) Junction-to-ambient (at 200 ft/min)(1)(3) (Four-layer board-2s2p) Junction-to-board(4) Junction-to-case (5) 1. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, airflow, power dissipation of other components on the board, and board thermal resistance. 2. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal. 3. Per JEDEC JESD51-6 with the board horizontal. 4. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 5. Thermal resistance between the die and the case top surface without thermal grease. 15 2137C–HIREL–03/04 Package Thermal Characteristics for HiTCE Table 5 provides the package thermal characteristics for the PC107 HiTCE. Table 5. Package Thermal Characteristics for HiTCE Package(1) Value Characteristic Thermal resistance junction to case(2) Thermal resistance junction to bottom of balls Thermal resistance junction to board, Jedec JESD51-8 (2s2p board) Thermal resistance junction to ambient, Jedec JESD51-2 (2s2p board = 2 signals + 2 power planes in board) Notes: PC107 HiTCE Unit 0.295 15.8 18.4 26.3 °C/Watt °C/Watt °C/Watt °C/Watt 1. Nominal values: means computed with nominal geometry and nominal thermal conductivities of materials as given in legend of each simulation results. 2. In this case thermal resistance junction to case is thermal resistance junction to top of Silicon die, and value almost not depend from substrate used for land grid array. Value depends strongly on heating zone size in Silicon chip assumption. In present simulations heating zone is 5.8 mm × 3.65 mm that is 42% of die size. Assuming the full die size as uniformly power dissipating is not realistic. Assuming 8.3 mm × 5.15 mm heating zone (85% of die surface) leads to 0.15°C/watt instead of 0.29°C/watt. 16 PC107A [Preliminary] 2137C–HIREL–03/04 PC107A [Preliminary] Thermal Management Information An estimation of the chip junction temperature, TJ, can be obtained from the equation: TJ = TA + (RθJA × PD) where TA = ambient temperature for the package (°C) RθJA = junction-to-ambient thermal resistance (°C/W) PD = power dissipation in the package (W) The junction-to-ambient thermal resistance is an industry-standard value that provides a quick and easy estimation of thermal performance. Table 4 has four junction-to-ambient thermal resistances (RθJA or RθJMA). Two test boards are used: single-signal-layer (1s) and four-layer boards with two internal planes (2s2p). Which value is closer to the application depends on the system board thermal resistance and the density of other highpower dissipation components. To illustrate the process, determine the junction temperature based on the values provided in Table 4 for an PC107 that is mounted on a board with many internal planes using arbitrary values. If the PC107 is doing most of the power dissipation, use RθJMA of 26°C/W given in Table 4. The ambient temperature near the device is 45°C. Suppose the total typical power dissipation at 100 MHz core frequency is 2.1W (see Table 6). The junction temperature is: TJ = 45 + (2.1 × 26) = 100°C. If this value is less than the maximum junction temperature noted in Table 2, the PC107 will not need a heat sink. If the ambient temperature is higher or the power dissipation is higher because of faster bus speed, the device will probably need a heat sink. The PC107 may need a heat sink depending on the system. This section provides thermal management information for the flip chip plastic ball grid array (FC-PBGA) package for air-cooled applications. Proper thermal control design is primarily dependent on the system-level design–the heat sink, airflow, and thermal interface material. To reduce the die-junction temperature, heat sinks may be attached to the package by several methods–spring clip to holes in the printed-circuit board or package, and mounting clip and screw assembly (see Figure 7); however, due to the potential large mass of the heat sink, attachment through the printed-circuit board is suggested. The force of the heat sink on the die should not exceed 6 lb. The heat sink surface must be flat without protrusions and must be parallel with the die as the heat sink is brought into contact to avoid chipping the edges of the die and the heat sink. Because of the small contact area of the heat sink, it is suggested that the mounting force be centered over the die. 17 2137C–HIREL–03/04 Figure 7. Package Exploded Cross-Sectional View with Several Heat Sink Options Heat Sink Heat Sink Clip FC-PBGA Package Thermal Interface Material Printed-Circuit Board The board designer can choose between several types of heat sinks to place on the PC107. There are several commercially available heat sinks for the PC107 provided by the listvendors: Aavid Thermalloy 80 Commercial St. Concord, NH 03301 Internet: www.aavidthermalloy.com Alpha Novatech 473 Sapena Ct. #15 Santa Clara, CA 95054 Internet: www.alphanovatech.com 603-224-9988 408-749-7601 International Electronic Research Corporation (IERC) 818-842-7277 413 North Moss St. Burbank, CA 91502 Internet: www.ctscorp.com Tyco Electronics Chip Coolers™ P.O. Box 3668 Harrisburg, PA 17105-3668 Internet: www.chipcoolers.com Wakefield Engineering 33 Bridge St. Pelham, NH 03076 Internet: www.wakefield.com 800-522-6752 603-635-5102 Ultimately, the final selection of an appropriate heat sink depends on many factors, such as thermal performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost. 18 PC107A [Preliminary] 2137C–HIREL–03/04 PC107A [Preliminary] Internal Package Conduction Resistance For the PBGA packaging technology, the intrinsic conduction thermal resistance paths are as follows: • • The die junction-to-case thermal resistance, The die junction-to-ball thermal resistance. Figure 8 depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board. Figure 8. C4 Package with Heat Sink Mounted to a Printed-Circuit Board External Re sistance Radiation Convection Heat Sink Thermal Interface Material Internal Resistance Die/Package Die Junction Package/Leads Printed-Circuit Board External Resistance Note: Radiation Convection The internal versus external package resistance For this PBGA package, heat is dissipated from the component via several concurrent paths. Heat is conducted through the silicon and may be removed to the ambient air by convection and/or radiation. In addition, a second, parallel heat flow path exists by conduction in parallel through the C4 bumps and the epoxy under-fill, to the plastic substrate for further convection cooling off the edges. Then from the plastic substrate, heat is conducted via the leads/balls to the next-level interconnect (printed-circuit board) whereupon the primary mode of heat transfer is by convection and/or radiation. 19 2137C–HIREL–03/04 Power Characteristics Table 6 provides the preliminary power consumption estimates for the PC107A. Power consumption on the PLL supply pin (AVDD) and the DLL supply pin (LAVDD) < 15 mW. This information is based on characterization data. Table 6. Power Consumption PCI_SYNC_IN/Core Frequency (MHz) 25/50 Mode Typical Doze Nap Sleep Notes: VDD Power 468 176 139 79 I/O Power 923 697 744 718 33/33 VDD Power 351 118 93 45 I/O Power 759 636 693 677 33/66 VDD Power 644 235 185 102 I/O Power 1087 800 420 841 66/100 VDD Power 933 350 276 138 I/O Power 1122 915 970 939 Unit mW mW mW mW Notes (1)(2) (1)(2) (1)(2) (1)(2) 1. Power is measured with VDD = 2.625V, GVDD = OVDD = BVDD = 3.45V at 0°C and one DIMM populated in test system. 2. All clock drivers enabled. 20 PC107A [Preliminary] 2137C–HIREL–03/04 PC107A [Preliminary] Electrical Characteristics Static Characteristics DC Electrical Specification Table 7 provides the DC electrical characteristics for the PC107A. At recommended operating conditions (see Table 3 on page 12) Table 7. DC Electrical Specifications Value Characteristics Input High Voltage Input Low Voltage Input High Voltage(2) Input High Voltage Input Low Voltage PCI_SYNC_IN Input High Voltage PCI_SYNC_IN Input Low Voltage Input Leakage Current for pins using DRV_PCI driver(4) Input Leakage Current all others(4) Output High Voltage(5) Output Low Voltage (5) (2) (2)(3) (1) This section provides the AC and DC electrical specifications and thermal characteristics for the PC107A. Conditions PCI only PCI only Symbol VIH VIL VIH VIH VIL CVIH CVIL Min 0.65*OVDD – 2.0 1.7 GND 2.4 GND – – 2.4 – 1.85 2.0 – – – (3) Max LVDD 0.3*OVDD – – 0.8 – 0.4 Unit V V V V V V V µA µA V V V V V V All other pins (GVDD = 3.3V) All other pins (BVDD = 2.5V) All inputs except PCI_SYNC_IN 0.5V ≤ VIN ≤ 2.7V at LVDD = 4.75 LVDD = 3.6V (GVDD ≤ 3.465) IOH = Driver Dependent(5) (GVDD = 3.3V) IOL = Driver Dependent (5) (5) IL IL VOH VOL VOH VOH VOL VOL CIN ± 70 ± 10 – 0.4 – – 0.4 0.3 7.0 (GVDD = 3.3V) Output High Voltage(5) IOH = Driver Dependent (BVDD = 2.5V) All outputs except CPU_CLKS[0-2] IOH = Driver Dependent(5) (BVDD = 2.5V) CPUCLKS[0-2] Only IOL = Driver Dependent(5) (BVDD = 2.5V) All outputs except CPU_CLK[0-2] IOL = Driver Dependent(5) (BVDD = 2.5V) CPU_CLK[0-2] Only VIN = 0V, f = 1 MHz Output Low Voltage(5) Capacitance(6) Notes: 1. These specifications are for the default driver strengths indicated in Table 8 on page 22. 2. See Figure 23 on page 35 for pins with internal pull-up resistors. 3. The minimum Input high voltage is not compliant with the PCI Local Bus Specification (Rev 2.1) which specifies 0.5*OVDD for minimum input high voltage. 4. Leakage current is measured on input pins and on output pins in the high impedance state. The leakage current is measured for nominal OVDD/LVDD and VDD or both OvDD/LVDD and VDD must vary in the same direction. 5. See Table 8 on page 22 for the typical drive capability of a specific signal pin based upon the type of output driver associated with that pin as listed in Table 1 on page 5. 6. Capacitance is periodically sampled rather than 100% tested. 21 2137C–HIREL–03/04 Output Driver Characteristics Table 8 provides information on the characteristics of the output drivers referenced in Table 1 on page 5. The values are from the PC107A IBIS model (v1.1) and are not tested, for additional detailed information see the complete IBIS model listing at http://www.motorola.com/semiconductor. Table 8. Drive Capability of PC107A Output Pins Driver Type Programmable Output Impedance (Ohms) 20 DRV_CPU 40 (default) Supply Voltage BVDD = 3.3V BVDD = 2.5V BVDD = 3.3V BVDD = 2.5V 25 DRV_PCI 50 (default) 8 (default) DRV_MEM_ADDR DRV_PCI_CLK 13.3 20 40 20 (default) DRV_MEM_DATA Notes: 1. OVDD = 3.3V OVDD = 3.3V GVDD = 3.3V GVDD = 3.3V GVDD = 3.3V GVDD = 3.3V GVDD = 3.3V IOH 36.6 21.4 18.6 10.8 12.0 6.1 89.0 55.8 36.6 18.6 36.6 IOL 18.1 15.6 9.2 7.9 12.4 6.3 42.3 26.4 18.1 9.2 18.1 Unit mA mA mA mA mA mA mA mA mA mA mA Notes (2)(5) (3)(6)(7) (2)(5) (3)(6)(7) (1)(4) (1)(4) (2)(5) (2)(5) (2)(5) (2)(5) (2)(5) 2. 3. 4. 5. 6. 7. (2)(5) 40 GVDD = 3.3V 18.6 9.2 mA For DRV_PCI, IOH read from the IBIS listing in the pull-up mode, I(Min) column, at the 0.33V label by interpolating between the 0.3V and 0.4V table entries’ current values which corresponds to the PCI VOH = 2.97 = 0.9*OVDD (OVDD = 3.3V) where Table Entry Voltage = OVDD - PCI VOH. For all others with GVDD or BVDD = 3.3V, IOH read from the IBIS listing in the pull-up mode, I(Min) column, at the 0.9V table entry which corresponds to the VOH = 2.4V where Table Entry Voltage = G/BVDD - VOH. For all others with BVDD = 2.5V, IOH read from the IBIS listing in the pull-up mode, I(Min) column, at the 0.65V table entry by interpolating between the 0.6V and 0.7V table entries’ current values which corresponds to the VOH = 1.85V where Table Entry Voltage = BVDD - VOH. For DRV_PCI, IOL read from the IBIS listing in the pull-down mode, I(Min) column, at 0.33V = PCI VOL = 0.1*OVDD (OVDD = 3.3V) by interpolating between the 0.3V and 0.4V table entries. For all others with GVDD or BVDD = 3.3V, IOL read from the IBIS listing in the pull-down mode, I(Min) column, at the 0.4V table entry. For all others with BVDD = 2.5V, IOL read from the IBIS listing in the pull-down mode, I(Min) column, at the 0.4V table entry. For BVDD = 2.5V, the IOH and IOL values are estimated from the io_mem_data_XX_2.5 and io_mem_addr_XX_2.5 sections of the IBIS model where XX = driver output impedance (20 or 40Ω). 22 PC107A [Preliminary] 2137C–HIREL–03/04 PC107A [Preliminary] Dynamic Electrical Characteristics Clock AC Specifications Table 9 provides the clock AC timing specifications as defined in Section. At recommended operating conditions (see Table 3 on page 12) with GVDD = 3.3V ± 5% and LVDD = 3.3 ±0.3V Table 9. Clock AC Timing Specifications Num 1a 1b 2, 3 4 5a 5b 7 9a 9b 9c 9d 10 15 16 17 18 19 20 21 Notes: Characteristics and Conditions (1) Frequency of Operation (PCI_SYNC_IN) PCI_SYNC_IN Cycle Time PCI_SYNC_IN Rise and Fall Times PCI_SYNC_IN Duty Cycle Measured at 1.4V PCI_SYNC_IN Pulse Width High Measured at 1.4V PCI_SYNC_IN Pulse Width Low Measured at 1.4V PCI_SYNC_IN Jitter PCI_CLK[0–4] Skew (Pin to Pin) SDRAM_CLK[0–3] Skew (Pin to Pin) CPU_CLK[0–2] Skew (Pin to Pin) SDRAM_CLK[0–3]/CPU_CLK[0–2] Jitter Internal PLL Relock Time DLL lock range with DLL_STANDARD = 1 (default) DLL lock range with DLL_STANDARD = 0 Frequency of Operation (OSC_IN) OSC_IN Cycle Time OSC_IN Rise and Fall Times OSC_IN Duty Cycle Measured at 1.4V OSC_IN Frequency Stability 1. 2. 3. 4. 5. Min 12.5 80 – 40 6 6 – – – – – – Max 66 15 2.0 60 9 9 < 150 500 350 350 150 100 Unit MHz ns ns % ns ns ps ps ps ps ps µs ns ns MHz ns ns % ppm (3)(4)(6) (7) (7) (8) (8) (5) (3) (3) Notes (8) (8) (2) See Figure 11 on page 24 See Figure 12 on page 25 12.5 80 – 40 – 66 15 5 60 100 These specifications are for the default driver strengths indicated in Table 8 on page 22. Rise and fall times for the PCI_SYNC_IN input are measured from 0.4V to 2.4V. Specification value at maximum frequency of operation. Relock time is guaranteed by design and characterization. Relock time is not tested. Rise and fall times for the OSC_IN input is guaranteed by design and characterization. OSC_IN input rise and fall times are not tested. 6. Relock timing is guaranteed by design. PLL-relock time is the maximum amount of time required for PLL lock after a stable VDD and PCI_SYNC_IN are reached during the reset sequence. This specification also applies when the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL-relock time during the reset sequence. 7. DLL_STANDARD is bit 7 of the PMC2 register . N is a non-zero integer (1 or 2). Tclk is the period of one SDRAM_SYNC_OUT clock cycle in ns. tloop is the propagation delay of the DLL synchronization feedback loop (PC board runner) from SDRAM_SYNC_OUT to SDRAM_SYNC_IN in ns; 6.25 inches of loop length (unloaded PC board runner) corresponds to approximately 1 ns of delay. See Figure 12 on page 25 for DLL locking ranges. 8. See Table 19 on page 41 for PCI_SYNC_IN input frequency range for specific PLL_CFG[0–3] settings. 23 2137C–HIREL–03/04 Figure 9 shows the PCI_SYNC_IN Input Clock Timing Diagram, Figure 10 illustrates how Table 9 clock specifications relate to the PC107A Clocking diagram, and Figure shows the DLL Locking Range Loop Delay vs. Frequency of Operation. Figure 9. PCI_SYNC-IN Input Clock Timing Diagram 1 5a 5b 2 3 CVIH PCI_SYNC_IN VM VM VM CVIL VM = Midpoint Voltage (1.4V) Figure 10. Clock Subsystem Block Diagram MPC107 Specs. 15,16 DLL Spec. 10 CPU_CLK[0:2] SDRAM_CLK[0:3] Specs. 9b,9d SDRAM_SYNC_OUT SDRAM_SYNC_IN sys_logic_clk PCI_SYNC_IN PCI_SYNC_OUT OSC_IN Specs. 17 - 23 Core Logic PCI_CLK[0:4] Spec. 9a Specs. 1 - 7 Specs. 9c,9d PLL Note: Specification numbers are from Table 9. Figure 11. DLL Locking Range Loop Delay (DLL_Standard = 0) 50 Tclk SDRAM_SYNC_OUT Period (ns) 45 40 35 30 25 20 15 10 5 0 0 5 10 15 Tloop Propagation Delay Time (ns) Tclk = 0.7 x Tloop + 3.96 ns Tclk = 2.2 x Tloop + 11.88 ns Tclk = 0.6 x Tloop + 9.27 ns Tclk = 1.8 x Tloop + 27.9 ns 24 PC107A [Preliminary] 2137C–HIREL–03/04 PC107A [Preliminary] Figure 12. DLL Locking Range Loop Delay (DLL_Standard = 1) 50 Tclk SDRAM_SYNC_OUT Period (ns) 45 40 35 30 25 20 15 10 5 0 0 Tclk = 0.55 x Tloop + 2.97 ns Tclk = 0.9 x Tloop + 13.95 ns Tclk = 1.1 x Tloop + 5.94 ns Tclk = 0.45 x Tloop + 6.98 ns 5 10 15 Tloop Propagation Delay Time (ns) Operating Frequency This section provides the AC electrical characteristics for the PC107A. After fabrication, functional parts are sorted by maximum core frequency as shown in Figure 10 and “Clock AC Specifications” on page 23 and tested for conformance to the AC specifications for that frequency. The core frequency is determined by the bus (PCI_SYNC_IN) clock frequency and the settings of the PLL_CFG[0–3] signals. Parts are sold by maximum processor core frequency; see “Ordering Information” on page 46. Table 10 provides the operating frequency information for the PC107A. At recommended operating conditions (see Table 3 on page 12) with LVDD = 3.3 ±0.3V. Table 10. Operating Frequency 66 MHz Characteristic (1) 100 MHz Min 25 Max 100 Unit MHz MHz Min 25 Max 66 Core (memory bus/processor bus) frequency PCI input frequency (PCI_SYNC_IN) Note: 12.5 – 66 1. Caution: The PCI_SYNC_IN frequency and PLL_CFG[0–3] settings must be chosen such that the resulting peripheral logic/memory bus frequency, CPU (core) frequency, and PLL (VCO) frequencies do not exceed their respective maximum or minimum operating frequencies. Refer to the PLL_CFG[0–3] signal description in “Clock Relationships Choice” on page 41 for valid PLL_CFG[0–3] settings and PCI_SYNC_IN frequencies. 25 2137C–HIREL–03/04 Input AC Timing Specifications Table 11 provides the input AC timing specifications. See Figure 13 on page 27 and Figure 14 on page 27. At recommended operating conditions (see Table 3 on page 12) with GVDD = 3.3V ±5% and LVDD = 3.3 ±0.3V Table 11. Input AC Timing Specifications Num 10a 10b 10c 10d 10e 10f 11a1 11a2 11a3 11b Notes: Characteristics PCI Input Signals Valid to PCI_SYNC_IN (Input Setup) Memory Interface Signals Valid to SDRAM_SYNC_IN (Input Setup) Epic, Misc. Debug Input Signals Valid to SDRAM_SYNC_IN (Input Setup) Two-wire interface Input Signals Valid to SDRAM_SYNC_IN (Input Setup) Mode select Inputs Valid to HRESET (Input Setup) 60x Processor Interface Signals Valid to SDRAM_SYNC_IN (Input Setup) PCI_SYNC_IN (SDRAM_SYNC_IN) to Inputs Invalid (Input Hold) Memory Interface Signals SDRAM_SYNC_IN to Inputs Invalid (Input Hold) 60x Processor Interface Signals SDRAM_SYNC_IN to Inputs Invalid (Input Hold) HRESET to Mode select Inputs Invalid (Input Hold) Min 3.0 2.0 2.0 2.0 9*tCLK 2.0 1.0 0.5 0 0 Max – – – – – – – – – – Unit ns ns ns ns ns ns ns ns ns ns Notes (2)(3) (1)(3) (1)(3) (1)(3) (1)(3)(5) (1)(3) (2)(3) (1)(3) (1)(3) (1)(3)(5) 1. All memory, processor and related interface input signal specifications are measured from the TTL level (0.8 or 2.0V) of the signal in question to the VM = 1.4V of the rising edge of the memory bus clock, SDRAM_SYNC_IN. SDRAM_SYNC_IN is the same as PCI_SYNC_IN in 1:1 mode, but is twice the frequency in 2:1 mode (processor/memory bus clock rising edges occur on every rising and falling edge of PCI_SYNC_IN). See Figure 13. 2. All PCI signals are measured from OVDD/2 of the rising edge of PCI_SYNC_IN to 0.4*OVDD of the signal in question for 3.3 V PCI signaling levels. See Figure 14. 3. Input timings are measured at the pin. 4. tCLK is the time of one SDRAM_SYNC_IN clock cycle. 5. All mode select input signals specifications are measured from the TTL level (0.8 or 2.0V) of the signal in question to the VM = 1.4V of the rising edge of the HRESET signal. See Figure 15 on page 27. 26 PC107A [Preliminary] 2137C–HIREL–03/04 PC107A [Preliminary] Figure 13. Input – Output Timing Diagram Referenced to SDRAM_SYNC_IN PCI_SYNC_IN SDRAM_SYNC_IN shown in 2:1 mode 10b-d VM VM VM 11a 12b-d 13b 14b 2.0V MEMORY INPUTS/OUTPUTS 0.8V Input Timing 2.0V 0.8V Output Timing VM = Midpoint Voltage (1.4V) Figure 14. Input – Output Timing Diagram Referenced to PCI_SYNC_IN PCI_SYNC_IN OVdd/2 OVdd/2 OVdd/2 10a 11a 12a 13a 14a 0.615*OVdd 0.4*OVdd 0.285*OVdd PCI INPUTS/OUTPUTS Input Timing Figure 15. Input Timing Diagram for Mode Select Signals Output Timing HRESET 10e VM 11b MODE PINS 2.0V 0.8V VM = Midpoint Voltage (1.4V) 27 2137C–HIREL–03/04 Output AC Timing Specification Table 12 provides the processor bus AC timing specifications for the PC107A. See Figure 13 on page 27 and Figure 14 on page 27. At recommended operating conditions (see Table 3 on page 12) with LVDD = 3.3 ±0.3V Table 12. Output AC Timing Specifications Num Characteristics(3)(6) PCI_SYNC_IN to Output Valid, 66 MHz PCI, with SDMA4 pulleddown to logic 0 state. See Figure 17. 12a PCI_SYNC_IN to Output Valid, 33 MHz PCI, with SDMA4 in the default logic 1 state. See Figure 17. 12b 12b1 12b2 12c 12d 12e Memory Interface Signals, SDRAM_SYNC_IN to Output Valid Memory Interface Signal: CKE (100 MHz Device), SDRAM_SYNC_IN to Output Valid Memory Interface Signal: CKE (66 MHz Device), SDRAM_SYNC_IN to Output Valid Epic, Misc. Debug Signals, SDRAM_SYNC_IN to Output Valid Two-wire interface, SDRAM_SYNC_IN to Output Valid 60x Processor Interface Signals, SDRAM_SYNC_IN to Output Valid Output Hold, 66 MHz PCI, with SDMA4 and SDMA3 pulled-down to logic 0 states. See Table 13. 13a Output Hold, 33 MHz PCI, with SDMA4 in the default logic 1 state and SDMA3 pulled-down to logic 0 state. See Table 13. 13b 14a 14b Notes: Output Hold (For All Others) PCI_SYNC_IN to Output High Impedance (Toff for PCI) SDRAM_SYNC_IN to Output High Impedance (For All Others) 2.0 1 – – 14.0 4.0 – ns ns ns ns (2)(4)(5) Min – – – – – – – – 1.0 Max 6.0 11.0 5.5 5.5 6.0 9.0 5.0 5.5 – Unit ns ns ns ns ns ns ns ns ns Notes (2)(4) (2)(4) (1) (1) (1) (1) (1) (1) (2)(4)(5) (1) (2)(4) (1) 1. All memory and related interface output signal specifications are specified from the VM = 1.4V of the rising edge of the memory bus clock, SDRAM_SYNC_IN to the TTL level (0.8 or 2.0V) of the signal in question. SDRAM_SYNC_IN is the same as PCI_SYNC_IN in 1:1 mode, but is twice the frequency in 2:1 mode (processor/memory bus clock rising edges occur on every rising and falling edge of PCI_SYNC_IN). See Figure 13 on page 27. 2. All PCI signals are measured from OVDD/2 of the rising edge of PCI_SYNC_IN to 0.285*OVDD or 0.615*OVDD of the signal in question for 3.3V PCI signaling levels. See Figure 14 on page 27. 3. All output timings assume a purely resistive 50Ω load (See Figure 16 on page 28). Output timings are measured at the pin; time-of-flight delays must be added for trace lengths, vias, and connectors in the system. 4. PCI Bussed signals are composed of the following signals: LOCK, IRDY, C/BE[0–3], PAR, TRDY, FRAME, STOP, DEVSEL, PERR, SERR, AD[0–31], REQ[4–0], GNT[4–0], IDSEL, INTA. 5. PCI hold times can be varied, see “PCI Signal Output Hold Timing” on page 29 for information on programmable PCI output hold times. The values shown for item 13a are for PCI compliance. 6. These specifications are for the default driver strengths indicated in Table 8 on page 22. Figure 16. AC Test Load for the PC107A Output measurements are made at the device pin. OUTPUT PIN OVdd/2 RL = 50Ω Z0 = 50Ω 28 PC107A [Preliminary] 2137C–HIREL–03/04 PC107A [Preliminary] PCI Signal Output Hold Timing In order to meet minimum output hold specifications relative to PCI_SYNC_IN for both 33 MHz and 66 MHz PCI systems, the PC107A has a programmable output hold delay for PCI signals. The initial value of the output hold delay is determined by the values on the SDMA4 and SDMA3 reset configuration signals. Further output hold delay values are available by programming the PCI_HOLD_DEL value of the PMCR2 configuration register. Table 13 describes the bit values for the PCI_HOLD_DEL values in PMCR2. Table 13. Power Management Configuration Register 2-0x72 Bit 6–4 Name PCI_HOLD_DEL Reset value xx0 Description PCI output hold delay values relative to PCI_SYNC_IN. The initial values of bits 6 and 5 are determined by the reset configuration pins SDMA4 and SDMA3, respectively. As these two pins have internal pull-up resistors, the default value after reset is 0b110. While the minimum hold times are guaranteed at shown values, changes in the actual hold time can be made by incrementing or decrementing the value in these bit fields of this register via software or hardware configuration. The increment is in approximately 400 picosecond steps. Lowering the value in the three bit field decreases the amount of output hold available. 000 66 MHz PCI. Pull-down SDMA4 configuration pin with a 2 kΩ or less value resistor. This setting guarantees the minimum output hold, item 13a, and the maximum output valid, item 12a, times as specified in Figure 14 are met for a 66 MHz PCI system. See Figure 17 on page 30. 001 010 011 100 33 MHz PCI. This setting guarantees the minimum output hold, item 13a, and the maximum output valid, item 12a, times as specified in Figure 14 are met for a 33 MHz PCI system. See Figure 17 on page 30. 101 110 (Default if reset configuration pins left unconnected) 111 29 2137C–HIREL–03/04 Figure 17. PCI_HOLD_DEL Effect on Output Valid and Hold Time PCI_SYNC_IN OVdd/2 OVdd/2 12a, 8 ns for 33 MHz PCI PCI_HOLD_DEL = 100 13a, 2 ns for 33 MHz PCI PCI_HOLD_DEL = 100 PCI INPUTS/OUTPUTS 33 MHz PCI 12a, 6 ns for 66 MHz PCI PCI_HOLD_DEL = 000 13a, 1 ns for 66 MHz PCI PCI_HOLD_DEL = 000 PCI INPUTS/OUTPUTS 66 MHz PCI As PCI_HOLD_DEL values decrease PCI INPUTS and OUTPUTS As PCI_HOLD_DEL values increase Diagram Not to Scale OUTPUT VALID OUTPUT HOLD 30 PC107A [Preliminary] 2137C–HIREL–03/04 PC107A [Preliminary] Two-wire Interface AC Timing Specifications Table 14 provides the two-wire interface input AC timing specifications for the PC107A. At recommended operating conditions (see Table 3 on page 12) with LVDD = 3.3 ±0.3V Table 14. Two-wire Interface Input AC Timing Specifications Num 1 Characteristics Start condition hold time Clock low period (The time before the PC107A will drive SCL low as a transmitting slave after detecting SCL low as driven by an external master) Min 4.0 8.0 + (16 × 2FDR[4:2]) × (5 4({FDR[5],FDR[1]} == b’10) 3({FDR[5],FDR[1]} == b’11) 2({FDR[5],FDR[1]} == b’00) 1({FDR[5],FDR[1]} == b’01)) – 0 – 5.0 3.0 4.0 4.0 Max – Unit CLKs Notes (1)(2) 2 – CLKs (1)(2)(4)(5) 3 4 5 6 SCL/SDA rise time (from 0.5V to 2.4V) Data hold time SCL/SDA fall time (from 2.4V to 0.5V) Clock high period (Time needed to either receive a data bit or generate a START or STOP) Data setup time Start condition setup time (for repeated start condition only) Stop condition setup time 1 – 1 – – – – ms ns mS CLKs ns CLKs CLKs (1)(2)(5) (2) 7 8 9 Notes: (3) (1)(2) (1)(2) 1. Units for these specifications are in SDRAM_CLK/CPU_CLK units. 2. The actual values depend on the setting of the Digital Filter Frequency Sampling Rate (DFFSR) bits in the Frequency Divider Register two-wire interface FDR. Therefore, the noted timings in the above table are all relative to qualified signals. The qualified SCL and SDA are delayed signals from what is seen in real time on the two-wire interface bus. The qualified SCL, SDA signals are delayed by the SDRAM_CLK/CPU_CLK clock times DFFSR times 2 plus 1 SDRAM_CLK/CPU_CLK clock. The resulting delay value is added to the value in the table (where this note is referenced). See Figure 19 on page 34. 3. Timing is relative to the Sampling Clock (not SCL). 4. FDR[x] refers to the Frequency Divider Register I2CFDR bit x. 5. Input clock low and high periods in combination with the FDR value in the Frequency Divider Register (I2CFDR) determine the maximum two-wire interface input frequency. See Figure 19 on page 34. 31 2137C–HIREL–03/04 Table 15 provides the two-wire interface Frequency Divider Register (I2CFDR) information for the PC107A. At recommended operating conditions (see Table 3 on page 12) with LVDD = 3.3V ± 5% Table 15. PC8240 Maximum Two-wire Interface Input Frequency Max Two-wire Interface Input Frequency(1) SDRAM_CLK/ CPU_CLK at 25 MHz 862 555 409 324 229 177 121 92 62 47 32 24 16 12 8 6 4 3 SDRAM_CLK/ CPU_CLK at 33 MHz 1.13 MHz 733 540 428 302 234 160 122 83 62 42 31 21 16 10 8 5 4 SDRAM_CLK/ CPU_CLK at 50 MHz 1.72 MHz 1.11 MHz 819 649 458 354 243 185 125 95 64 48 32 24 16 12 8 6 SDRAM_CLK/ CPU_CLK at 100 MHz 3.44 MHz 2.22 MHz 1.63 MHz 1.29 MHz 917 709 487 371 251 190 128 96 64 48 32 24 16 12 FDR Hex(2) 20, 21 22, 23, 24, 25 0, 1 2, 3, 26, 27, 28, 29 4, 5 6, 7, 2A, 2B, 2C, 2D 8, 9 A, B, 2E, 2F, 30, 31 C, D E, F, 32, 33, 34, 35 10, 11 12, 13, 36, 37, 38, 39 14, 15 16, 17, 3A, 3B, 3C, 3D 18, 19 1A, 1B, 3E, 3F 1C, 1D 1E, 1F Notes: Divider (Dec)(2) 160, 192 224, 256, 320, 384 288, 320 384, 448, 480, 512, 640, 768 576, 640 768, 896, 960, 1024, 1280, 1536 1152, 1280 1536, 1792, 1920, 2048, 2560, 3072 2304, 2560 3072, 3584, 3840, 4096, 5120, 6144 4608, 5120 6144, 7168, 7680, 8192, 10240, 12288 9216, 10240 12288, 14336, 15360, 16384, 20480, 24576 18432, 20480 24576, 28672, 30720, 32768 36864, 40960 49152, 61440 1. Values are in kHz unless otherwise specified. 2. FDR Hex and Divider (Dec) values are listed in corresponding order. 3. Multiple Divider (Dec) values will generate the same input frequency but each Divider (Dec) value will generate a unique output frequency as shown in Table 16 on page 33. 32 PC107A [Preliminary] 2137C–HIREL–03/04 PC107A [Preliminary] Table 16 provides the two-wire interface output AC timing specifications for the PC107A. At recommended operating conditions (see Table 3 on page 12) with GVDD = 3.3V ± 5% and LVDD = 3.3 ±0.3V Table 16. Two-wire Interface Output AC Timing Specifications Num 1 2 3 Characteristics Start condition hold time Clock low period SCL/SDA rise time (from 0.5V to 2.4V) Min (FDR[5] == 0) × (DFDR/16) / 2N + (FDR[5] == 1) × (DFDR/16) / 2M DFDR / 2 – 8.0 + (16 × 2FDR[4:2]) × (5 4({FDR[5],FDR[1]} == b’10) 3({FDR[5],FDR[1]} == b’11) 2({FDR[5],FDR[1]} == b’00) 1({FDR[5],FDR[1]} == b’01)) – DFDR / 2 (DFDR / 2) - (Output data hold time) DFDR + (Output start condition hold time) 4.0 Max – – – Unit CLKs CLKs mS Notes (1)(2)(5) (1)(2)(5) (3) 4 Data hold time – CLKs (1)(2)(5) 5 6 7 8 9 Notes: SCL/SDA fall time (from 2.4V to 0.5V) Clock high time Data setup time (PC107A as a master only) Start condition setup time (for repeated start condition only) Stop condition setup time