PC7447AMGH1420LB

Features • • • • • • • • • • • • • • • 3000 Dhrystone 2.1 MIPS at 1.3 GHz Selectable Bus Clock (30 CPU Bus Dividers up to 28x) Selectable MPx/60x Interface Voltage (1.8V, 2.5V) PD Typically 18W at 1.33 GHz at VDD = 1.3V; 8.0W at 1 GHz at VDD = 1.1V Full Operating Conditions Nap, Doze and Sleep Power Saving Modes Superscalar (Four Instructions Fetched Per Clock Cycle) 4 GB Direct Addressing Range Virtual Memory: 4 Hexabytes (252) 64-bit Data and 36-bit Address Bus Interface Integrated L1: 32 KB Instruction and 32 KB Data Cache Integrated L2: 512 KB 11 Independent Execution Units and 3 Register Files Write-back and Write-through Operations fINT Max = 1.33 GHz (1.42 GHz to be Confirmed) fBUS Max = 133 MHz/166 MHz PowerPC® 7447A RISC Microprocessor PC7447A Preliminary Description The PC7447A host processor is a high-performance, low-power, 32-bit implementations of the PowerPC Reduced Instruction Set Computer (RISC) architecture combined with a full 128-bit implementation of Freescale®’s AltiVec™ technology. This microprocessor is ideal for leading-edge embedded computing and signal processing applications. The PC7447A features 512 KB of on-chip L2 cache. The PC7447A microprocessor has no backside L3 cache, allowing for a smaller package designed as a pin-for-pin replacement for the PC7447 microprocessor. This device benefits from a silicon-on-insulator (SOI) CMOS process technology, engineered to help deliver tremendous power savings without sacrificing speed. A low-power version of the PC7447A microprocessor is also available. Figure 1-1 shows a block diagram of the PC7447A. The core is a high-performance superscalar design supporting a double-precision floating-point unit and a SIMD multimedia unit. The memory storage subsystem supports the MPX bus protocol and a subset of the 60x bus protocol to the main memory and other system resources. Note that the PC7447A is a footprint-compatible, drop-in replacement in a PC7447 application if the core power supply is 1.3V. Screening • Full Military Temperature Range (Tj = -55°C, +125°C) • Industrial Temperature Range (Tj = -40°C, +110°C) GH suffix HITCE 360 Rev. 5387B–HIREL–07/05 Figure 1-1. 1. Block Diagram 2 Additional Features • Time Base Counter/Decrementer Clock Multiplier JTAG/COP Interface Thermal/Power Management Performance Monitor Dynamic Frequency Switching (DFS) Temperature Dioder Completion Unit 96-Bit (3 Instructions) Completion Queue (16-Entry) Instruction Unit Branch Processing Unit BTIC (128-Entry) BHT (2048-Entry) CTR IBAT Array LR Dispatch Unit Data MMU SRs (Original) VR Issue (4-Entry/2-Issue) GPR Issue (6-Entry/3-Issue) FPR Issue (2-Entry/1-Issue) 128-Entry DTLB Tags Fetcher Instruction Queue (12-Word) Instruction MMU SRs (Shadow) 128-Entry ITLB 128-Bit (4 Instructions) PC7447A [Preliminary] 5387B–HIREL–07/05 Tags 32-Kbyte I Cache PC7447A Microprocessor Block Diagram 32-Kbyte D Cache DBAT Array Reservation Stations (2-Entry) EA Completes up to three instructions per clock VR File 16 Rename Buffers Reservation Reservation Reservation Reservation Station Station Station Station Vector Touch Queue GPR File 16 Rename Buffers Load/Store Unit Vector Touch Engine + (EA Calculation) Finished Stores L1 Castout PA FPR File 16 Rename Buffers Reservation Stations (2) Reservation Stations (2) Reservation Station Integer Unit 2 x÷ Integer Unit 1 (3) + 32-Bit FloatingPoint Unit + x÷ FPSCR L1 Push Completed Stores Vector Permute Unit Vector Integer Unit 2 Vector Integer Unit 1 Vector FPU 128-Bit 128-Bit 32-Bit 32-Bit Load Miss 64-Bit 64-Bit Memory Subsystem L1 Store Queue (LSQ) L1 Load Queue (LLQ) L1 Load Miss (5) L2 Prefetch (3) Instruction Fetch (2) Cacheable Store Request (1) L1 Castouts (4) L2 Store Queue (L2SQ) Snoop Push/ Interventions 512-Kbyte Unified L2 Cache Controller L1 Service Queues Line Block 0 (32-Byte) Block 1 (32-Byte) Tags Status Status System Bus Interface Load Queue (11) Bus Store Queue Castout Queue (9) / Push Queue (10)2 Bus Accumulator Notes: The castout queue and push queue share resources such for a combined total of entries. The castout queue itself is limited to 9 entries, ensuring 1 entry will be available for a push. 36-bit Address Bus 64-bit Data Bus PC7447A [Preliminary] 2. General Parameters Table 2-1 provides a summary of the general parameters of the PC7477A. Table 2-1. Parameter Technology Die size Transistor count Logic design Packages Core power supply I/O power supply Device Parameters Description 0.13 µm CMOS, nine-layer metal 8.51 mm × 9.86 mm 48.6 million Fully-static Surface mount 360 ceramic ball grid array (HITCE) 1.3V ±50 mV DC nominal 1.8V ±5% DC, or 2.5V ±5% DC 3. Features This section summarizes features of the PC7447A implementation of the PowerPC architecture. Major features of the PC7447A are as follows: • High-performance, superscalar microprocessor – Up to four instructions can be fetched from the instruction cache at a time – Up to 12 instructions can be in the instruction queue (IQ) – Up to 16 instructions can be at some stage of execution simultaneously – Single-cycle execution for most instructions – One instruction per clock cycle throughput for most instructions – Seven-stage pipeline control • Eleven independent execution units and three register files – Branch processing unit (BPU) features static and dynamic branch prediction 128-entry (32-set, four-way set-associative) branch target instruction cache (BTIC), a cache of branch instructions that have been encountered in branch/loop code sequences. If a target instruction is in the BTIC, it is fetched into the instruction queue a cycle sooner than it can be made available from the instruction cache. Typically, a fetch that hits the BTIC provides the first four instructions in the target stream. 2048-entry branch history table (BHT) with two bits per entry for four levels of prediction: not taken, strongly not taken, taken, and strongly taken Up to three outstanding speculative branches Branch instructions that do not update the count register (CTR) or link register (LR) are often removed from the instruction stream 3 5387B–HIREL–07/05 Eight-entry link register stack to predict the target address of Branch Conditional to Link Register (BCLR) instructions – Four integer units (IUs) that share 32 GPRs for integer operands Three identical IUs (IU1a, IU1b, and IU1c) can execute all integer instructions except multiply, divide, and move to/from special-purpose register instructions. IU2 executes miscellaneous instructions including the CR logical operations, integer multiplication and division instructions, and move to/from special-purpose register instructions. – Five-stage FPU and a 32-entry FPR file Fully IEEE 754-1985-compliant FPU for both single- and double-precision operations Supports non-IEEE mode for time-critical operations Hardware support for denormalized number Thirty-two 64-bit FPRs for single- or double-precision operands – Four vector units and 32-entry vector register file (VRs) Vector permute unit (VPU) Vector integer unit 1 (VIU1) handles short-latency AltiVec™ integer instructions, such as vector add instructions (for example, vaddsbs, vaddshs, and vaddsws). Vector integer unit 2 (VIU2) handles longer-latency AltiVec integer instructions, such as vector multiply add instructions (for example, vmhaddshs, vmhraddshs, and vmladduhm). Vector floating-point unit (VFPU) – Three-stage load/store unit (LSU) Supports integer, floating-point, and vector instruction load/store traffic Four-entry vector touch queue (VTQ) supports all four architectures of the AltiVec data stream operations Three-cycle GPR and AltiVec load latency (byte, half word, word, vector) with onecycle throughput Four-cycle FPR load latency (single, double) with one-cycle throughput No additional delay for misaligned access within double-word boundary 4 PC7447A [Preliminary] 5387B–HIREL–07/05 PC7447A [Preliminary] Dedicated adder calculates effective addresses (EAs) Supports store gathering Performs alignment, normalization, and precision conversion for floating-point data Executes cache control and TLB instructions Performs alignment, zero padding, and sign extension for integer data Supports hits under misses (multiple outstanding misses) Supports both big- and little-endian modes, including misaligned little-endian accesses • Three issue queues, FIQ, VIQ, and GIQ, can accept as many as one, two, and three instructions, respectively, in a cycle. Instruction dispatch requires the following: – Instructions can only be dispatched from the three lowest IQ entries: IQ0, IQ1, and IQ2 – A maximum of three instructions can be dispatched to the issue queues per clock cycle – Space must be available in the CQ for an instruction to dispatch (this includes instructions that are assigned a space in the CQ but not in an issue queue) • Rename buffers – 16 GPR rename buffers – 16 FPR rename buffers – 16 VR rename buffers • Dispatch unit – Decode/dispatch stage fully decodes each instruction • Completion unit – The completion unit retires an instruction from the 16-entry completion queue (CQ) when all instructions ahead of it have been completed, the instruction has finished execution, and no exceptions are pending – Guarantees sequential programming model (precise exception model) – Monitors all dispatched instructions and retires them in order – Tracks unresolved branches and flushes instructions after a mispredicted branch – Retires as many as three instructions per clock cycle • Separate on-chip L1 instruction and data caches (Harvard Architecture) – 32-Kbyte, eight-way set-associative instruction and data caches – Pseudo least-recently-used (PLRU) replacement algorithm – 32-byte (eight-word) L1 cache block – Physically indexed/physical tags – Cache write-back or write-through operation programmable on a per-page or perblock basis 5 5387B–HIREL–07/05 – Instruction cache can provide four instructions per clock cycle; data cache can provide four words per clock cycle – Caches can be disabled in software – Caches can be locked in software – MESI data cache coherency maintained in hardware – Separate copy of data cache tags for efficient snooping – Parity support on cache and tags – No snooping of instruction cache except for icbi instruction – Data cache supports AltiVec LRU and transient instructions – Critical double- and/or quad-word forwarding is performed as needed. Critical quadword forwarding is used for AltiVec loads and instruction fetches. Other accesses use critical double-word forwarding. • Level 2 (L2) cache interface – On-chip, 512-Kbyte, eight-way set-associative unified instruction and data cache – Fully pipelined to provide 32 bytes per clock cycle to the L1 caches – A total nine-cycle load latency for an L1 data cache miss that hits in L2 – Cache write-back or write-through operation programmable on a per-page or perblock basis 64-byte, two-sectored line size – Parity support on cache • Separate memory management units (MMUs) for instructions and data – 52-bit virtual address, 32- or 36-bit physical address – Address translation for 4-Kbyte pages, variable-sized blocks, and 256-Mbyte segments – Memory programmable as write-back/write-through, caching-inhibited/cachingallowed, and memory coherency enforced/memory coherency not enforced on a page or block basis – Separate IBATs and DBATs (eight each) also defined as SPRs – Separate instruction and data translation look aside buffers (TLBs) Both TLBs are 128-entry, two-way set-associative, and use a LRU replacement algorithm TLBs are hardware- or software-reloadable (that is, a page table search is performed in hardware or by system software on a TLB miss). • Efficient data flow – Although the VR/LSU interface is 128 bits, the L1/L2 bus interface allows up to 256 bits – The L1 data cache is fully pipelined to provide 128 bits/cycle to or from the VRs – L2 cache is fully pipelined to provide 256 bits per processor clock cycle to the L1 cache – As many as eight outstanding, out-of-order, cache misses are allowed between the L1 data cache and the L2 bus – As many as 16 out-of-order transactions can be present on the MPX bus 6 PC7447A [Preliminary] 5387B–HIREL–07/05 PC7447A [Preliminary] – Store merging for multiple store misses to the same line. Only coherency action taken (address-only) for store misses merged to all 32 bytes of a cache block (no data tenure needed) – Three-entry finished store queue and five-entry completed store queue between the LSU and the L1 data cache – Separate additional queues for efficient buffering of outbound data (such as castouts and write-through stores) from the L1 data cache and L2 cache • Multiprocessing support features include the following: – Hardware-enforced, MESI cache coherency protocols for data cache – Load/store with reservation instruction pair for atomic memory references, semaphores, and other multiprocessor operations • Power and thermal management – A new dynamic frequency switching (DFS) feature allows the processor core frequency to be halved through software to reduce power consumption – The following three power-saving modes are available to the system: Nap: Instruction fetching is halted. Only the clocks for the time base, decrementer, and JTAG logic remain running. The part goes into the doze state to snoop memory operations on the bus and then back to nap using a QREQ/QACK processor-system handshake protocol. Sleep: Power consumption is further reduced by disabling bus snooping, leaving only the PLL in a locked and running state. All internal functional units are disabled. Deep sleep: When the part is in the deep Sleep state, the system can disable the PLL. The system can then disable the SYSCLK source for greater system power savings. Power-on reset procedures for restarting and relocking the PLL must be followed upon exiting the deep sleep state. – Instruction cache throttling provides control of instruction fetching to limit device temperature – A new temperature diode that can determine the temperature of the microprocessor • Performance monitor can be used to help debug system designs and improve software efficiency • In-system testability and debugging features through JTAG boundary-scan capability • Testability – LSSD scan design – IEEE 1149.1 JTAG interface – Array built-in self test (ABIST), factory test only • Reliability and serviceability – Parity checking on system bus – Parity checking on the L1 and L2 caches 7 5387B–HIREL–07/05 4. Signal Description Figure 4-1. PC7447A Microprocessor Signal Groups BR Address Arbitration BG 1 1 A[0:35] Address Transfer AP[0:4] 36 5 INT SMI MCP SRESET HRESET CKSTP_IN CKSTP_OUT TBEN QREQ QACK BVSEL BMODE[0:1] PMON_IN PMON_OUT SYSCLK PLL_CFG[0:3](2) PLL_EXT EXT_QUAL CLK_OUT TCK TDI TDO TMS TRST AVDD GND Test Interface (JTAG) Clock Control Processor Status/Control Interrupts/Resets TS TT[0:4] TBST Address Transfer Attributes TSIZ[0:2] GBL WT CI 1 5 1 3 1 1 1 PC7447A 1 1 1 1 1 1 1 1 AACK Address Transfer Termination ARTRY SHD0/SHD1 HIT 1 1 2 1 1 1 1 2 1 DBG Data Arbitration DTI[0:3] DRDY 1 4 1 1 1 4 1 D[0:63] Data Transfer DP[0:7] 64 8 1 1 1 Data Transfer Termination TA TEA 1 1 1 1 1 1 VDD OVDD Note: For the PC7447A, there are 5 PLL_CFG signals, (PLL_CFG[0:4] 8 PC7447A [Preliminary] 5387B–HIREL–07/05 PC7447A [Preliminary] 5. Detailed Specification This specification describes the specific requirements for the microprocessor PC7447A in compliance with Atmel standard screening. 6. Applicable Documents 1. MIL-STD-883: Test methods and procedures for electronics 2. MIL-PRF-38535: Appendix A: General specifications for microcircuits The microcircuits are in accordance with the applicable documents and as specified herein. 6.1 6.1.1 Design and Construction Terminal Connections Depending on the package, the terminal connections are as shown in Table 8-1, Table 6-2 and Figure 4-1. 6.2 Absolute Maximum Ratings The tables in this section describe the PC7447A DC electrical characteristics. Table 6-1 provides the absolute maximum ratings. Table 6-1. Symbol VDD (2) Absolute Maximum Ratings(1) Characteristic Core supply voltage PLL supply voltage BVSEL = 0 Processor bus supply voltage BVSEL = HRESET or OVDD Processor bus Input voltage JTAG signals Storage temperature range -0.3 to 2.7 -0.3 to OVDD + 0.3 -0.3 to OVDD + 0.3 -55 to 150 V V V °C Maximum Value -0.3 to 1.60 -0.3 to 1.60 -0.3 to 1.95 Unit V V V AVDD(2) OVDD(3)(4) OVDD(3)(5) VIN VIN TSTG Notes: (6)(7) 1. Functional and tested operating conditions are given in Table 6-2 on page 10. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. Caution: VDD/AVDD must not exceed OVDD by more than 1V during normal operation; this limit may be exceeded for a maximum of 20 ms during the power-on reset and power-down sequences. 3. Caution: OVDD must not exceed VDD/AVDD by more than 2V during normal operation; this limit may be exceeded for a maximum of 20 ms during the power-on reset and power-down sequences. 4. BVSEL must be set to 0, such that the bus is in 1.8V mode. 5. BVSEL must be set to HRESET or 1, such that the bus is in 2.5V mode. 6. Caution: VIN must not exceed OVDD by more than 0.3V at any time including during power-on reset. 7. VIN may overshoot/undershoot to a voltage and for a maximum duration shown in Figure 6-1 on page 10. 9 5387B–HIREL–07/05 6.3 Recommended Operating Conditions Table 6-2 provides the recommended operating conditions for the PC7447A. Recommended Operating Conditions(1) Recommended Value Characteristic Core supply voltage (2) Table 6-2. Symbol VDD AVDD Min Max Unit V V 1.3V ±50 mV or 1.1V ±50 mV 1.3V ±50 mV or 1.1V ±50 mV BVSEL = 0 1.8V ±5% PLL supply voltage Processor bus supply voltage OVDD OVDD VIN VIN Tj Notes: BVSEL = HRESET or OVDD Processor bus GND GND -55 V 2.5V ±5% OVDD OVDD 125°C Input voltage JTAG signals Die-junction temperature V °C 1. These are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed. 2. This voltage is the input to the filter discussed in Section ”PLL Power Supply Filtering” on page 37 and not necessarily the voltage at the AVDD pin, which may be reduced from VDD by the filter. Figure 6-1. Overshoot/Undershoot Voltage OVDD + 20% OVDD + 5% OVDD VIH VIL GND GND – 0.3V GND – 0.7V Not to exceed 10% of tSYSCLK The PC7447A provides several I/O voltages to support both compatibility with existing systems and migration to future systems. The PC7447A core voltage must always be provided at a nominal 1.3V (see Table 6-2 on page 10 for the actual recommended core voltage). The input voltage threshold for each bus is selected by sampling the state of the voltage select pins at the negation of the signal HRESET. The output voltage will swing from GND to the maximum voltage applied to the OVDD power pins. Table 6-3 on page 11 provides the input threshold voltage settings. Because these settings may change in future products, it is recommended that BVSEL be configured using resistor options, jumpers, or some other flexible means, with the capability to reconfigure the termination of this signal in the future if necessary. 10 PC7447A [Preliminary] 5387B–HIREL–07/05 PC7447A [Preliminary] Table 6-3. Input Threshold Voltage Setting(1) Processor Bus Input Threshold is Relative to: 1.8V Not available 2.5V Notes (2) BVSEL Signal 0 ¬HRESET HRESET 1 Notes: 2.5V 1. Caution: The input threshold selection must agree with the OVDD voltages supplied. See notes in Table 6-1 on page 9. 2. If used, pull-down resistors should be less than 250Ω. 6.4 6.4.1 Thermal Characteristics Package Characteristics Package Thermal Characteristics(1) Characteristic Junction-to-ambient thermal resistance, natural convection, single-layer (1s) board Junction-to-ambient thermal resistance, natural convection, four-layer (2s2p) board Junction-to-ambient thermal resistance, 200 ft./min. airflow, single-layer (1s) board Junction-to-ambient thermal resistance, 200 ft./min. airflow, four-layer (2s2p) board Junction-to-board thermal resistance Junction-to-case thermal resistance Value 26 19 20 16 10 < 0.1 Unit Table 6-4. Symbol RθJA(2)(3) RθJMA(2)(4) RθJMA(2)(4) RθJMA(2)(4) RθJB(5) RθJC(6) Notes: °C/W °C/W °C/W °C/W °C/W °C/W 1. See ”Thermal Management Information” on page 12 for details about thermal management. 2. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, airflow, power dissipation of other components on the board, and board thermal resistance. 3. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal. 4. Per JEDEC JESD51-6 with the board horizontal. 5. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 6. This is the thermal resistance between the die and the case top surface as measured with the cold plate method (MIL SPEC-883 Method 1012.1) with the calculated case temperature. The actual value of RθJC for the part is less than 0.1°C/W. 6.4.2 Internal Package Conduction Resistance For the exposed-die packaging technology described in Table 6-4 on page 11, the intrinsic conduction thermal resistance paths are as follows: • The die junction-to-case thermal resistance (the case is actually the top of the exposed silicon die) • The die junction-to-ball thermal resistance Figure 19 depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board. 11 5387B–HIREL–07/05 Figure 6-2. C4 Package with Heat Sink Mounted to a Printed-Circuit Board Radiation Convection External Resistance Heat Sink Thermal Interface Material Internal Resistance Printed-Circuit Board Die/Package Die Junction Package/Leads External Resistance Radiation Convection Note the internal versus external package resistance. Heat generated on the active side of the chip is conducted through the silicon, through the heat sink attach material (or thermal interface material), and finally to the heat sink where it is removed by forced-air convection. Because the silicon thermal resistance is quite small, the temperature drop in the silicon may be neglected for a first-order analysis. Thus, the thermal interface material and the heat sink conduction/convective thermal resistances are the dominant terms. 6.4.3 Thermal Management Information This section provides thermal management information for the high coefficient of the thermal expansion ceramic ball grid array (HITCE) package for air-cooled applications. Proper thermal control design is primarily dependent on the system-level design – the heat sink, airflow, and thermal interface material. The PC7447A implements several features designed to assist with thermal management, including DFS and the temperature diode. DFS reduces the power consumption of the device by reducing the core frequency; see Table 6-6 on page 19 for specific information regarding power reduction and DFS. The temperature diode allows an external device to monitor the die temperature in order to detect excessive temperature conditions and alert the system; see section ”Temperature Diode” on page 16 for more information. To reduce the die-junction temperature, heat sinks may be attached to the package by several methods – spring clips to holes in the printed-circuit board or package, and mounting clips and screw assembly (see Figure 6-3); however, due to the potentially large mass of the heat sink, attachment through the printed-circuit board is suggested. If a spring clip is used, the spring force should not exceed ten pounds. 12 PC7447A [Preliminary] 5387B–HIREL–07/05 PC7447A [Preliminary] Figure 6-3. Package Exploded Cross-sectional View with Several Heat Sink Options Heat Sink HCTE Package Heat Sink Clip Thermal Interface Material Printed-Circuit Board 6.4.4 Thermal Interface Materials A thermal interface material is recommended at the package lid-to-heat sink interface to minimize the thermal contact resistance. For those applications where the heat sink is attached by spring clip mechanism, Figure 6-4 on page 14 shows the thermal performance of three thinsheet thermal-interface materials (silicone, graphite/oil, floroether oil), a bare joint, and a joint with thermal grease as a function of contact pressure. As shown, the performance of these thermal interface materials improves with increasing contact pressure. The use of thermal grease significantly reduces the interface thermal resistance. That is, the bare joint results in a thermal resistance approximately seven times greater than the thermal grease joint. Often, heat sinks are attached to the package by means of a spring clip to holes in the printedcircuit board (see Figure 6-3 on page 13). Therefore, synthetic grease offers the best thermal performance, considering the low interface pressure, and is recommended due to the high power dissipation of the PC7447A. Of course, the selection of any thermal interface material depends on many factors – thermal performance requirements, manufacturability, service temperature, dielectric properties, cost, and so on. 13 5387B–HIREL–07/05 Figure 6-4. 2 Thermal Performance of Select Thermal Interface Material Silicone Sheet (0.006 in.) Bare Joint Floroether Oil Sheet (0.007 in.) Graphite/Oil Sheet (0.005 in.) Synthetic Grease Specific Thermal Resistance (K-in.2/W) 1.5 1 0.5 0 0 10 20 30 40 50 Contact Pressure (psi) 60 70 80 6.4.4.1 Heat Sink Selection Example For preliminary heat sink sizing, the die-junction temperature can be expressed as follows: Tj = TI + Tr + (RθJC + Rθint + Rθsa) × Pd where: Tj is the die-junction temperature Ti is the inlet cabinet ambient temperature Tr is the air temperature rise within the computer cabinet RθJC is the junction-to-case thermal resistance Rθint is the adhesive or interface material thermal resistance Rθsa is the heat sink base-to-ambient thermal resistance Pd is the power dissipated by the device 14 PC7447A [Preliminary] 5387B–HIREL–07/05 PC7447A [Preliminary] During operation, the die-junction temperatures (Tj) should be maintained less than the value specified in Table 6-2 on page 10. The temperature of air cooling the component greatly depends on the ambient inlet air temperature and the air temperature rise within the electronic cabinet. An electronic cabinet inlet-air temperature (Ti) may range from 30° to 40°C. The air temperature rise within a cabinet (Tr) may be in the range of 5° to 10°C. The thermal resistance of the thermal interface material (Rθint) is typically about 1.5°C/W. For example, assuming a Ti of 30°C, a Tr of 5°C, an HITCE package Rθ JC = 0.1, and a typical power consumption (Pd ) of 18.7W, the following expression for Tj is obtained: Die-junction temperature: Tj = 30°C + 5°C + (0.1°C/W + 1.5°C/W + θsa) × 18.7W For this example, a Rθsa value of 2.1°C/W or less is required to maintain the die junction temperature below the maximum value of Table 6-2 on page 10. Though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a common figure-of-merit used for comparing the thermal performance of various microelectronic packaging technologies, one should exercise caution when only using this metric in determining thermal management because no single parameter can adequately describe three-dimensional heat flow. The final die-junction operating temperature is not only a function of the componentlevel thermal resistance, but the system-level design and its operating conditions. In addition to the component's power consumption, a number of factors affect the final operating die-junction temperature – airflow, board population (local heat flux of adjacent components), heat sink efficiency, heat sink attach, heat sink placement, next-level interconnect technology, system air temperature rise, altitude, and so on. Due to the complexity and variety of system-level boundary conditions for today's microelectronic equipment, the combined effects of the heat transfer mechanisms (radiation, convection, and conduction) may vary widely. For these reasons, we recommend using conjugate heat transfer models for the board, as well as system-level designs. For system thermal modeling, the PC7447A thermal model is shown in Figure 6-5 on page 16. Four volumes represent this device. Two of the volumes, solder ball-air and substrate, are modeled using the package outline size of the package. The other two, die, and bump-underfill, have the same size as the die. The silicon die should be modeled 9.5 × 9.5 × 0.7 mm with the heat source applied as a uniform source at the bottom of the volume. The bump and underfill layer is modeled as 7.3 × 9.3 × 0.7 mm (or as a collapsed volume) with orthotropic material properties: 0.6 W/(m × K) in the xy-plane and 1.9 W/(m × K) in the direction of the z-axis. The substrate volume is 25 × 25 × 1.2 mm, and has 8.1 W/(m × K) isotropic conductivity in the xy-plane and 4 W/(m × K) in the direction of the z-axis. The solder ball and air layer are modeled with the same horizontal dimensions as the substrate and are 0.6 mm thick. They can also be modeled as a collapsed volume using orthotropic material properties: 0.034 W/(m × K) in the xy-plane direction and 3.8 W/(m × K) in the direction of the z-axis. 15 5387B–HIREL–07/05 Figure 6-5. Recommended Thermal Model of PC7447A Conductivity Value Unit Die W/(m x K) z Bump and Underfill Substrate Solder and Air Side View of Model (Not to Scale) x 8.1 8.1 4.0 Substrate Solder Ball and Air (25 x 25 x 0.6 mm) Bump and Underfill (7.3 x 9.3 x 0.070 mm) kx ky kz 0.6 0.6 1.9 Substrate (25 x 25 x 1.2 mm) kx ky kz kx ky kz 0.034 0.034 3.8 y Die Side View of Model (Not to Scale) 6.4.4.2 Temperature Diode The PC7447A has a temperature diode on the microprocessor that can be used in conjunction with other system temperature monitoring devices. These devices use the negative temperature coefficient of a diode operated at a constant current to determine the temperature of the microprocessor and its environment. For proper operation, the monitoring device used should autocalibrate the device by canceling out the VBE variation of each PC7447A’s internal diode. The following are the specifications of the PC7447A on-board temperature diode: Vf > 0.40V Vf < 0.90V Operating range 2 - 300 µA Diode leakage < 10 nA at 125°C Ideality factor over 5 µA – 150 µA at 60°C: 1