T6816

Features • Six High-side and Six Low-side Drivers • Outputs Freely Configurable as Switch, Half Bridge or H-bridge • Capable to Switch all Kinds of Loads such as DC Motors, Bulbs, Resistors, Capacitors • • • • • • • • • • • • and Inductors 0.6A Continuous Current per Switch Low-side: RDSon < 1.5Ω versus Total Temperature Range High-side: RDSon < 2.0Ω versus Total Temperature Range Very Low Quiescent Current Is < 20 µA in Standby Mode Outputs Short-circuit Protected Overtemperature Prewarning and Protection Undervoltage Protection Various Diagnosis Functions such as Shorted Output, Open Load, Overtemperature and Power Supply Fail Serial Data Interface Operation Voltage up to 40V Daisy Chaining Possible SO28 Power Package 40-V Dual Hex Output Driver with Serial Input Control T6816 1. Description The T6816 is a fully protected driver interface designed in 0.8 µm BCDMOS technology. It is especially suitable for truck or bus applications and the industrial 24-V supply. It controls up to 12 different loads via a 16-bit dataword. Each of the six high-side and six low-side drivers is capable to drive currents up to 600 mA. The drivers are freely configurable and can be controlled separately from a standard serial data interface. Therefore, all kinds of loads such as bulbs, resistors, capacitors and inductors can be combined. The IC is also designed to easily build H-bridges to drive DC motors in motion-control applications. Protection is guaranteed in terms of short-circuit conditions, overtemperature and undervoltage. Various diagnosis functions and a very low quiescent current in standby mode open a wide range of applications. Automotive qualification referring to conducted interferences, EMC protection and 2 kV ESD protection gives added value and enhanced quality for the exacting requirements of automotive applications. 4595F–BCD–02/08 Figure 1-1. Block Diagram HS1 15 15 HS2 13 13 HS3 12 12 HS4 3 3 HS5 2 2 HS6 28 28 Fault Detect Fault Detect Fault Detect Fault Detect Fault Detect Fault Detect 5 VS 10 26 6 VS DI GND Osc CLK 25 S I S C T O L D H S 6 L S 6 H S 5 L S 5 H S 4 L S 4 H S 3 L S 3 H S 2 L S 2 H S 1 L S 1 S R R 7 GND VS CS 24 Input Register Output Register P S F I N H S C D H S 6 L S 6 H S 5 L S 5 H S 4 L S 4 H S 3 L S 3 H S 2 L S 2 H S 1 L S 1 T P Control logic 8 UV protection Thermal protection Power-on reset GND 9 GND INH 17 20 GND 18 DO 21 GND VCC Fault Detect Fault Detect Fault Detect Fault Detect Fault Detect Fault Detect 22 GND 23 GND VCC 19 VCC 16 LS1 LS2 14 11 LS3 LS4 4 LS5 1 27 LS6 2 T6816 4595F–BCD–02/08 T6816 2. Pin Configuration Figure 2-1. Pinning SO28 HS6 28 LS6 27 DI 26 CLK 25 CS 24 GND GND GND GND VCC DO 23 22 21 20 19 18 INH 17 LS1 HS1 16 15 T6816 Lead frame 1 LS5 2 HS5 3 HS4 4 LS4 5 VS 6 7 8 9 10 VS 11 LS3 12 HS3 13 HS2 14 LS2 GND GND GND GND Table 2-1. Pin 1 2 3 4 5 6, 7, 8, 9 10 11 12 13 14 15 16 17 18 19 20-23 24 25 26 27 28 Pin Description Symbol LS5 HS5 HS4 LS4 VS GND VS LS3 HS3 HS2 LS2 HS1 LS1 INH DO VCC GND CS CLK DI LS6 HS6 Function Low-side driver output 5; Power-MOS open drain with internal reverse diode; short-circuit protection; diagnosis for short and open load High-side driver output 5; Power-MOS open drain with internal reverse diode; short-circuit protection; diagnosis for short and open load High-side driver output 4; see pin 2 Low-side driver output 4; see pin 1 Power supply output stages HS4, HS5, HS6, internal supply; external connection to pin 10 necessary Ground; reference potential; internal connection to pin 20-23; cooling tab Power supply output stages HS1, HS2 and HS3 Low-side driver output 3; see pin 1 High-side driver output 3; see pin 2 High-side driver output 2; see pin 2 Low-side driver output 2; see pin 1 High-side driver output 1; see pin 2 Low-side driver output 1; see pin 1 Inhibit input; 5V logic input with internal pull down; low = standby, high = normal operating Serial data output; 5V CMOS logic level tri-state output for output (status) register data; sends 16-bit status information to the microcontroller (LSB is transferred first). Output will remain tri-stated unless device is selected by CS = low, therefore, several ICs can operate on one data output line only. Logic supply voltage (5V) Ground; see pin 6-9 Chip select input; 5V CMOS logic level input with internal pull up; low = serial communication is enabled, high = disabled Serial clock input; 5V CMOS logic level input with internal pull down; controls serial data input interface and internal shift register (fmax = 2 MHz) Serial data input; 5V CMOS logic level input with internal pull down; receives serial data from the control device; DI expects a 16-bit control word with LSB being transferred first Low-side driver output 6; see pin 1 High-side driver output 6; see pin 2 3 4595F–BCD–02/08 3. Functional Description 3.1 Serial Interface Data transfer starts with the falling edge of the CS signal. Data must appear at DI synchronized to CLK and are accepted on the falling edge of the CLK signal. LSB (bit 0, SRR) has to be transferred first. Execution of new input data is enabled on the rising edge of the CS signal. When CS is high, pin DO is in tri-state condition. This output is enabled on the falling edge of CS. Output data will change their state with the rising edge of CLK and stay stable until the next rising edge of CLK appears. LSB (bit 0, TP) is transferred first. Figure 3-1. CS Data Transfer Input Data Protocol DI SRR 0 LS1 1 HS1 2 LS2 3 HS2 4 LS3 5 HS3 6 LS4 7 HS4 8 LS5 9 HS5 10 LS6 11 HS6 12 OLD 13 SCT 14 SI 15 CLK DO TP SLS1 SHS1 SLS2 SHS2 SLS3 SHS3 SLS4 SHS4 SLS5 SHS5 SLS6 SHS6 SCD INH PSF Table 3-1. Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Input Data Protocol Input Register SRR LS1 HS1 LS2 HS2 LS3 HS3 LS4 HS4 LS5 HS5 LS6 HS6 OLD SCT Function Status register reset (high = reset; the bits PSF, SCD and overtemperature shutdown in the output data register are set to low) Controls output LS1 (high = switch output LS1 on) Controls output HS1 (high = switch output HS1 on) See LS1 See HS1 See LS1 See HS1 See LS1 See HS1 See LS1 See HS1 See LS1 See HS1 Open load detection (low = on) Programmable time delay for short circuit (shutdown delay high/low = 12 ms/1.5 ms) Software inhibit; low = standby, high = normal operation (data transfer is not affected by standby function because the digital part is still powered) 15 SI 4 T6816 4595F–BCD–02/08 T6816 Table 3-2. Bit 0 Output Data Protocol Output (Status) Register Function TP Temperature prewarning: high = warning (overtemperature shutdown see remark below) Normal operation: high = output is on, low = output is off Open-load detection: high = open load, low = no open load (correct load condition is detected if the corresponding output is switched off) Normal operation: high = output is on, low = output is off Open-load detection: high = open load, low = no open load (correct load condition is detected if the corresponding output is switched off) Description see LS1 Description see HS1 Description see LS1 Description see HS1 Description see LS1 Description see HS1 Description see LS1 Description see HS1 Description see LS1 Description see HS1 Short circuit detected: set high, when at least one output is switched off by a short circuit condition Inhibit: this bit is controlled by software (bit SI in input register) and hardware inhibit (pin 17). High = standby, low = normal operation Power supply fail: undervoltage at pin VS detected 1 Status LS1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Note: Status HS1 Status LS2 Status HS2 Status LS3 Status HS3 Status LS4 Status HS4 Status LS5 Status HS5 Status LS6 Status HS6 SCD INH PSF Bit 0 to 15 = high: overtemperature shutdown Table 3-3. Bit 15 (SI) H Bit 14 (SCT) H Status of the Input Register after Power on Reset Bit 13 (OLD) H Bit 12 (HS6) L Bit 11 (LS6) L Bit 10 (HS5) L Bit 9 (LS5) L Bit 8 (HS4) L Bit 7 (LS4) L Bit 6 (HS3) L Bit 5 (LS3) L Bit 4 (HS2) L Bit 3 (LS2) L Bit 2 (HS1) L Bit 1 (LS1) L Bit 0 (SRR) L 5 4595F–BCD–02/08 3.2 Power Supply Fail In case of undervoltage at pin VS, an internal timer is started. When the undervoltage delay time (tdUV) programmed by the SCT bit is reached, the power supply fail bit (PSF) in the output register is set and all outputs are disabled. When normal voltage is present again, the outputs are enabled immediately. The PSF bit remains high until it is reset by the SRR bit in the input register. 3.3 Open-load Detection If the open-load detection bit (OLD) is set to low, a pull-up current for each high-side switch and a pull-down current for each low-side switch is turned on (open-load detection current IHS1-6, ILS1-6). If VVS – VHS1-6 or VLS1-6 is lower than the open-load detection threshold (open-load condition), the corresponding bit of the output in the output register is set to high. Switching on an output stage with OLD bit set to low disables the open-load function for this output. 3.4 Overtemperature Protection If the junction temperature exceeds the thermal prewarning threshold, TjPW set, the temperature prewarning bit (TP) in the output register is set. When the temperature falls below the thermal prewarning threshold, TjPW reset, the bit TP is reset. The TP bit can be read without transferring a complete 16-bit data word: with CS = high to low, the state of TP appears at pin DO. After the microcontroller has read this information, CS is set high and the data transfer is interrupted without affecting the state of the input and output registers. If the junction temperature exceeds the thermal shutdown threshold, Tj switch off, the outputs are disabled and all bits in the output register are set high. The outputs can be enabled again when the temperature falls below the thermal shutdown threshold, Tj switch on, and when a high has been written to the SRR bit in the input register. Thermal prewarning and shutdown threshold have hysteresis. 3.5 Short-circuit Protection The output currents are limited by a current regulator. Current limitation takes place when the overcurrent limitation and shutdown threshold (IHS1-6, ILS1-6) are reached. Simultaneously, an internal timer is started. The shorted output is disabled when during a permanent short the delay time (tdSd) programmed by the short-circuit timer bit (SCT) is reached. Additionally, the short-circuit detection bit (SCD) is set. If the temperature prewarning bit TP in the output register is set during a short, the shorted output is disabled immediately and SCD bit is set. By writing a high to the SRR bit in the input register, the SCD bit is reset and the disabled outputs are enabled. 3.6 Inhibit There are two ways to inhibit the T6816: 1. Set bit SI in the input register to zero 2. Switch pin 17 (INH) to 0V In both cases, all output stages are turned off but the serial interface stays active. The output stages can be activated again by bit SI = 1 or by pin 17 (INH) switched back to 5V. 6 T6816 4595F–BCD–02/08 T6816 4. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All values refer to GND pins Parameter Supply voltage Supply voltage t < 0.5 s; IS ≥ –2 A Supply voltage difference ⏐ VS_pin5 – VS_pin10⏐ Supply current Supply current t < 200 ms Logic supply voltage Input voltage Logic input voltage Logic output voltage Input current Output current Output current Reverse conducting current (tPulse = 150 µs) Junction temperature range Storage temperature range 5, 10 5, 10 19 17 24 to 26 18 17, 24 to 26 18 1 to 4, 11 to 16, 27 and 28 2, 3, 12, 13, 15, 28 towards 5, 10 Pin 5, 10 5, 10 Symbol VVS VVS ∆VVS IVS IVS VVCC VINH VDI, VCLK, VCS VDO IINH, IDI, ICLK, ICS IDO ILS1 to ILS6 IHS1 to IHS6 IHS1 to IHS6 Tj TSTG Value –0.3 to +40 –1 150 1.4 2.6 –0.3 to +7 –0.3 to +17 –0.3 to VVCC +0.3 –0.3 to VVCC +0.3 –10 to +10 –10 to +10 Internal limited, see output specification 17 –40 to +150 –55 to +150 A °C °C Unit V V mV A A V V V V mA mA 5. Thermal Resistance All values refer to GND pins Parameter Junction pin Junction ambient Test Conditions Measured to GND Pin 6 to 9, 20 to 23 Symbol RthJP RthJA Min. Typ. Max. 25 65 Unit K/W K/W 6. Operating Range All values refer to GND pins Parameter Supply voltage Logic supply voltage Logic input voltage Serial interface clock frequency Junction temperature range Note: 1. Threshold for undervoltage detection. Test Conditions Pin 5, 10 19 17, 24 to 26 25 Symbol VVS VVCC VINH, VDI, VCLK, VCS fCLK Tj –40 Min. VUV(1) 4.5 –0.3 5 Typ. Max. 40 5.5 VVCC 2 150 Unit V V V MHz °C 7 4595F–BCD–02/08 7. Noise and Surge Immunity Parameter Conducted interferences Interference Suppression ESD (Human Body Model) ESD (Machine Model) Note: 1. Test pulse 5: VSmax = 40V Test Conditions ISO 7637-1 VDE 0879 Part 2 MIL-STD-883D Method 3015.7 EOS/ESD - S 5.2 Value Level 4(1) Level 5 2 kV 150V 8. Electrical Characteristics 7.5V < VVS < 40V; 4.5V < VVCC < 5.5V; INH = High; –40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins. No. 1 1.1 1.2 Parameters Current Consumption Quiescent current (VS) Quiescent current (VCC) Supply current (VS) VVS < 28V, INH or bit SI = low 4.5V < VVCC < 5.5V, INH or bit SI = low VVS < 28V normal operating, all output stages off VVS < 28V normal operating, all output stages on, no load 4.5V < VVCC < 5.5V, normal operating pin 5, 10 19 IVS IVCC IVS 0.8 40 20 µA µA A A Test Conditions Pin Symbol Min. Typ. Max. Unit Type* 1.3 5, 10 1.2 mA A 1.4 Supply current (VS) 5, 10 IVS IVCC 10 mA A 1.5 2 2.1 3 3.1 3.2 3.3 3.4 3.5 4 4.1 4.2 4.3 4.4 Notes: Supply current (VCC) 19 150 µA A Internal Oscillator Frequency Frequency (timebase for delay timers) Undervoltage Detection, Power-on Reset Power-on reset threshold Power-on reset delay time Undervoltage detection threshold Undervoltage detection hysteresis Undervoltage detection delay Thermal Prewarning and Shutdown Thermal prewarning Thermal prewarning Thermal prewarning hysteresis Thermal shutdown 17 17 17 TjPWset TjPWreset ∆TjPW Tj switch off 150 125 105 145 125 20 170 190 165 145 °C °C K °C A A A A After switching on VVCC 19 19 5, 10 5, 10 5, 10 VVCC tdPor VUV ∆VUV tdUV 7 3.4 30 5.5 0.4 21 3.9 95 4.4 160 7.0 V µs V V ms A A A A A fOSC 19 45 kHz A *) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 1. Delay time between rising edge of CS after data transmission and switch on output stages to 90% of final level 8 T6816 4595F–BCD–02/08 T6816 8. Electrical Characteristics (Continued) 7.5V < VVS < 40V; 4.5V < VVCC < 5.5V; INH = High; –40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins. No. 4.5 4.6 Parameters Thermal shutdown Thermal shutdown hysteresis Ratio thermal shutdown/thermal prewarning Ratio thermal shutdown/thermal prewarning Output Specification (LS1-LS6, HS1-HS6) On resistance IOut = 600 mA 1, 4, 11, 14, 16, 27 2, 3, 12, 13, 15, 28 1, 4, 11, 14, 16, 27 1, 4, 11, 14, 16, 27 2, 3, 12, 13, 15, 28 1-4, 11-16, 27, 28 1-4, 11-16, 27, 28 1-4, 11-16, 27 2, 3, 12,13, 15, 28 Input register bit 14 (SCT) = low Input register bit 13 (OLD) = low, output off Input register bit 13 (OLD) = low, output off 1, 4, 11,14, 16, 27 2, 3, 12, 13 15, 28 RDS OnL 1.5 Ω A Test Conditions Pin 17 Symbol Tj switch on ∆Tj switch off Tj switch off/ TjPW set Tj switch on/ TjPW reset 1.05 Min. 130 Typ. 150 20 Max. 170 Unit °C K Type* A A 4.7 1.17 A 4.8 5 5.1 1.05 1.2 A 5.2 On resistance IOut = –600 mA RDS OnH 2.0 Ω A 5.3 Output clamping voltage ILS1-6 = 50 mA VLS1–6 = 40V all output stages off VHS1-6 = 0V all output stages off VLS1-6 40 60 V A 5.4 Output leakage current ILS1-6 10 µA A 5.5 Output leakage current IHS1-6 –10 µA A 5.7 Inductive shutdown energy Output voltage edge steepness Overcurrent limitation and shutdown threshold Overcurrent limitation and shutdown threshold Overcurrent shutdown delay time Open load detection current Open load detection current Woutx dVLS1-6/dt dVHS1-6/dt ILS1-6 15 mJ D 5.8 50 200 400 mV/µs A 5.9 650 950 1250 mA A 5.10 IHS1-6 tdSd ILS1-6 –1250 –950 –650 mA A 5.11 1.0 1.5 2.0 ms A 5.12 60 200 µA A 5.13 IHS1-6 –150 –30 µA A *) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. Delay time between rising edge of CS after data transmission and switch on output stages to 90% of final level 9 4595F–BCD–02/08 8. Electrical Characteristics (Continued) 7.5V < VVS < 40V; 4.5V < VVCC < 5.5V; INH = High; –40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins. No. 5.14 Parameters Open load detection current ratio Open load detection threshold Open load detection threshold Output switch on delay(1) Output switch off delay(1) Inhibit Input Input voltage low level threshold Input voltage high level threshold Hysteresis of input voltage Pull-down current Input voltage low-level threshold Input voltage high-level threshold Hysteresis of input voltage Pull-down current pin DI, CLK Pull-up current pin CS VDI, VCLK = VVCC VCS= 0V VINH = VVCC Serial Interface - Logic Inputs DI, CLK, CS 24-26 24-26 24-26 25, 26 24 18 18 18 VIL VIH ∆VI IPDSI IPUSI VDOL VDOH IDO VVCC –0.7V –10 10 50 2 –50 0.3 × VVCC 0.7 × VVCC 500 50 –2 0.5 V V mV µA µA V V µA A A A A A A A A 17 17 17 17 VIL VIH ∆VI IPD 100 10 0.3 × VVCC 0.7 × VVCC 700 80 V V mV µA A A A A Input register bit 13 (OLD) = low, output off Input register bit 13 (OLD) = low, output off RLoad = 1 kΩ RLoad = 1 kΩ 1, 4, 11,14, 16, 27 2, 3, 12, 13 15, 28 Test Conditions Pin Symbol ILS1-6/IHS1-6 VLS1-6 VVS – VHS1-6 tdon tdoff Min. 1.2 Typ. Max. Unit Type* A 5.15 0.6 2 V A 5.16 0.6 2 V A 5.17 5.18 6 6.1 6.2 6.3 6.4 7 7.1 7.2 7.3 7.4 7.5 8 8.1 8.2 8.3 0.5 1 ms ms A A Serial Interface - Logic Output DO Output voltage low level IOL = 3 mA Output voltage high level Leakage current (tri-state) IOL = –2 mA VCS = VVCC, 0V < VDO < VVCC *) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. Delay time between rising edge of CS after data transmission and switch on output stages to 90% of final level 10 T6816 4595F–BCD–02/08 T6816 9. Serial Interface - Timing Parameters DO enable after CS falling edge DO disable after CS rising edge DO fall time DO rise time DO valid time CS setup time CS setup time CS high time CS high time CLK high time CLK low time CLK period time CLK setup time CLK setup time DI setup time DI hold time Input register bit 14 (SCT) = high Input register bit 14 (SCT) = low Test Conditions CDO = 100 pF CDO = 100 pF CDO = 100 pF CDO = 100 pF CDO = 100 pF Timing Chart No. 1 2 – – 10 4 8 9 9 5 6 – 7 3 11 12 Symbol tENDO tDISDO tDOf tDOr tDOVal tCSSethl tCSSetlh tCSh tCSh tCLKh tCLKl tCLKp tCLKSethl tCLKSetlh tDIset tDIHold 225 225 16 2 225 225 500 225 225 40 40 Min. Typ. Max. 200 200 100 100 200 Unit ns ns ns ns ns ns ns ms ms ns ns ns ns ns ns ns 11 4595F–BCD–02/08 Figure 9-1. Serial Interface Timing with Chart Numbers 1 2 CS DO 9 CS 4 7 CLK 5 3 6 8 DI 11 CLK 10 12 DO Inputs DI, CLK, CS: High level = 0.7 × VCC, low level = 0.2 × VCC Output DO: High level = 0.8 × VCC, low level = 0.2 × VCC 12 T6816 4595F–BCD–02/08 T6816 10. Application Figure 10-1. Application Circuit VCC U5021M WATCHDOG Trigger Reset Enable HS1 15 HS2 13 HS3 12 HS4 HS5 HS6 3 2 28 VS BYT41D Fault Detect Fault Detect Fault Detect Fault Detect Fault Detect Fault Detect 5V S VS GND VBatt 24V Microcontroller DI 26 6 Osc S C T O L D H S 6 L S 6 H S 5 L S 5 H S 4 L S 4 H S 3 L S 3 H S 2 L S 2 H S 1 L S 1 S R R CLK 25 S I 7 VS Control logic UV protection Thermal protection Power-on Reset GND 8 9 20 21 22 23 GND CS 24 Input Register Output Register P S F I N H S C D H S 6 L S 6 H S 5 L S 5 H S 4 L S 4 H S 3 L S 3 H S 2 L S 2 H S 1 L S 1 T P GND INH 17 GND 18 DO GND VCC Fault Detect Fault Detect Fault Detect Fault Detect Fault Detect Fault Detect GND GND VCC VCC 16 LS1 14 LS2 11 LS3 LS4 19 V CC 4 LS5 1 27 LS6 VS VS 10.1 Application Notes It is strongly recommended to connect the blocking capacitors at VCC and VS as close as possible to the power supply and GND pins. Recommended value for capacitors at VS: electrolythic capacitor C > 22 µF in parallel with a ceramic capacitor C = 100 nF. Value for electrolytic capacitor depends on external loads, conducted interferences and reverse conducting current IHSX (see: Absolute Maximum Ratings). Recommended value for capacitors at VCC: electrolythic capacitor C > 10 µF in parallel with a ceramic capacitor C = 100 nF. To reduce thermal resistance it is recommended to place cooling areas on the PCB as close as possible to GND pins. 4595F–BCD–02/08 + VCC + 10 VCC 5V 13 11. Ordering Information Extended Type Number T6816-TIQY Package SO28 Remarks Power package, taped and reeled, Pb-free 12. Package Information Package SO28 Dimensions in mm 18.05 17.80 9.15 8.65 7.5 7.3 2.35 0.4 1.27 28 16.51 15 0.25 0.10 0.25 10.50 10.20 technical drawings according to DIN specifications 1 14 14 T6816 4595F–BCD–02/08 T6816 13. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. 4595F-BCD-02/08 History • Put datasheet in the newest template • Pb-free logo on page 1 deleted • Section 8 “Electrical Characteristics” number 5 on page 9 changed • Pb-free logo on page 1 added • Section 1 “Description” on page 1 changed • Ordering Information on page 14 changed • Put datasheet in a new template • Table “Electrical Characteristics” rows 5.15 and 5.16 changed • Put datasheet in a new template • Table “Absolute Maximum Ratings” on page 7 changed • Table “Electrical Characteristics” on page 10 changed 4595E-BCD-09/05 4595D-BCD-05/05 4595C-BCD-04/04 15 4595F–BCD–02/08 Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 International Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-en-Yvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Product Contact Web Site www.atmel.com Technical Support auto_control@atmel.com Sales Contact www.atmel.com/contacts Literature Requests www.atmel.com/literature Disclaimer: T he information in this document is provided in connection with Atmel products. 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