T6817

Features • Three High-side and Three Low-side Drivers • Outputs Freely Configurable as Switch, Half Bridge or H-bridge • Capable of Switching All Kinds of Loads Such as DC Motors, Bulbs, Resistors, Capacitors and Inductors 0.6A Continuous Current Per Switch Low-side: RDSon < 1.5Ω Versus Total Temperature Range High-side: RDSon < 2.0Ω Versus Total Temperature Range Very Low Quiescent Current IS < 20 µA in Standby Mode Outputs Short-circuit Protected Overtemperature Prewarning and Protection Undervoltage and Overvoltage Protection Various Diagnosis Functions Such as Shorted Output, Open Load, Overtemperature and Power Supply Fail • Serial Data Interface • Daisy Chaining Possible • SSO20 Package • • • • • • • • Dual Triple DMOS Output Driver with Serial Input Control T6817 1. Description The T6817 is a fully protected driver interface designed in 0.8-µm BCDMOS technology. It can be used to control up to 6 different loads by a microcontroller in automotive and industrial applications. Each of the 3 high-side and 3 low-side drivers is capable of driving currents up to 600 mA. The drivers are freely configurable and can be controlled separately from a standard serial data interface. Therefore, all kinds of loads such as bulbs, resistors, capacitors and inductors can be combined. The IC design is especially supportive of H-bridges applications to drive DC motors. Protection is guaranteed in terms of short-circuit conditions, overtemperature, underand overvoltage. Various diagnosis functions and a very low quiescent current in standby mode open a wide range of applications. Meeting automotive qualifications in the area of conducted interferences, EMC protection and 2 kV ESD protection provide added value and enhanced quality for the exacting requirements of automotive applications. 4670D–BCD–04/07 Figure 1-1. Block Diagram HS3 12 HS2 14 HS1 16 Osc Fault detect Fault detect Fault detect VS 6 VS DI 2 S C T O L D H S 3 L S 3 H S 2 L S 2 H S 1 L S 1 S R R VS S I n. u. n. u. n. u. n. u. n. u. n. u. 7 CLK OV protection 4 VS Input register CS Vcc VCC 19 3 Output register Serial interface Control logic H S 1 LT SP 1 UV protection - INH 5 P S F I N H S C D n. u. n. u. n. n. u. u. n. u. n. u. H S 3 L S 3 H S 2 L S 2 Power-on reset GND 1 GND 10 GND 11 DO 18 Vcc Fault detect Fault detect Fault detect Thermal protection 17 GND 13 GND 8 LS3 LS2 15 LS1 20 2 T6817 4670D–BCD–04/07 T6817 2. Pin Configuration Figure 2-1. Pinning SSO20 GND DI CS CLK INH VS VS LS3 n.c. GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 GND VCC DO LS1 HS1 LS2 HS2 GND HS3 GND Table 2-1. Pin 1 2 3 4 5 6, 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pin Description Symbol GND DI CS CLK INH VS LS3 n.c. GND GND HS3 GND HS2 LS2 HS1 LS1 DO VCC GND Function Ground; reference potential; internal connection to pin 10, 11, 13 and 20; cooling tab Serial data input; 5-V CMOS logic level input with internal pull-down; receives serial data from the control device, DI expects a 16-bit control word with LSB being transferred first Chip-select input; 5-V CMOS logic level input with internal pull-up; low = serial communication is enabled, high = disabled Serial clock input; 5-V CMOS logic level input with internal pull down; controls serial data input interface and internal shift register (fmax = 2 MHz) Inhibit input; 5-V logic input with internal pull-down; low = standby, high = normal operating Power supply output stages HS1, HS2 and HS3 Low-side driver output 3; power-MOS open drain with internal reverse diode: overvoltage protection by active zenering; short-circuit protection; diagnosis for short and open load Not connected Ground (see pin 1) be consistent Ground (see pin 1) High-side driver output 3; power-MOS open drain with internal reverse diode: overvoltage protection by active zenering; short-circuit protection; diagnosis for short and open load Ground (see pin 1) High-side driver output 2 (see pin 12) be consistent Low-side driver output 2 (see pin 8) High-side driver output 1 (see pin 12) Low-side driver output 1 (see pin 8) Serial data output; 5-V CMOS logic level tri-state output for output (status) register data; sends 16-bit status information to the microcontroller (LSB is transferred first); output will remain tri-stated unless device is selected by CS = low, therefore, several ICs can operate on only one data output line only. Logic supply voltage (5V) Ground (see pin 1) 3 4670D–BCD–04/07 3. Functional Description 3.1 Serial Interface Data transfer starts with the falling edge of the CS signal. Data must appear at DI synchronized to CLK and are accepted on the falling edge of the CLK signal. LSB (bit 0, SRR) has to be transferred first. Execution of new input data is enabled on the rising edge of the CS signal. When CS is high, pin DO is in tri-state condition. This output is enabled on the falling edge of CS. Output data will change their state with the rising edge of CLK and stay stable until the next rising edge of CLK appears. LSB (bit 0, TP) is transferred first. Figure 3-1. CS Data Transfer Input Data Protocol DI SRR 0 LS1 1 HS1 2 LS2 3 HS2 4 LS3 5 HS3 6 n.u. 7 n.u. 8 n.u. 9 n.u. 10 n.u. 11 n.u. 12 OLD 13 SCT 14 SI 15 CLK DO TP SLS1 SHS1 SLS2 SHS2 SLS3 SHS3 n.u. n.u. n.u. n.u. n.u. n.u. SCD INH PSF Table 3-1. Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Input Data Protocol Function Status register reset (high = reset; the bits PSF, SCD and overtemperature shutdown in the output data register are set to low) Controls output LS1 (high = switch output LS1 on) Controls output HS1 (high = switch output HS1 on) See LS1 See HS1 See LS1 See HS1 Not used Not used Not used Not used Not used Not used Open load detection (low = on) Programmable time delay for short circuit and overvoltage shutdown (short circuit shutdown delay high/low = 100 ms/12.5 ms, overvoltage shutdown delay high/low = 14 ms/3.5 ms Software inhibit; low = standby, high = normal operation (data transfer is not affected by standby function because the digital part is still powered) Input Register SRR LS1 HS1 LS2 HS2 LS3 HS3 n.u. n.u. n.u. n.u. n.u. n.u. OLD SCT 15 SI 4 T6817 4670D–BCD–04/07 T6817 Table 3-2. Bit 0 Output Data Protocol Output (Status) Register TP Function Temperature prewarning: high = warning (overtemperature shut-down, see remark below) Normal operation: high = output is on, low = output is off Open-load detection: high = open load, low = no open load (correct load condition is detected if the corresponding output is switched off) Normal operation: high = output is on, low = output is off Open-load detection: high = open load, low = no open load (correct load condition is detected if the corresponding output is switched off) Description, see LS1 Description, see HS1 Description, see LS1 Description, see HS1 Not used Not used Not used Not used Not used Not used Short circuit detected: set high, when at least one output is switched off by a short circuit condition Inhibit: this bit is controlled by software (bit SI in input register) and hardware inhibit (pin 17). High = standby, low = normal operation Power supply fail: over- or undervoltage at pin VS detected 1 Status LS1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Note: Status HS1 Status LS2 Status HS2 Status LS3 Status HS3 n.u. n.u. n.u. n.u. n.u. n.u. SCD INH PSF Bit 0 to 15 = high: overtemperature shutdown Table 3-3. Bit 15 Bit 14 (SI) (SCT) H H Status of the Input Register after Power on Reset Bit 13 (OLD) H Bit 12 n.u. Bit 11 n.u. Bit 10 n.u. Bit 9 n.u. Bit 8 n.u. Bit 7 n.u. Bit 6 (HS3) L Bit 5 (LS3) L Bit 4 (HS2) L Bit 3 (LS2) L Bit 2 Bit 1 (HS1) (LS1) L L Bit 0 (SRR) L 5 4670D–BCD–04/07 3.2 Power-supply Fail In case of over- or undervoltage at pin VS, an internal timer is started. When the undervoltage delay time (tdUV, tdOV) programmed by the SCT bit is reached, the power supply fail bit (PSF) in the output register is set and all outputs are disabled. When normal voltage is present again, the outputs are enabled immediately. The PSF bit remains high until it is reset by the SRR bit in the input register. 3.3 Open-load Detection If the open-load detection bit (OLD) is set to low, a pull-up current for each high-side switch and a pull-down current for each low-side switch is turned on (open-load detection current IHS1-3, ILS1-3). If VVS-VHS1-3 or VLS1-3 is lower than the open-load detection threshold (open-load condition), the corresponding bit of the output in the output register is set to high. Switching on an output stage with the OLD bit set to low disables the open-load function for this output. If bit SI is set to low, the open-load function is also switched off. 3.4 Overtemperature Protection If the junction temperature exceeds the thermal prewarning threshold, TjPW set, the temperature prewarning bit (TP) in the output register is set. When the temperature falls below the thermal prewarning threshold, TjPW reset, the bit TP is reset. The TP bit can be read without transferring a complete 16-bit data word: with CS = high to low, the state of TP appears at pin DO. After the microcontroller has read this information, CS is set high and the data transfer is interrupted without affecting the state of the input and output registers. If the junction temperature exceeds the thermal shutdown threshold, Tj switch off, the outputs are disabled and all bits in the output register are set high. The outputs can be enabled again when the temperature falls below the thermal shutdown threshold, Tj switch on, and when a high has been written to the SRR bit in the input register. Thermal prewarning and shutdown threshold have hysteresis. 3.5 Short-circuit Protection The output currents are limited by a current regulator. Current limitation takes place when the overcurrent limitation and shutdown threshold (IHS1-3, ILS1-3) are reached. Simultaneously, an internal timer is started. The shorted output is disabled when during a permanent short the delay time (tdSd) programmed by the short-circuit timer bit (SCT) is reached. Additionally, the short-circuit detection bit (SCD) is set. If the temperature prewarning bit TP in the output register is set during a short, the shorted output is disabled immediately and SCD bit is set. By writing a high to the SRR bit in the input register, the SCD bit is reset and the disabled outputs are enabled. 3.6 Inhibit There are two ways to inhibit the T6817: 1. Set bit SI in the input register to zero 2. Switch pin 5 (INH) to 0V In both cases, all output stages are turned off but the serial interface stays active. The output stages can be activated again by bit SI = 1 and by pin 5 (INH) switched back to 5V. 6 T6817 4670D–BCD–04/07 T6817 4. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All values refer to GND pins. Parameter Supply voltage Supply voltage t < 0.5s; IS > –2A Supply voltage difference |VS_Pin6 – VS_Pin7| Supply current Supply current t < 200 ms Logic supply voltage Input voltage Logic input voltage Logic output voltage Input current Output current Output current Reverse conducting current (tPulse = 150 µs) Junction temperature range Storage temperature range 6, 7 6, 7 19 5 2 to 4 18 5, 2 to 4 18 8, 12, 14 to 17 12, 14, 16 towards 6, 7 Pin 6, 7 6, 7 Symbol VVS VVS ∆VVS IVS IVS VVCC VINH VDI, VCLK, VCS VDO IINH, IDI, ICLK, ICS IDO ILS1 to ILS3 IHS1 to IHS3 IHS1 to IHS3 Tj TSTG Value –0.3 to +40 –1 150 1.4 2.6 –0.3 to 7 –0.3 to 17 –0.3 to VVCC +0.3 –0.3 to VVCC +0.3 –10 to +10 –10 to +10 Internal limited, see output specification 17 –40 to +150 –55 to +150 A °C °C Unit V V mV A A V V V V mA mA 5. Thermal Resistance All values refer to GND pins Parameter Junction pin Junction ambient Test Conditions Measured to GND Pins 1, 10, 11, 13 and 20 Symbol RthJP RthJA Value 25 65 Unit K/W K/W 6. Operating Range All values refer to GND pins Parameter Supply voltage Logic supply voltage Logic input voltage Serial interface clock frequency Junction temperature range Notes: 1. Threshold for undervoltage detection 2. Outputs disabled for VVS > VOV (threshold for overvoltage detection) Test Conditions Pins 6, 7 Pin 19 Pin 2 to 4 and 5 Pin 4 Symbol VVS VVCC VINH, VDI, VCLK, VCS fCLK Tj –40 Min. VUV (1) Typ. 5 Max. 40 (2) Unit V V V MHz °C 4.5 –0.3 5.5 VVCC 2 150 7 4670D–BCD–04/07 7. Noise and Surge Immunity Parameter Conducted interferences Interference Suppression ESD (Human Body Model) ESD (Machine Model) Note: 1. Test pulse 5: VSmax = 40V Test Conditions ISO 7637–1 VDE 0879 Part 2 MIL-STM 5.1 – 1998 JEDEC EIA / JESD 22 – A115-A Value Level 4(1) Level 5 2 kV 150V 8. Electrical Characteristics 7.5V < VVS < VOV; 4.5V < VVCC < 5.5V; INH = High; –40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins. No. 1 1.1 1.2 Parameters Current Consumption Quiescent current (VS) Quiescent current (VCC) Supply current (VS) VVS < 16V, INH or bit SI = low 4.5V < VVCC < 5.5V, INH or bit SI = low VVS < 16V normal operating, all output stages off, VVS < 16V normal operating, all output stages on, no load 4.5V < VVCC < 5.5V, normal operating pin 6, 7 19 IVS IVCC IVS 0.8 40 20 µA µA A A Test Conditions Pin Symbol Min. Typ. Max. Unit Type* 1.3 6, 7 1.2 mA A 1.4 Supply current (VS) 6, 7 IVS IVCC 10 mA A 1.5 2 2.1 3 3.1 3.2 3.3 3.4 3.6 3.7 3.8 Supply current (VCC) 19 150 µA A Internal Oscillator Frequency Frequency (time base for delay timers) Over- and Undervoltage Detection, Power-on Reset Power-on reset threshold Power-on reset delay time Undervoltage detection threshold Undervoltage detection hysteresis Undervoltage detection delay Overvoltage detection threshold Overvoltage detection hysteresis Undervoltage detection delay Input register bit 14 (SCT) = high bit 14 (SCT) = low After switching on VVCC 19 19 6, 7 6, 7 6, 7 6, 7 6, 7 VVCC tdPor VUV ∆VUV tdUV VOV ∆VOV tdOV tdOV 7 1.75 7 18.0 1 3.4 30 5.5 0.4 21 22.5 3.9 95 4.4 160 7.0 V µs V V ms V V A A A A A A A fOSC 19 45 kHz A 3.9 21 5.25 ms ms A *) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Delay time between rising edge of CS after data transmission and switch on/off output stages to 90% of final level 8 T6817 4670D–BCD–04/07 T6817 8. Electrical Characteristics (Continued) 7.5V < VVS < VOV; 4.5V < VVCC < 5.5V; INH = High; –40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins. No. 4 4.1 4.2 4.3 4.4 4.5 4.6 Parameters Thermal prewarning Thermal prewarning Thermal prewarning hysteresis Thermal shutdown Thermal shutdown Thermal shutdown hysteresis Ratio thermal shutdown/thermal prewarning Ratio thermal shutdown/thermal prewarning 8, 15, 17 12, 14, 16 8, 15, 17 8, 15, 17 2, 3, 12, 13, 15, 28 8, 12, 14 to 17 8, 12, 14 to 17 8, 15, 17 12, 14, 16 Input register bit 14 (SCT) = high bit 14 (SCT) = low Input register bit 13 (OLD) = low, output off 8, 15, 17 Test Conditions Pin Symbol TjPWset TjPWreset ∆TjPW Tj switch off Tj switch on ∆Tj switch off Tj switch off/ TjPW set Tj switch on/ TjPW reset Min. 125 105 3 150 130 3 Typ. 145 125 20 170 150 20 190 170 Max. 165 145 Unit °C °C K °C °C K Type* A A A A A A Thermal Prewarning and Shutdown 4.7 1.05 1.17 A 4.8 5 5.1 5.2 5.3 5.4 1.05 1.2 A Output Specification (LS1-LS6, HS1-HS6) 7.5V < VVS < VOV On resistance On resistance Output clamping voltage Output leakage current Output leakage current Inductive shutdown energy Output voltage edge steepness Overcurrent limitation and shutdown threshold Overcurrent limitation and shutdown threshold Overcurrent shutdown delay time Open load detection current IOut = 600 mA IOut = –600 mA ILS1-3 = 50 mA VLS1–3 = 40V all output stages off VHS1-3 = 0V all output stages off RDS OnL RDS OnH VLS1-3 ILS1–3 IHS1–3 –10 40 1.5 2.0 60 10 Ω Ω V µA A A A A 5.5 µA A 5.7 Woutx dVLS1–3/dt dVHS1–3/dt ILS1–3 15 mJ D 5.8 50 200 400 mV/µs A 5.9 650 950 1250 mA A 5.10 IHS1–3 –1250 –950 –650 mA A 5.11 tdSd tdSd ILS1–3 70 8.75 60 100 140 17.5 200 ms ms µA A A A 5.12 *) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Delay time between rising edge of CS after data transmission and switch on/off output stages to 90% of final level 9 4670D–BCD–04/07 8. Electrical Characteristics (Continued) 7.5V < VVS < VOV; 4.5V < VVCC < 5.5V; INH = High; –40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins. No. 5.13 5.14 5.15 5.16 5.17 5.18 6 6.1 6.2 6.3 6.4 7 7.1 7.2 7.3 7.4 7.5 8 8.1 8.2 8.3 Parameters Open load detection current Open load detection current ratio Open load detection threshold Open load detection threshold Output switch on delay(1) Output switch off delay(1) Inhibit Input Input voltage low level threshold Input voltage high level threshold Hysteresis of input voltage Pull-down current Input voltage low-level threshold Input voltage high-level threshold Hysteresis of input voltage Pull-down current pin DI, CLK Pull-up current pin CS Output voltage low level Output voltage high level Leakage current (tri-state) VDI, VCLK = VVCC VCS = 0V VINH = VVCC Serial Interface – Logic Inputs DI, CLK, CS 2-4 2-4 2-4 2, 4 3 VIL VIH ∆VI IPDSI IPUSI 50 2 –50 0.3 × VVCC 0.7 × VVCC 500 50 –2 V V mV µA µA A A A A A 5 5 5 5 VIL VIH ∆VI IPD 100 10 0.3 × VVCC 0.7 × VVCC 700 80 V V mV µA A A A A Input register bit 13 (OLD) = low, output off Input register bit 13 (OLD) = low, output off RLoad = 1 kΩ RLoad = 1 kΩ 8, 15, 17 12, 14, 16 Test Conditions Input register bit 13 (OLD) = low, output off Pin 12, 14, 16 Symbol IHS1–3 ILS1–3/ IHS1–3 VLS1–3 VVS– VHS1–3 tdon tdoff Min. –150 1.2 0.6 0.6 2 2 0.5 1 V V ms ms Typ. Max. –30 Unit µA Type* A A A A A A Serial Interface - Logic Output DO IOL = 3 mA IOL = –2 mA VCS = VVCC, 0 V < VDO < VVCC 18 18 18 VDOL VDOH IDO VVCC –1V –10 10 0.5 V V µA A A A *) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Delay time between rising edge of CS after data transmission and switch on/off output stages to 90% of final level 10 T6817 4670D–BCD–04/07 T6817 9. Serial Interface - Timing Parameters DO enable after CS falling edge DO disable after CS rising edge DO fall time DO rise time DO valid time CS setup time CS setup time CS high time CS high time CLK high time CLK low time CLK period time CLK setup time CLK setup time DI setup time DI hold time Input register bit 14 (SCT) = high Input register bit 14 (SCT) = low Test Conditions CDO = 100 pF CDO = 100 pF CDO = 100 pF CDO = 100 pF CDO = 100 pF Timing Chart No. 1 2 – – 10 4 8 9 9 5 6 – 7 3 11 12 Symbol tENDO tDISDO tDOf tDOr tDOVal tCSSethl tCSSetlh tCSh tCSh tCLKh tCLKl tCLKp tCLKSethl tCLKSetlh tDIset tDIHold 225 225 140 17.5 225 225 500 225 225 40 40 Min. Typ. Max. 200 200 100 100 200 Unit ns ns ns ns ns ns ns ms ms ns ns ns ns ns ns ns 11 4670D–BCD–04/07 Figure 9-1. Serial Interface Timing with Chart Numbers 1 2 CS DO 9 CS 4 7 CLK 5 3 6 8 DI 11 CLK 10 12 DO Inputs DI, CLK, CS: High level = 0.7 Output DO: High level = 0.8 VCC, low level = 0.3 VCC VCC VCC, low level = 0.2 12 T6817 4670D–BCD–04/07 T6817 10. Application Figure 10-1. Application Circuit Vcc U5021M Watchdog Trigger Enable Reset M HS3 HS2 M HS1 12 Fault detect Fault detect 14 Fault detect 16 Osc VS Vs BYT41D 6 VS 7 + + VS V Batt 13 V DI 2 S I S C T O L D n. u. n. u. n. n. n. u. u. u. H n. S u. 3 L S 3 H S 2 L S 2 H S 1 L S 1 S R R CLK OVprotection VS Vcc 19 VCC 4 Vcc 5V µC CS 3 5 P S F I Input register Output register S C D n. u. n. n. u. u. n. u. n. u. n. u. Serial interface H S 3 L S 3 H S 2 L S 2 H S 1 LT SP 1 Control logic UVprotection INH N H Power-on reset Vcc 1 10 11 GND DO GND 18 GND GND GND Fault detect Fault detect Fault detect Thermal protection 17 13 20 8 LS3 LS2 15 LS1 10.1 Application Notes It is strongly recommended that the blocking capacitors at VCC and VS be connected as close as possible to the power supply and GND pins. Recommended value for capacitors at VS: Electrolythic capacitor C > 22 µF in parallel with a ceramic capacitor C = 100 nF. Value for electrolytic capacitor depends on external loads, conducted interferences and reverse conducting current IHSX (see: Absolute Maximum Ratings). Recommended value for capacitors at VCC: Electrolythic capacitor C > 10 µF in parallel with a ceramic capacitor C = 100 nF. To reduce thermal resistance it is recommended that cooling areas be placed on the PCB as close as possible to GND pins. 13 4670D–BCD–04/07 11. Ordering Information Extended Type Number T6817-TKSY T6817-TKQY Package SSO20 SSO20 Remarks Power package, tube, Pb-free Power package, taped and reeled, Pb-free 12. Package Information 5.4±0.2 6.75-0.25 4.4±0.1 0.05+0.1 1.3±0.05 0.25±0.05 0.65±0.05 5.85±0.05 6.45±0.15 20 11 Package: SSO20 Dimensions in mm technical drawings according to DIN specifications 1 10 Drawing-No.: 6.543-5056.01-4 Issue: 1; 10.03.04 14 T6817 4670D–BCD–04/07 0.15±0.05 T6817 13. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. 4670D-BCD-04/07 History • Put datasheet in a new template • Pb-free logo on page 1 deleted • Table 8 “Electrical Characteristics” number 5.11 on page 9 changed • Pb-free logo on page 1 added • Table “Ordering Information” on page 14 changed • Put datasheet in a new template • Table “Electrical Characteristics” rows 5.15 and 5.16 changed 4670C-BCD-09/05 4670B-BCD-05/05 15 4670D–BCD–04/07 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. 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A tmel ®, logo and combinations thereof, Everywhere You Are® a nd others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. 4670D–BCD–04/07