T6819_05

Features • • • • • • • • • • • • • • Supply Voltage up to 40V RDSon Typically 0.5Ω at 25°C, Maximum 1.1Ω at 150°C Up to 1.5A Output Current Three High-side and Three Low-side Drivers Usable as Single Outputs or Half Bridges Capable to Switch all Kinds of Loads such as DC Motors, Bulbs, Resistors, Capacitors and Inductors PWM Capability for Each Output Controlled by External PWM Signal No Shoot-through Current Very Low Quiescent Current IS < 5 µA in Standby Mode over Total Temperature Range Outputs Short-circuit Protected Selective Overtemperature Protection for Each Switch and Overtemperature Prewarning Undervoltage Protection Various Diagnostic Functions such as Shorted Output, Open Load, Overtemperature and Power-supply Fail Detection Serial Data Interface, Daisy Chain Capable, up to 2 MHz Clock Frequency SO16 Power Package Dual Triple DMOS Output Driver with Serial Input Control T6819/ATA6829 1. Description The T6819/ATA6829 are fully protected driver interfaces designed in 0.8-µm BCDMOS technology. They are used to control up to six different loads by a microcontroller in automotive and industrial applications. Each of the three high-side and three low-side drivers is capable to drive currents up to 1.5A. Each driver is freely configurable and can be controlled separately from a standard serial data interface. Therefore, all kinds of loads such as bulbs, resistors, capacitors and inductors can be combined. The IC design especially supports the applications of H-bridges to drive DC motors. The capability to control each output with an external PWM signal opens additional applications. Protection is guaranteed regarding short-circuit conditions, overtemperature and undervoltage. Various diagnostic functions and a very low quiescent current in stand-by mode opens a wide range of applications. Automotive qualification (protection against conducted interferences, EMC protection and 2-kV ESD protection) gives added value and enhanced quality for exacting requirements of automotive applications. Rev. 4531F–BCD–09/05 Figure 1-1. Block Diagram OUT3H 4 OUT2H 14 OUT1H 13 Charge pump Fault detect Fault detect Fault detect 6 12 DI VS 7 CLK S I O C S O L D P H 3 P L 3 P H 2 P L 2 P H 1 P L 1 H S 3 L S 3 H S 2 L S 2 H S 1 L S 1 S R R 5 Input register Output register P S F I N H O V L n. u. n. u. n. n. u. u. Serial interface n. n. u. u. H S 3 L S 3 H S 2 L S 2 H S 1 LT SP 1 Control logic UV protection Power-on reset 11 CS VCC 10 DO 16 PWM 8 Fault detect Fault detect Fault detect GND Thermal protection 9 GND GND 1 3 15 2 OUT3L OUT2L OUT1L 2 T6819/ATA6829 4531F–BCD–09/05 T6819/ATA6829 2. Pin Configuration Figure 2-1. Pinning SO16/PSO16 GND OUT1L OUT3L OUT3H CS DI CLK PWM 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 GND OUT2L OUT2H OUT1H VS VCC DO GND Table 2-1. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Description Symbol GND OUT1L OUT3L OUT3H CS DI CLK PWM GND DO VCC VS OUT1H OUT2H OUT2L GND Function T6819: ground; reference potential; internal connection to pin 9 and pin 16; cooling tab ATA6829: additional connection to heat slug Low-side driver output 1; power MOS open drain with internal reverse diode; short-circuit protection; overtemperature protection; diagnosis for short and open load; PWM ability Low-side driver output 3; see pin 2 High-side driver output 3; power MOS open source with internal reverse diode; short-circuit protection; overtemperature protection; diagnosis for short and open load; PWM ability Chip select input; 5-V CMOS logic level input with internal pull up; low = serial communication is enabled, high = disabled Serial data input; 5-V CMOS logic level input with internal pull down; receives serial data from the control device; DI expects a 16-bit control word with LSB being transferred first Serial clock input; 5-V CMOS logic level input with internal pull down; controls serial data input interface and internal shift register (fmax = 2 MHz) PWM input; 5-V CMOS logic level input with internal pull down; receives PWM signal to control outputs which are selected for PWM mode by the serial data interface, high = outputs on, low = outputs off Ground; see pin 1 Serial data output; 5-V CMOS logic-level tri-state output for output (status) register data; sends 16-bit status information to the microcontroller (LSB is transferred first); output will remain tri-stated unless device is selected by CS = low, therefore, several ICs can operate on one data-output line only. Logic supply voltage (5V) Power supply for high-side output stages OUT1H, OUT2H, OUT3H, internal supply High-side driver output 1; see pin 4 High-side driver output 2; see pin 4 Low-side driver output 2; see pin 2 Ground; see pin 1 3 4531F–BCD–09/05 3. Functional Description 3.1 Serial Interface Data transfer starts with the falling edge of the CS signal. Data must appear at DI synchronized to CLK and are accepted on the falling edge of the CLK signal. LSB (bit 0, SRR) has to be transferred first. Execution of new input data is enabled on the rising edge of the CS signal. When CS is high, pin DO is in tri-state condition. This output is enabled on the falling edge of CS. Output data will change their state with the rising edge of CLK and stay stable until the next rising edge of CLK appears. LSB (bit 0, TP) is transferred first. Figure 3-1. CS Data Transfer DI SRR 0 LS1 1 HS1 2 LS2 3 HS2 4 LS3 5 HS3 6 PL1 7 PH1 8 PL2 9 PH2 10 PL3 11 PH3 12 OLD 13 OCS 14 15 SI CLK DO TP S1L S1H S2L S2H S3L S3H n. u. n. u. n. u. n. u. n. u. n. u. OVL INH PSF Table 3-1. Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Input Data Protocol Function Status register reset (high = reset; the bits PSF and OVL in the output data register are set to low) Controls output LS1 (high = switch output LS1 on) Controls output HS1 (high = switch output HS1 on) See LS1 See HS1 See LS1 See HS1 Output LS1 additionally controlled by PWM Input Output HS1 additionally controlled by PWM Input See PL1 See PH1 See PL1 See PH1 Open load detection (low = on) Overcurrent shutdown (high = overcurrent shutdown is active) Software inhibit; low = standby, high = normal operation (data transfer is not affected by standby function because the digital part is still powered) Input Register SRR LS1 HS1 LS2 HS2 LS3 HS3 PL1 PH1 PL2 PH2 PL3 PH3 OLD OCS SI 4 T6819/ATA6829 4531F–BCD–09/05 T6819/ATA6829 Table 3-2. Bit 0 Output Data Protocol Output (Status) Register TP Function Temperature prewarning: high = warning Normal operation: high = output is on, low = output is off Open-load detection: high = open load, low = no open load (correct load condition is detected if the corresponding output is switched off); not affected by SRR Normal operation: high = output is on, low = output is off Open-load detection: high = open load, low = no open load (correct load condition is detected if the corresponding output is switched off); not affected by SRR Description see LS1 Description see HS1 Description see LS1 Description see HS1 Not used Not used Not used Not used Not used Not used Over-load detected: set high, when at least one output is switched off by a short-circuit condition or an overtemperature event. Bits 1 to 6 can be used to detect the affected switch. (open-load detection bit OLD = high) Inhibit: this bit is controlled by software (bit SI in input register) High = standby, low = normal operation Power-supply fail: undervoltage at pin VS detected 1 Status LS1 2 Status HS1 3 4 5 6 7 8 9 10 11 12 Status LS2 Status HS2 Status LS3 Status HS3 n. u. n. u. n. u. n. u. n. u. n. u. 13 OVL 14 15 INH PSF After power-on reset, the input register has the following status: Bit 15 SI H Bit 14 OCS H Bit 13 OLD H Bit 12 PH3 L Bit 11 PL3 L Bit 10 PH2 L Bit 9 PL2 L Bit 8 PH1 L Bit 7 PL1 L Bit 6 HS3 L Bit 5 LS3 L Bit 4 HS2 L Bit 3 LS2 L Bit 2 HS1 L Bit 1 LS1 L Bit 0 SRR L The following patterns are used to enable internal test modes of the IC. It is not recommended to use these patterns during normal operation. Bit 15 H H H Bit 14 H H H Bit 13 (OCS) H H H H L L H L L L H L L H L L L H L L H Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 (HS3) L L L Bit 5 (LS3) L L L Bit 4 (HS2) L L L Bit 3 (LS2) L L L Bit 2 (HS1) L L L Bit 1 (LS1) L L L Bit 0 (SRR) L L L 5 4531F–BCD–09/05 3.2 Power-supply Fail In case of undervoltage at pin VS, the Power-Supply Fail bit (PSF) in the output register is set and all outputs are disabled. To detect an undervoltage, its duration has to last longer than the undervoltage detection delay time tdUV. The outputs are enabled immediately when supply voltage recovers normal operation value. The PSF bit stays high until it is reset by the SRR bit in the input register. 3.3 Open-load Detection If the open-load detection bit (OLD) is set to low, a pull-up current for each high-side switch and a pull-down current for each low-side switch is turned on (open-load detection current IOUT1-3). If the current through the external load does not reach the open-load detection current, the corresponding bit of the output in the output register is set to high. Switching on an output stage with OLD bit set to low disables the open-load function for this output. 3.4 Overtemperature Protection If the junction temperature of one ore more output stages exceeds the thermal prewarning threshold, TjPW set, the temperature prewarning bit (TP) in the output register is set. When the temperature falls below the thermal prewarning threshold, TjPW reset, the bit TP is reset. The TP bit can be read without transferring a complete 16-bit data word. The status of TP is available at pin DO with the falling edge of CS. After the microcontroller has read this information, CS is set high and the data transfer is interrupted without affecting the status of input and output registers. If the junction temperature of an output stage exceeds the thermal shutdown threshold, Tj switch off, the affected output is disabled and the corresponding bit in the output register is set to low. Additional the overload detection bit (OVL) in the output register is set. The output can be enabled again when the temperature falls below the thermal shutdown threshold, Tjswitch on and the SRR bit in the input register is set to high. Hysteresis of thermal prewarning and shutdown threshold avoids oscillations. 3.5 Short-circuit Protection The output currents are limited by a current regulator. Overcurrent detection is activated by writing a high to the OCS bit in the input register. When the current in an output stage exceeds the overcurrent limitation and shut-down threshold, it is switched off after a delay time (tdSd). The over-load detection bit (OVL) is set and the corresponding status bit in the output register is set to low. For OCS = low the overcurrent shutdown is inactive and the OVL bit is not set by an overcurrent. By writing a high to the SRR bit in the input register the OVL bit is reset and the disabled outputs are enabled. 3.6 Inhibit The SI bit in the input register has to be set to zero to inhibit the T6819/ATA6829. All output stages are then turned off but the serial interface stays active. The current consumption is reduced to less than 5 µA at pin VS and less than 100 µA at pin VCC. The output stages can be activated again by bit SI = 1. 6 T6819/ATA6829 4531F–BCD–09/05 T6819/ATA6829 4. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All values refer to GND pins. Parameters Supply voltage Supply voltage t < 0.5s; IS > –2A Logic supply voltage Logic input voltage Logic output voltage Input current Output current Output current Output voltage Reverse conducting current (tpulse = 150 µs) Junction temperature range Storage temperature range Pin 12 12 11 5 to 8 10 5 to 8 10 2 to 4 13 to 15 2 to 4 13 to 15 2 to 4 13 to 15 towards pin 12 Symbol VVS VVS VVCC VCS, VDI, VCLK, VPWM VDO ICS, IDI, ICLK, IPWM IDO IOut3H, IOut2H, IOut1H IOut3L, IOut2L, IOut1L IOut3H, IOut2H, IOut1H IOut3L, IOut2L, IOut1L IOut3H, IOut2H, IOut1H IOut3L, IOut2L, IOut1L TJ TSTG Value –0.3 to +40 –1 –0.3 to +7 –0.3 to VVCC + 0.3 –0.3 to VVCC + 0.3 –10 to +10 –10 to +10 Internally limited, see output specification –0.3 to +40 V Unit V V V V V mA mA 17 –40 to +150 –55 to +150 A °C °C 5. Thermal Resistance Parameters T6819 Junction pin Junction ambient ATA6829 Junction pin Junction ambient Measured to heat slug GND pins 1, 9 and 16 RthJP RthJA 5 30 K/W K/W Measured to GND Pins 1, 9 and 16 RthJP RthJA 30 65 K/W K/W Test Conditions Symbol Value Unit 6. Operating Range Parameters Supply voltage Logic supply voltage Logic input voltage Serial interface clock frequency PWM input frequency Junction temperature range Note: 1. Threshold for undervoltage detection. Symbol VVS VVCC VCS,VDI, VCLK, VPWM fCLK fPWM Tj Value VUV(1) to 40 4.75 to 5.25 –0.3 to VVCC 2 1 –40 to +150 Unit V V V MHz kHz °C 7 4531F–BCD–09/05 7. Noise and Surge Immunity Parameters Conducted interferences Interference suppression ESD (Human Body Model) ESD (Machine Model) Note: 1. Test pulse 5: Vsmax = 40V. Test Conditions ISO 7637-1 VDE 0879 Part 2 ESD S 5.1 JEDEC A115A Value Level 4(1) Level 5 2 kV 200 V 8. Electrical Characteristics 7.5V < VS < 40V; 4.75V < VCC < 5.25V; INH = High; -40° C < Tj < 150° C; unless otherwise specified, all values refer to GND pins. No. 1 1.1 1.2 Parameters Current Consumption Quiescent current VS Quiescent current VCC VVS < 20V, SI = low 4.75V < VVCC < 5.25V, SI = low VVS < 20V normal operating, all outputs off, input register bit 13 (OLD) = high 4.75V < VVCC < 5.25V, normal operating VVS = 32.5V, INH = low VVS = 40V, INH = low 12 11 IVS IVCC 1 60 5 100 µA µA A A Test Conditions Pin Symbol Min. Typ. Max. Unit Type* 1.3 Supply current VS 12 IVS 4 6 mA A 1.4 1.5 1.6 2 2.1 2.2 2.3 2.4 2.5 3 3.1 3.2 3.3 3.4 Supply current VCC Discharge current VS Discharge current VS Power-on reset threshold Power-on reset delay time 11 12 12 IVCC IVS IVS 0.5 2.5 350 650 5.5 10 µA mA mA A A A Undervoltage Detection, Power-on Reset 11 After switching on VCC 12 12 VVCC tdPor VUv ∆VUv tdUV 10 3.2 30 5.6 0.6 40 3.9 95 4.4 190 7.0 V µs V V µs A A A A A Undervoltage-detection VCC = 5V threshold Undervoltage-detection VCC = 5V hysteresis Undervoltage-detection delay time Thermal Prewarning and Shutdown Thermal prewarning set Thermal prewarning reset Thermal prewarning hysteresis Thermal shutdown off TjPW set TjPW reset ∆TjPW Tj switch off 120 105 145 130 15 170 155 °C °C K B B B B 150 175 200 °C *) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Delay time between rising edge of input signal at pin CS after data transmission and switch on/off output stages to 90% of final level. Device not in standby for t > 1 ms. 2. Delay time between rising/falling edge of input signal at pin PWM and switch on/off output stages to 90% of final level. 3. Difference between switch-on and switch-off delay time of input signal at pin PWM to output stages in PWM mode. 8 T6819/ATA6829 4531F–BCD–09/05 T6819/ATA6829 8. Electrical Characteristics (Continued) 7.5V < VS < 40V; 4.75V < VCC < 5.25V; INH = High; -40° C < Tj < 150° C; unless otherwise specified, all values refer to GND pins. No. 3.5 3.6 Parameters Thermal shutdown on Thermal shutdown hysteresis Ratio thermal shutdown off/thermal prewarning set Ratio thermal shutdown on/thermal prewarning reset Output Specification (OUT1-OUT3) On resistance High-side output leakage current Low-side output leakage current High-side switch reverse diode forward voltage IOut 1-3 H = –1.3A IOut 1-3 L = 1.3A VOut 1-3 H = 0V, output stages off VOut 1-3 L = VVS, output stages off IOut = 1.5A 4, 13, 14 2, 3, 15 4, 13, 14 2, 3, 15 4, 13, 14 2, 3, 15 4, 13, 14 RDSOn1-3H RDSOn1-3L IOut1-3H IOut1-3L VOut1-3 – VVS VOut1-3L IOut1-3H –1.5 –5 5 1.1 1.1 Ω Ω µA µA A A A A Test Conditions Pin Symbol Tj switch on ∆Tj switch off Tj switch off/ TjPW set Tj switch on/ TjPW reset 1.05 Min. 135 Typ. 160 15 Max. 185 Unit °C K Type* B B 3.7 1.2 B 3.8 4 4.1 4.2 4.3 4.4 1.05 1.2 B 4.5 1.5 V A 4.6 Low-side switch reverse IOut 1-3 L = –1.5A diode forward voltage High-side overcurrent limitation and shutdown threshold Low-side overcurrent limitation and shutdown threshold Overcurrent shutdown delay time High-side open load detection current Low-side open load detection current Input register bit 13 (OLD) = low, output off Input register bit 13 (OLD) = low, output off V A 4.7 –2.5 –2 –1.5 A A 4.8 2, 3, 15 IOut1-3L tdSd 1.5 2 2.5 A A 4.9 4.10 4.11 4.12 4.13 4.14 10 –2.5 0.2 40 –0.2 2.5 20 20 20 µs mA mA µs µs µs A A A A A A 4, 13, 14 2, 3, 15 IOut1-3H IOut1-3L tdon tdon tdoff High-side output switch VVS = 13V on delay(1),(2) RLoad = 30Ω Low-side output switch VVS = 13V on delay(1),(2) RLoad = 30Ω High-side output switch VVS =13V off delay(1),(2) RLoad = 30Ω *) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Delay time between rising edge of input signal at pin CS after data transmission and switch on/off output stages to 90% of final level. Device not in standby for t > 1 ms. 2. Delay time between rising/falling edge of input signal at pin PWM and switch on/off output stages to 90% of final level. 3. Difference between switch-on and switch-off delay time of input signal at pin PWM to output stages in PWM mode. 9 4531F–BCD–09/05 8. Electrical Characteristics (Continued) 7.5V < VS < 40V; 4.75V < VCC < 5.25V; INH = High; -40° C < Tj < 150° C; unless otherwise specified, all values refer to GND pins. No. 4.15 Parameters Test Conditions Pin Symbol tdoff tdon – tdoff ∆tdPWM = tdon – tdoff ∆tdPWM = tdon – tdoff 3 1 Min. Typ. Max. 3 Unit µs Type* A Low-side output switch VVS =13V off delay(1),(2) RLoad = 30Ω Dead time between corresponding highand low-side switches ∆tdPWM low-side switch(3) ∆tdPWM high-side switch(3) Input voltage low-level threshold Input voltage high-level threshold Hysteresis of input voltage Pull-down current Pins DI, CLK, PWM Pull-up current Pin CS VDI, VCLK, VPWM = VCC VCS = 0V VVS =13V RLoad = 30Ω VVS = 13V RLoad = 30Ω VVS = 13V RLoad = 30Ω 4.16 µs A 4.17 4.18 5 5.1 5.2 5.3 5.4 5.5 6 6.1 6.2 6.3 7 7.1 20 7 µs µs A A Logic Inputs DI, CLK, CS, PWM 5-8 5-8 5-8 6, 7, 8 5 VIL VIH ∆VI IPD IPU 50 10 –65 0.3 × VVCC 0.7 × VVCC 700 65 –10 V V mV µA µA A A A A A Serial Interface – Logic Output DO Output-voltage low level IDOL = 2 mA Output-voltage high level Leakage current (tri-state) Inhibit Input – Timing Delay time from standby to normal operation tdINH 100 µs A IDOL = –2 mA VCS = VCC 0V < VDO < VVCC 10 10 10 VDOL VDOH IDO VVCC – 0.7 V –10 10 0.4 V V µA A A A *) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Delay time between rising edge of input signal at pin CS after data transmission and switch on/off output stages to 90% of final level. Device not in standby for t > 1 ms. 2. Delay time between rising/falling edge of input signal at pin PWM and switch on/off output stages to 90% of final level. 3. Difference between switch-on and switch-off delay time of input signal at pin PWM to output stages in PWM mode. 10 T6819/ATA6829 4531F–BCD–09/05 T6819/ATA6829 9. Serial Interface – Timing No. 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 Parameters Test Conditions Pin 10 10 10 10 10 5 5 5 7 7 7 7 7 6 6 Timing Chart No.(1) 1 2 10 4 8 9 5 6 7 3 11 12 Symbol tENDO tDISDO tDOf tDOr tDOVal tCSSethl tCSSetlh tCSh tCLKh tCLKl tCLKp tCLKSethl tCLKSetlh tDIset tDIHold 225 225 500 225 225 500 225 225 40 40 Min. Typ. Max. 200 200 100 100 200 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Type* D D D D D D D D D D D D D D D DO enable after CS CDO = 100 pF falling edge DO disable after CS CDO = 100 pF rising edge DO fall time DO rise time DO valid time CS setup time CS setup time CS high time CLK high time CDO = 100 pF CDO = 100 pF CDO = 100 pF 8.10 CLK low time 8.11 CLK period time 8.12 CLK setup time 8.13 CLK setup time 8.14 DI setup time 8.15 DI hold time Note: 1. See Figure 9-1 on page 12 *) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 11 4531F–BCD–09/05 Figure 9-1. Serial Interface Timing with Chart Number 1 2 CS DO 9 CS 4 7 CLK 5 3 6 8 DI 11 CLK 10 12 DO Inputs DI, CLK, CS: High level = 0.7 × VCC, low level = 0.3 × VCC Output DO: High level = 0.8 × VCC, low level = 0.2 × VCC 12 T6819/ATA6829 4531F–BCD–09/05 T6819/ATA6829 10. Application Circuit VCC U5021M Watchdog Trigger OUT3H 4 M OUT2H 14 M OUT1H 13 Charge pump Reset Fault detect Fault detect Fault detect VS 12 6 DI VBatt VS 0 to 40 V O C S O L D P H 3 P L 3 P H 2 P L 2 P H 1 P L 1 H S 3 L S 3 H S 2 L S 2 H S 1 L S 1 S R R Control Input register 5 Output register Serial interface logic Power-on reset n. n. u. u. n. u. n. u. H S 3 L S 3 H S 2 L S 2 H S 1 LT SP 1 UV protection 11 VCC Microcontroller 7 CLK S I CS P S F 10 DO I N H O V L n. u. n. u. 16 PWM 8 Fault detect Fault detect Fault detect GND Thermal protection 9 GND 1 3 OUT3L OUT2L 15 OUT1L 2 GND VCC 10.1 Application Notes It is strongly recommended to connect the blocking capacitors at VCC and VS as close as possible to the power supply and GND pins. Recommended value for capacitors at VS: Electrolytic capacitor C > 22 µF in parallel with a ceramic capacitor C = 100 nF. Value for electrolytic capacitor depends on external loads, conducted interferences and reverse conducting current IOut1,2,3 (see “Absolute Maximum Ratings” on page 7). Recommended value for capacitors at VCC: Electrolytic capacitor C > 10 µF in parallel with a ceramic capacitor C = 100 nF. To reduce thermal resistance it is recommended to place cooling areas on the PCB as close as possible to the GND pins. Negative spikes at the output pins (e.g. negative spikes caused by an inductive load switched off with a high side driver) may activate the overtemperature protection function of the T6819/ATA6829. In this condition, the affected output will be switched off. If this behavior is not acceptable or compatible with the specific application functionally, it is necessary, that for switching on required outputs again, the SRR bit (Status Register Reset) is set, to ensure a reset of the overtemperature function. 4531F–BCD–09/05 + VCC 5V + 13 11. Ordering Information Extended Type Number T6819-TBSY T6819-TBQY ATA6829-T3SY ATA6829-T3QY Package SO16 SO16 PSO16 PSO16 Remarks Power package, tubed, lead-free Power package, taped and reeled, lead-free Power package with heat slug, tubed, lead-free Power package with heat slug, taped and reeled, lead-free 12. Package Information Package SO16 Dimensions in mm 10.0 9.85 5.2 4.8 3.7 1.4 0.4 1.27 8.89 16 9 0.25 0.10 0.2 3.8 6.15 5.85 technical drawings according to DIN specifications 1 8 14 T6819/ATA6829 4531F–BCD–09/05 T6819/ATA6829 1 Package: PSO16 with heat slug Dimensions in mm 2.54-0.5 8 heat slug exposed ∅ 0.4 A B 16 6.86 9 technical drawings according to DIN specifications 1.62 max. 9.9±0.1 A 0.23 0.1 max. 0.41 1.27 nom. 1.52 max. 3.99 max. 4.27±0.4 6±0.2 B 7 x 1.27 = 8.89 nom. Drawing-No.: 6.541-5050.01-4 Issue: 2; 18.08.05 13. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. 4531F-BCD-09/05 History • Complete datasheet: T6829 changed in ATA6829 • Ordering Information on page 14 changed • Package drawing on page 15 changed 15 4531F–BCD–09/05 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. 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