T7024-PGQM

Features • • • • • • • • Single 3-V Supply Voltage High Power-added Efficient Power Amplifier (Pout Typically 23 dBm) Ramp-controlled Output Power Low-noise Preamplifier (NF Typically 2.1 dB) Biasing for External PIN Diode T/R Switch Current-saving Standby Mode Few External Components QFN20 Package with Extended Performance 1. Description The T7024 is a monolithic SiGe transmit/receive front-end IC with power amplifier, low-noise amplifier and T/R switch driver. It is especially designed for operation in TDMA systems like Bluetooth® and WDCT. Due to the ramp-control feature and a very low quiescent current, an external switch transistor for VS is not required. Figure 1-1. Block Diagram RX_ON PU VS_LNA TX TX/RX/ Standby Control RX Bluetooth/ISM 2.4-GHz Front-end IC T7024 SWITCH_OUT R_SWITCH LNA_OUT LNA LNA_IN V1_PA RAMP V2_PA PA_IN PA V3_PA_OUT 4533I–BLURF–01/09 2. Pin Configuration Figure 2-1. Pinning QFN20 VS_LNA LNA_IN 7 GND GND 8 10 9 V3_PA_OUT V3_PA_OUT V3_PA_OUT GND RAMP GND 6 5 4 11 12 13 14 15 16 17 18 19 20 SWITCH_OUT R_SWITCH PU RX_ON LNA_OUT T7024 3 2 1 GND V2_PA V2_PA Table 2-1. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Slug Pin Description Symbol LNA_OUT RX_ON PU R_SWITCH SWITCH_OUT GND LNA_IN GND VS_LNA GND V3_PA_OUT V3_PA_OUT V3_PA_OUT GND RAMP V2_PA V2_PA GND V1_PA PA_IN GND Function Low-noise amplifier output RX active high Power-up active high Resistor to GND sets the PIN diode current Switched current output for PIN diode Ground Low-noise amplifier input Ground Supply voltage input for low-noise amplifier Ground Inductor to power supply and matching network for power amplifier output Inductor to power supply and matching network for power amplifier output Inductor to power supply and matching network for power amplifier output Ground Power ramping control input Inductor to power supply for power amplifier Inductor to power supply for power amplifier Ground Supply voltage for power amplifier Power amplifier input Ground 2 T7024 4533I–BLURF–01/09 V1_PA PA_IN T7024 3. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Supply voltage Pins VS_LNA, V1_PA, V2_PA, V3_PA_OUT Junction temperature Storage temperature RF input power LNA RF input power PA Symbol VS Tj Tstg PinLNA PinPA Value 6 150 –40 to +125 5 10 Unit V °C °C dBm dBm Electrostatic sensitive device. Observe precautions for handling. 4. Thermal Resistance Parameters Junction ambient QFN20, slug soldered on PCB Symbol RthJA Value 27 Unit K/W 5. Handling Do not operate this part near strong electrostatic fields. This IC meets class 1 ESD test requirement (HBM in accordance to EIA/JESD22-A114-A (October 97) and class A ESD test requirement (MM) in accordance to EIA/JESD22-A115A. 6. Operating Range All voltages are referred to ground (pins GND and slug). Power supply points are VS_LNA, V1_PA, V2_PA, V3_PA_OUT. The table represents the sum of all supply currents depending on the TX/RX mode. Parameters Supply voltage Pins V1_PA, V2_PA and V3_PA_OUT Supply voltage, pin VS_LNA Supply current TX Supply current RX Standby current, PU = 0 Ambient temperature Symbol VS VS IS IS IS_standby Tamb –25 Min. 2.7 2.7 Typ. 3.0 3.0 165 8 10 +25 +85 Max. 4.6 5.5 Unit V V mA mA µA °C 3 4533I–BLURF–01/09 7. Electrical Characteristics Test conditions (unless otherwise specified): VS = 3.0V, Tamb = 25°C Parameters Power Amplifier Supply voltage Supply current Standby current Frequency range Gain-control range Power gain maximum Power gain minimum Ramping voltage maximum Ramping voltage minimum Ramping current maximum Power-added efficiency Saturated output power Input matching(2) Output matching(2) Harmonics at Psat = 23 dBm (1) Test Conditions Pins V1_PA, V2_PA, V3_PA_OUT TX RX (PA off), VRAMP ≤ 0.1V Standby TX TX TX, pin PA_IN to V3_PA_OUT TX, pin PA_IN to V3_PA_OUT TX, power gain (maximum) Pin RAMP TX, power gain (minimum) Pin RAMP TX, VRAMP = 1.75V, pin RAMP TX TX, input power = 0 dBm referred to pins V3_PA_OUT TX, pin PA_IN TX, pins V3_PA_OUT TX, pins V3_PA_OUT TX, pins V3_PA_OUT Standby, pin SWITCH_OUT RX TX at 100Ω TX at 1.2 kΩ TX at 33 kΩ TX at ∞ Symbol Min. Typ. Max. Unit VS IS_TX IS_RX IS_standby f ΔGp Gp Gp VRAMP max VRAMP min IRAMP max PAE Psat Load VSWR Load VSWR 2 fo 3 fo IS_O_standby IS_O_RX IS_O_100 IS_O_1k2 IS_O_33k IS_O_R VS IS IS 2.7 3.0 165 4.6 10 10 V mA µA µA GHz dB dB dB V V 2.4 60 28 –40 1.7 1.75 0.1 42 30 2.5 33 –17 1.83 0.5 35 22 40 23 < 1.5:1 < 1.5:1 –30 –30 1 1 1.7 7 17 19 2.7 3.0 8 5.5 9 0.5 24 mA % dBm dBc dBc µA µA mA mA mA mA V mA mA T/R Switch Driver (Current Programming by External Resistor from R_SWITCH to GND) Switch-out current output Low-noise Amplifier(3) Supply voltage Supply current Supply current (LNA and control logic) Notes: All, pin VS_LNA RX TX (control logic active) Pin VS_LNA 1. Power amplifier shall be unconditionally stable, maximum duty cycle 100%, true CW operation, maximum load mismatch and duration: load VSWR = 10:1 (all phases) 10s, ZG = 50Ω. 2. With external matching network, load impedance 50Ω. 3. Low-noise amplifier shall be unconditionally stable. 4. With external matching components. 5. LNA gain can be adjusted with RX_ON voltage according to Figure 9-10 on page 9. Please note, that for RX_ON below 1.4V the T/R switch driver switches to TX mode. 4 T7024 4533I–BLURF–01/09 T7024 7. Electrical Characteristics (Continued) Test conditions (unless otherwise specified): VS = 3.0V, Tamb = 25°C Parameters Standby current Frequency range Power gain (5) Test Conditions Standby, pin VS_LNA RX RX, pin LNA_IN to LNA_OUT RX RX, referred to pin LNA_OUT RX RX, pin LNA_IN RX, pin LNA_OUT (5) Symbol Min. Typ. Max. Unit IS_standby f Gp NF O1dB IIP3 VSWRin VSWRout ViH ViL IiH IiL 2.4 0 –9 –16 2.4 15 1 16 2.1 –7 –14 10 2.5 19 2.3 –6 –13 2:1 2:1 VS, LNA 0.5 µA GHz dB dB dBm dBm Noise figure Gain compression 3 -order input interception point Input matching (4) rd Output matching(4) Logic Input Levels (RX_ON, PU) High input level Low input level High input current Low input current Notes: = ‘1’ pins RX_ON and PU = ‘0’ = ‘1’ ViH = 2.4V = ‘0’ V V µA µA 40 60 0.2 1. Power amplifier shall be unconditionally stable, maximum duty cycle 100%, true CW operation, maximum load mismatch and duration: load VSWR = 10:1 (all phases) 10s, ZG = 50Ω. 2. With external matching network, load impedance 50Ω. 3. Low-noise amplifier shall be unconditionally stable. 4. With external matching components. 5. LNA gain can be adjusted with RX_ON voltage according to Figure 9-10 on page 9. Please note, that for RX_ON below 1.4V the T/R switch driver switches to TX mode. 8. Control Logic PA and LNA/Antenna Switch Driver PU 0 0 0 0 1 1 1 1 Notes: RX_ON 0 0 1 1 0 0 1 1 Ramp(1) 0 1 0 1 0 1 0 1 PA off on off on off on off on LNA off off on on off off on on Antenna Switch Driver off off off off on on off off Operation Mode standby (2) (3) (4) (4) TX RX (5) 1. “0” = VRAMP ≤0.1V, “1” = VRAMP typically 1.75V, 1.3V < VRAMP < 1.83V controls gain and output power, compare Figure 9-5 on page 7 2. Only for special operation, e.g. only PA operation, no LNA/switch driver operation 3. Only for special operation, e.g. no switch driver operation 4. Only for special operation 5. Only for special operation, e.g. separate TX/RX antennas, TX and RX operation at the same time 5 4533I–BLURF–01/09 9. Typical Operating Characteristics Figure 9-1. LNA: Gain and Noise Figure versus Frequency 25 5 20 Gain 4 Gain (dB) NF 10 2 5 1 0 2000 2200 2400 2600 2800 0 3000 Frequency (MHz) Figure 9-2. LNA: NF and Gain versus Temperature 2.5 2.0 1.5 NF VS = 3V Relative gain relative NF (dB) 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -40 -20 0 20 40 60 80 Gain Temperature (°C) Figure 9-3. LNA: Typical Switch-out Current versus Rswitch 2.0 16 IS_O (mA) 12 8 4 0 1 10 100 1000 10000 100000 1000000 Rswitch (Ω) 6 T7024 4533I–BLURF–01/09 NF (dB) 15 3 T7024 Figure 9-4. PA: Output Power and PAE versus Supply Voltage 50 250 Pout (dBm), PAE (%) 40 PAE I_S_TX 220 30 Pout 190 20 f = 2.4 GHz Vramp = 1.8V PinPA = 0 dBm 160 10 130 0 2.7 3.1 3.5 3.9 4.3 100 4.7 Supply Voltage (V) Figure 9-5. PA: Output Power and PAE versus Ramp Voltage 50 PAE 250 Pout (dBm), PAE (%) 30 Pout 200 10 150 -10 I_S_TX -30 f = 2.4 GHz VS = 3V PinPA = 0 dBm 100 50 -50 1.2 1.4 1.6 1.8 0 2.0 Vramp (V) Figure 9-6. PA: Output Power and PAE versus Input Power 50 300 PAE Gain Pout (dBm), PAE (%), Gp (dB) 40 30 20 10 0 Pout I_S_TX VS = 3V f = 2.4 GHz Vramp = 1.8V PinPA = 0 dBm 250 200 150 100 50 0 -10 -40 -30 -20 -10 0 -10 Input Power (dBm) IS_TX (mA) IS_TX (mA) IS_TX (mA) 7 4533I–BLURF–01/09 Figure 9-7. PA: Output Power and PAE versus Frequency 50 PAE 250 Pout (dBm), PAE (%) 40 I_S_TX 200 30 150 20 Pout 10 VS = 3V Vramp = 1.8V PinPA = 0 dBm 100 50 0 2400 2420 2440 2460 2480 0 2500 Frequency (MHz) Figure 9-8. LNA: Supply Current versus Temperature 8.0 7.8 Supply current (mA) 7.6 7.4 7.2 7.0 6.8 6.6 6.4 6.2 6.0 -40 -20 0 20 40 60 80 Temperature (°C) Figure 9-9. PA: Pout versus VRAMP and Temperature 30 f = 2.4 GHz VS = 3V Pin = 0 dBm 20 5 Pout (dBm) 10 25 0 80 -15 -10 -40°C -20 1.0 1.2 1.4 1.6 1.8 Vramp (V) 8 T7024 4533I–BLURF–01/09 IS_TX (mA) T7024 Figure 9-10. LNA Gain (dB) versus RX_ON (V) 20 15 10 5 Gain (dB) VS = 3V 0 -5 -10 -15 -20 -25 1 1.5 2 2.5 3 RX_ON (V) 10. Input/Output Circuits Figure 10-1. Input Circuit PA_IN/V1_PA V1_PA PA_IN GND Figure 10-2. Input Circuit RAMP/V1_PA V1_PA RAMP 9 4533I–BLURF–01/09 Figure 10-3. Input Circuit V2_PA V2_PA GND Figure 10-4. Input/Output Circuit V3_PA_OUT V3_PA_OUT GND Figure 10-5. Input Circuit SWITCH_OUT/R_SWITCH V1_PA SWITCH_OUT R_SWITCH GND 10 T7024 4533I–BLURF–01/09 T7024 Figure 10-6. Input Circuit LNA_IN/VS_LNA VS_LNA LNA_IN GND Figure 10-7. Input Circuit PU/RX_ON VS_LNA LNA_IN / PU Figure 10-8. Output Circuit LNA_OUT VS_LNA LNA_OUT GND 11 4533I–BLURF–01/09 Figure 10-9. Typical Application T7024 LNA_OUT PA_IN V1_PA V2_PA 2.2 pF 1 pF 3.3 pF 20 19 18 17 16 1 PX_ON PU 2 3 4 R1 is selected with DIL-switch R1 Var 5 6 7 8 9 10 0.8 pF Pin diode replaced by LED on application board 15 14 PA_RAMP T7024 13 12 11 harm. termination 2.2 pF 1.8 pF 18 nH Switch_OUT LNA_IN VS_LNA V3_PA PA_OUT blocking capacitors depending on application 12 T7024 4533I–BLURF–01/09 T7024 11. Ordering Information Extended Type Number T7024-PGPM T7024-PGQM Demoboard-T7024-PGM Package QFN20 QFN20 QFN20 Remarks Taped and reeled Pb free, halogen free Taped and reeled Pb free, halogen free Evaluation board QFN MOQ 1500 pcs. 6000 pcs. 1 12. Package Information Package: QFN 20 - 5 x 5 Exposed pad 3.1 x 3.1 Dimensions in mm Not indicated tolerances ± 0.05 0.9±0.1 0.05-0.05 20 1 15 16 +0 5 3.1 20 1 technical drawings according to DIN specifications 5 0.28 0.6 11 10 6 5 0.65 nom. Drawing-No.: 6.543-5094.01-4 Issue: 1; 19.12.02 2.6 13 4533I–BLURF–01/09 13. Recommended PCB Land Pattern Figure 13-1. Recommended PCB Land Pattern B E D A F C Table 13-1. Recommended PCB Land Pattern Signs Sign A B C D E F Description Distance of vias Size of slug pattern Distance slug to pins Diameter of vias Width of pin pattern Distance of pin pattern Size 1.6 mm 3.1 mm 0.33 mm 1 mm 0.3 mm 0.33 mm 14. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. 4533I-BLURF-01/09 4533H-BLURF-07/07 History • PSSO20 package variant deleted • Put datasheet in a new template • Page 1: Block diagram changed • Page 13: Figure 10-8 changed 14 T7024 4533I–BLURF–01/09 Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 International Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-en-Yvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Product Contact Web Site www.atmel.com Technical Support cordless_phone@atmel.com Sales Contact www.atmel.com/contacts Literature Requests www.atmel.com/literature Disclaimer: T he information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2009 Atmel Corporation. All rights reserved. A tmel®, logo and combinations thereof, and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. 4533I–BLURF–01/09