T89C51AC2-SLSI-M

T89C51AC2 8-bit MCU with 32K bytes Flash, 10 bits A/D and EEPROM 1. Description The T89C51AC2 is a high performance CMOS FLASH version of the 80C51 CMOS single chip 8-bit microcontrollers. It contains a 32Kbytes Flash memory block for program and data. The 16K bytes or 32K bytes FLASH memory can be programmed either in parallel mode or in serial mode with the ISP capability or with software. The programming voltage is internally generated from the standard VCC pin. The T89C51AC2 retains all features of the 80C52 with 256 bytes of internal RAM, a 7-source 4-level interrupt controller and three timer/counters. In addition, the T89C51AC2 has a 10 bits A/D converter, a 2Kbytes Boot Flash Memory, 2 Kbytes EEPROM for data, a Programmable Counter Array, an XRAM of 1024 byte, a Hardware Watchdog Timer and a more versatile serial channel that facilitates multiprocessor communication (EUART). The fully static design of the T89C51AC2 allows to reduce system power consumption by bringing the clock frequency down to any value, even DC, without loss of data. The T89C51AC2 has 2 software-selectable modes of reduced activity and 8 bit clock prescaler for further reduction in power consumption. In the Idle mode the CPU is frozen while the peripherals and the interrupt system are still operating. In the power-down mode the RAM is saved and all other functions are inoperative. The added features of the T89C51AC2 make it more powerful for applications that need A/D conversion, pulse width modulation, high speed I/O and counting capabilities such as industrial control, consumer goods, alarms, motor control, ... While remaining fully compatible with the 80C51 it offers a superset of this standard microcontroller. In X2 mode a maximum external clock rate of 20 MHz reaches a 300 ns cycle time. 2. Features • 80C51 core architecture: • • • • • • • • • 256 bytes of on-chip RAM 1Kbytes of on-chip XRAM 32 Kbytes of on-chip Flash memory 2 Kbytes of on-chip Flash for Bootloader 2 Kbytes of on-chip EEPROM 14-source 4-level interrupt Three 16-bit timer/counter Full duplex UART compatible 80C51 maximum crystal frequency 40 MHz. In X2 mode, 20 MHz (CPU core, 40 MHz) • Five ports: 32 + 2 digital I/O lines • Five channel 16-bit PCA with: - PWM (8-bit) - High-speed output - Timer and edge capture • Double Data Pointer • 21 bit watchdog timer (including 7 programmable bits) • A 10-bit resolution analog to digital converter (ADC) with 8 multiplexed inputs • 20 microsecond conversion time • Two conversion modes On-chip emulation Logic (enhanced Hook system) • Idle mode • Power down mode Power supply: 5V +/- 10% (or 3V** +/- 10%) • • Power saving modes: • • Temperature range: Industrial (-40 to +85C) • Packages: TQFP44, PLCC44 Draft.A- March 30, 2001 1 Preview - Confidential T89C51AC2 3. Block Diagram T2EX RxD TxD Vcc Vss PCA ECI XTAL1 XTAL2 ALE PSEN CPU EA RD WR Timer 0 Timer 1 INT Ctrl Parallel I/O Ports & Ext. Bus Port 0 Port 1 Port 2 Port 3 Port 4 Watch Dog Emul Unit 10 bit ADC UART RAM 256x8 Flash 32kx 8 ERAM Boot EE 1kx8 loader PROM 2kx8 2kx8 PCA Timer2 C51 CORE IB-bus P1(1) INT0 RESET INT1 (1): 8 analog Inputs / 8 Digital I/O (2): 2-Bit I/O Port 2 P4(2) P2 T0 T1 P0 P3 Draft.A - March 30, 2001 Preview - Confidential T2 T89C51AC2 4. Pin Configuration P1.3 / AN3 / CEX0 P1.2 / AN2 / ECI P1.1 / AN1 / T2EX P1.0 / AN 0 / T2 VAREF VAGND RESET VSS VCC XTAL1 XTAL2 P1.4 / AN4 / CEX1 P1.5 / AN5 / CEX2 P1.6 / AN6 / CEX3 P1.7 / AN7 / CEX4 EA P3.0 / RxD P3.1 / TxD P3.2 / INT0 P3.3 / INT1 P3.4 / T0 P3.5 / T1 7 8 9 10 11 12 13 14 15 16 17 6 5 4 3 2 1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 PLCC44 ALE PSEN P0.7 / AD7 P0.6 / AD6 P0.5 / AD5 P0.4 / AD4 P0.3 / AD3 P0.2 / AD2 P0.1 / AD1 P0.0 / AD0 P2.0 / A8 44 43 42 41 40 39 38 37 36 35 34 P1.4 / AN4 / CEX1 P1.5 / AN5 / CEX2 P1.6 / AN6 / CEX3 P1.7 / AN7 / CEX4 EA P3.0 / RxD P3.1 / TxD P3.2 / INT0 P3.3 / INT1 P3.4 / T0 P3.5 / T1 P1.3 / AN3 / CEX0 P1.2 / AN2 / ECI P1.1 / AN1 / T2EX P1.0 / AN 0 / T2 VAREF VAGND RESET VSS VCC XTAL1 XTAL2 P3.6 / WR P3.7 / RD P4.0 P4.1 P2.7 / A15 P2.6 / A14 P2.5 / A13 P2.4 / A12 P2.3 / A11 P2.2 / A10 P2.1 / A9 18 19 20 21 22 23 24 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 TQFP44 ALE PSEN P0.7 / AD7 P0.6 / AD6 P0.5 / AD5 P0.4 /AD4 P0.3 /AD3 P0.2 /AD2 P0.1 /AD1 P0.0 /AD0 P2.0 / A8 1213 14 15 16 17 18 19 20 2122 P3.6 / WR P3.7 / RD P4.0 P4.1 P2.7 / A15 P2.6 / A14 P2.5 / A13 P2.4 / A12 P2.3 / A11 P2.2 / A10 P2.1 / A9 Draft.A - March 30, 2001 3 Preview - Confidential T89C51AC2 Table 1. Pin Description Pin Name VSS VCC VAREF VAGND Type GND Circuit ground potential. Description Supply voltage during normal, idle, and power-down operation. Reference Voltage for ADC Reference Ground for ADC Port 0: is an 8-bit open drain bi-directional I/O port. Port 0 pins that have 1’s written to them float, and in this state can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external Program and Data Memory. In this application it uses strong internal pullups when emitting 1’s. Port 0 also outputs the code bytes during program validation. External pull-ups are required during program verification. In the T89C51AC2 Port 0 can sink or source 5mA. It can drive CMOS inputs without external pull-ups. Port 1: is an 8-bit bi-directional I/O port with internal pull-ups. Port 1 pins can be used for digital input/output or as analog inputs for the Analog Digital Converter (ADC). Port 1 pins that have 1’s written to them are pulled high by the internal pull-up transistors and can be used as inputs in this state. As inputs, Port 1 pins that are being pulled low externally will be the source of current (IIL, on the datasheet) because of the internal pull-ups. Port 1 pins are assigned to be used as analog inputs via the ADCCF register. As a secondary digital function, port 1 contains the Timer 2 external trigger and clock input; the PCA external clock input and the PCA module I/O. P1.0 / AN0 / T2 Analog input channel 0, External clock input for Timer/counter2. P1.1 / AN1 / T2EX Analog input channel 1, Trigger input for Timer/counter2. P1.2 / AN2 / ECI Analog input channel 2, PCA external clock input. P1.3 / AN3 / CEX0 Analog input channel 3, PCA module 0 Entry of input/PWM output. P1.4 / AN4 / CEX1 Analog input channel 4, PCA module 1 Entry of input/PWM output. P1.5 / AN5 / CEX2 Analog input channel 5, PCA module 2 Entry of input/PWM output. P1.6 / AN6 / CEX3 Analog input channel 6, PCA module 3 Entry of input/PWM output. P1.7 / AN7 / CEX4 Analog input channel 7, PCA module 4 Entry ot input/PWM output. Port 1 receives the low-order address byte during EPROM programming and program verification. In the T89C51AC2 Port 1 can sink or source 5mA. It can drive CMOS inputs without external pull-ups. Port 2: Is an 8-bit bi-directional I/O port with internal pull-ups. Port 2 pins that have 1’s written to them are pulled high by the internal pull-ups and can be used as inputs in this state. As inputs, Port 2 pins that are being pulled low externally will be a source of current (IIL, on the datasheet) because of the internal pull-ups. Port 2 emits the high-order address byte during accesses to the external Program Memory and during accesses to external Data Memory that uses 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pullups when emitting 1’s. During accesses to external Data Memory that use 8 bit addresses (MOVX @Ri), Port 2 transmits the contents of the P2 special function register. It also receives high-order addresses and control signals during program validation. In the T89C51AC2 Port 2 can sink or source 5mA. It can drive CMOS inputs without external pull-ups. P0.0:7 I/O P1.0:7 I/O P2.0:7 I/O 4 Draft.A - March 30, 2001 Preview - Confidential T89C51AC2 Pin Name Type Description Port 3: Is an 8-bit bi-directional I/O port with internal pull-ups. Port 3 pins that have 1’s written to them are pulled high by the internal pull-up transistors and can be used as inputs in this state. As inputs, Port 3 pins that are being pulled low externally will be a source of current (IIL, on the datasheet) because of the internal pull-ups. The output latch corresponding to a secondary function must be programmed to one for that function to operate (except for TxD and WR). The secondary functions are assigned to the pins of port 3 as follows: P3.0 / RxD: Receiver data input (asynchronous) or data input/output (synchronous) of the serial interface P3.1 / TxD: Transmitter data output (asynchronous) or clock output (synchronous) of the serial interface P3.2 / INT0: External interrupt 0 input / timer 0 gate control input P3.3 / INT1: External interrupt 1 input / timer 1 gate control input P3.4 / T0: Timer 0 counter input P3.5 / T1: Timer 1 counter input P3.6 / WR: External Data Memory write strobe; latches the data byte from port 0 into the external data memory P3.7 / RD: External Data Memory read strobe; Enables the external data memory. In the T89C51AC2 Port 3 can sink or source 5mA. It can drive CMOS inputs without external pull-ups. Port 4: Is an 2-bit bi-directional I/O port with internal pull-ups. Port 4 pins that have 1’s written to them are pulled high by the internal pull-ups and can be used as inputs in this state. As inputs, Port 4 pins that are being pulled low externally will be a source of current (IIL, on the datasheet) because of the internal pullup transistor. In the T89C51AC2 Port 3 can sink or source 5mA. It can drive CMOS inputs without external pull-ups. RESET I/O Reset: A high level on this pin during two machine cycles while the oscillator is running resets the device. An internal pull-down resistor to VSS permits power-on reset using only an external capacitor to VCC. ALE: An Address Latch Enable output for latching the low byte of the address during accesses to the external memory. The ALE is activated every 1/6 oscillator periods (1/3 in X2 mode) except during an external data memory access. When instructions are executed from an internal FLASH (EA = 1), ALE generation can be disabled by the software. PSEN: The Program Store Enable output is a control signal that enables the external program memory of the bus during external fetch operations. It is activated twice each machine cycle during fetches from the external program memory. (However, when executing outside of the external program memory two activations of PSEN are skipped during each access to the external Data memory). The PSEN is not activated during fetches from the internal data memory. EA: EA I When External Access is held at the high level, instructions are fetched from the internal FLASH when the program counter is less then 8000H. When held at the low level, CANARY fetches all instructions from the external program memory. XTAL1: Input of the inverting oscillator amplifier and input of the internal clock generator circuits. To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected. To operate above a frequency of 16 MHz, a duty cycle of 50% should be maintained. XTAL2: Output from the inverting oscillator amplifier. P3.0:7 I/O P4.0:1 I/O ALE O PSEN O XTAL1 I XTAL2 O Draft.A - March 30, 2001 5 Preview - Confidential T89C51AC2 4.1. I/O Configurations Each Port SFR operates via type-D latches, as illustrated in Figure 1 for Ports 3 and 4. A CPU "write to latch" signal initiates transfer of internal bus data into the type-D latch. A CPU "read latch" signal transfers the latched Q uotput onto the internal bus. Similarly, a "read pin" signal transfers the logical level of the Port pin. Some Port data instructions activate the "read latch" signal while others activate the "read pin" signal. Latch instructions are referred to as Read-Modify-Write instructions. Each I/O line may be independently programmed as input or output. 4.2. Port 1, Port 3 and Port 4 Figure 1 shows the structure of Ports 1 and 3, which have internal pull-ups. An external source can pull the pin low. Each Port pin can be configured either forgeneral-purpose I/O or for its alternate input output function. To use a pin for general-purpose output, set or clear the corresponding bit in the Px register (x=1,3 or 4). To use a pin for general purpose input, set the bit in the Px register. This turns off the output FET drive. To configure a pin for its alternate function, set the bit in the Px register. When the latch is set, the "alternate output function" signal controls the output level (see Figure 1). The operation of Ports 1, 3 and 4 is discussed further in "quasi-Bidirectional Port Operation" paragraph. VCC ALTERNATE OUTPUT FUNCTION INTERNAL PULL-UP (1) READ LATCH INTERNAL BUS WRITE TO LATCH D P1.X Q P3.X P4.X LATCH CL P1.x P3.x P4.x READ PIN ALTERNATE INPUT FUNCTION NOTE: 1. The internal pull-up can be disabled on P1 when analog function is selected. Figure 1. Port 1, Port 3 and Port 4 Structure 4.3. Port 0 and Port2 Ports 0 and 2 are used for general-purpose I/O or as the external address/data bus. Port 0, shown in Figure 2, differs from the other Ports in not having internal pull-ups. Figure 3 shows the structure of Port 2. An external source can pull a Port 2 pin low. To use a pin for general-purpose output, set or clear the corresponding bit in the Px register (x=0 or 2). To use a pin for general purpose input, set the bit in the Px register to turn off the output driver FET. 6 Draft.A - March 30, 2001 Preview - Confidential T89C51AC2 ADDRESS LOW/ CONTROL DATA VDD READ LATCH 1 (2) P0.x (1) INTERNAL BUS WRITE TO LATCH D Q P0.X LATCH 0 READ PIN NOTE: 1. Port 0 is precluded from use as general purpose I/O Ports when used as address/data bus drivers. 2. Port 0 internal strong pull-ups assist the logic-one output for memory bus cycles only. Except for these bus cycles, the pull-up FET is off, Port 0 outputs are open-drain. Figure 2. Port 0 Structure ADDRESS HIGH/ CONTROL DATA VDD INTERNAL PULL-UP (2) READ LATCH 1 P2.x (1) INTERNAL BUS WRITE TO LATCH D Q P2.X LATCH 0 READ PIN NOTE: 1. Port 2 is precluded from use as general purpose I/O Ports when as address/data bus drivers. 2. Port 2 internal strong pull-ups FET (P1 in FiGURE) assist the logic-one output for memory bus cyle. Figure 3. Port 2 Structure When Port 0 and Port 2 are used for an external memory cycle, an internal control signal switches the outputdriver input from the latch output to the internal address/data line. Draft.A - March 30, 2001 7 Preview - Confidential T89C51AC2 4.4. Read-Modify-Write Instructions Some instructions read the latch data rather than the pin data. The latch based instructions read the data, modify the data and then rewrite the latch. These are called "Read-Modifiy-Write" instructions. Below is a complete list of these special instructions (see Table 2). When the destination operand is a Port or a Port bit, these instructions read the latch rather than the pin: Table 2. Read-Modify-Write Instructions Instruction ANL ORL XRL JBC CPL INC DEC DJNZ MOV Px.y, C CLR Px.y SET Px.y logical AND logical OR logical EX-OR jump if bit = 1 and clear bit complement bit increment decrement decrement and jump if not zero move carry bit to bit y of Port x clear bit y of Port x set bit y of Port x Description ANL P1, A ORL P2, A XRL P3, A Example JBC P1.1, LABEL CPL P3.0 INC P2 DEC P2 DJNZ P3, LABEL MOV P1.5, C CLR P2.4 SET P3.3 It is not obvious the last three instructions in this list are Read-Modify-Write instructions. These instructions read the port (all 8 bits), modify the specifically addressed bit and write the new byte back to the latch. These ReadModify-Write instructions are directed to the latch rather than the pin in order to avoid possible misinterpretation of voltage (and therefore, logic)levels at the pin. For example, a Port bit used to drive the base of an external bipolar transistor can not rise above the transistor’s base-emitter junction voltage (a value lower than VIL). With a logic one written to the bit, attemps by the CPU to read the Port at the pin are misinterpreted as logic zero. A read of the latch rather than the pins returns the correct logic-one value. 4.5. Quasi-Bidirectional Port Operation Port 1, Port 2, Port 3 and Port 4 have fixed internal pull-ups and are referred to as "quasi-bidirectional" Ports. When configured as an input, the pin impedance appears as logic one and sources current in response to an external logic zero condition. Port 0 is a "true bidirectional" pin. The pins float when configured as input. Resets write logic one to all Port latches. If logical zero is subsequently written to a Port latch, it can be returned to input condions by a logical one written to the latch. NOTE: Port latch values change near the end of Read-Modify-Write insruction cycles. Output buffers (and therefore the pin state) update early in the instruction after Read-Modify-Write instruction cycle. Logical zero-to-one transitions in Port 1, Port 2, Port 3 and Port 4 use an additional pull-up (p1) to aid this logic transition (see Figure 4.). This increases switch speed. This extra pull-up sources 100 times normal internal circuit current during 2 oscillator clock periods. The internal pull-ups are field-effect transistors rather than linear resistors. Pull-ups consist of three p-channel FET (pFET) devices. A pFET is on when the gate senses logical zero and off when the gate senses logical one. pFET #1 is turned on for two oscillator periods immediately after a zero-to-one transition in the Port latch. A logical one at the Port pin turns on pFET #3 (a weak pull-up) through the inverter. This inverter and pFET pair form a latch to drive logical one. pFET #2 is a very weak pull-up switched on whenever the associated nFET is switched off. This is traditional CMOS switch convention. Current strengths are 1/10 that of pFET #3. 8 Draft.A - March 30, 2001 Preview - Confidential T89C51AC2 2 Osc. PERIODS VCC p1(1) VCC p2 VCC p3 P1.x P2.x P3.x P4.x OUTPUT DATA n INPUT DATA READ PIN NOTE: 1. Port 2 p1 assists the logic-one output for memory bus cycles. Figure 4. Internal Pull-Up Configurations Draft.A - March 30, 2001 9 Preview - Confidential T89C51AC2 5. SFR Mapping The Special Function Registers (SFRs) of the T89C51AC2 fall into the following categories: Table 3. C51 Core SFRs Mnemonic Add ACC B PSW SP DPL DPH E0h Accumulator F0h B Register Name 7 6 5 4 3 2 1 0 D0h Program Status Word 81h 82h 83h Stack Pointer LSB of SPX Data Pointer Low byte LSB of DPTR Data Pointer High byte MSB of DPTR Table 4. I/O Port SFRs Mnemonic Add P0 P1 P2 P3 P4 80h 90h Port 0 Port 1 Name 7 6 5 4 3 2 1 0 A0h Port 2 B0h Port 3 C0h Port 4 (x2) Table 5. Timers SFRs Mnemonic Add TH0 TL0 TH1 TL1 TH2 TL2 TCON TMOD T2CON T2MOD RCAP2H RCAP2L WDTRST WDTPRG Name 7 6 5 4 3 2 1 0 8Ch Timer/Counter 0 High byte 8Ah Timer/Counter 0 Low byte 8Dh Timer/Counter 1 High byte 8Bh Timer/Counter 1 Low byte CDh Timer/Counter 2 High byte CCh Timer/Counter 2 Low byte 88h 89h Timer/Counter 0 and 1 control Timer/Counter 0 and 1 Modes TF1 GATE1 TF2 TR1 C/T1# EXF2 TF0 M11 RCLK TR0 M01 TCLK IE1 GATE0 EXEN2 IT1 C/T0# TR2 IE0 M10 C/T2# T2OE IT0 M00 CP/RL2# DCEN C8h Timer/Counter 2 control C9h Timer/Counter 2 Mode Timer/Counter 2 Reload/Capture CBh High byte CAh Timer/Counter 2 Reload/Capture Low byte A6h WatchDog Timer Reset A7h WatchDog Timer Program S2 S1 S0 Table 6. Serial I/O Port SFRs Mnemonic Add SCON SBUF SADEN 98h 99h Name Serial Control Serial Data Buffer 7 FE/SM0 6 SM1 5 SM2 4 REN 3 TB8 2 RB8 1 TI 0 RI B9h Slave Address Mask 10 Draft.A - March 30, 2001 Preview - Confidential T89C51AC2 Mnemonic Add SADDR Name 7 6 5 4 3 2 1 0 A9h Slave Address Table 7. PCA SFRs Mnemonic Add CCON CMOD CL CH CCAPM0 CCAPM1 CCAPM2 CCAPM3 CCAPM4 CCAP0H CCAP1H CCAP2H CCAP3H CCAP4H CCAP0L CCAP1L CCAP2L CCAP3L CCAP4L Name 7 CF CIDL 6 CR WDTE 5 - 4 CCF4 - 3 CCF3 - 2 CCF2 CPS1 1 CCF1 CPS0 0 CCF0 ECF D8h PCA Timer/Counter Control D9h PCA Timer/Counter Mode E9h PCA Timer/Counter Low byte F9h DAh DBh DCh DDh DEh FAh FBh FCh FDh FEh EAh EBh ECh EDh EEh PCA Timer/Counter High byte PCA PCA PCA PCA PCA Timer/Counter Timer/Counter Timer/Counter Timer/Counter Timer/Counter Mode Mode Mode Mode Mode 0 1 2 3 4 - ECOM0 ECOM1 ECOM2 ECOM3 ECOM4 CCAP0H6 CCAP1H6 CCAP2H6 CCAP3H6 CCAP4H6 CCAP0L6 CCAP1L6 CCAP2L6 CCAP3L6 CCAP4L6 CAPP0 CAPP1 CAPP2 CAPP3 CAPP4 CCAP0H5 CCAP1H5 CCAP2H5 CCAP3H5 CCAP4H5 CCAP0L5 CCAP1L5 CCAP2L5 CCAP3L5 CCAP4L5 CAP0 CAP1 CAP2 CAP3 CAP4 CCAP0H4 CCAP1H4 CCAP2H4 CCAP3H4 CCAP4H4 CCAP0L4 CCAP1L4 CCAP2L4 CCAP3L4 CCAP4L4 MAT0 MAT1 MAT2 MAT3 MAT4 CCAP0H3 CCAP1H3 CCAP2H3 CCAP3H3 CCAP4H3 CCAP0L3 CCAP1L3 CCAP2L3 CCAP3L3 CCAP4L3 TOG0 TOG1 TOG2 TOG3 TOG4 CCAP0H2 CCAP1H2 CCAP2H2 CCAP3H2 CCAP4H2 CCAP0L2 CCAP1L2 CCAP2L2 CCAP3L2 CCAP4L2 PWM0 PWM1 PWM2 PWM3 PWM4 CCAP0H1 CCAP1H1 CCAP2H1 CCAP3H1 CCAP4H1 CCAP0L1 CCAP1L1 CCAP2L1 CCAP3L1 CCAP4L1 ECCF0 ECCF1 ECCF2 ECCF3 ECCF4 CCAP0H0 CCAP1H0 CCAP2H0 CCAP3H0 CCAP4H0 CCAP0L0 CCAP1L0 CCAP2L0 CCAP3L0 CCAP4L0 PCA Compare Capture Module 0 H PCA Compare Capture Module 1 H PCA Compare Capture Module 2 H PCA Compare Capture Module 3 H PCA Compare Capture Module 4 H PCA Compare Capture Module 0 L PCA Compare Capture Module 1 L PCA Compare Capture Module 2 L PCA Compare Capture Module 3 L PCA Compare Capture Module 4 L CCAP0H7 CCAP1H7 CCAP2H7 CCAP3H7 CCAP4H7 CCAP0L7 CCAP1L7 CCAP2L7 CCAP3L7 CCAP4L7 Table 8. Interrupt SFRs Mnemonic Add IEN0 IEN1 IPL0 IPH0 IPL1 IPH1 Name 7 EA - 6 AC PPC PPCH - 5 ET2 PT2 PT2H - 4 ES PS PSH - 3 ET1 PT1 PT1H - 2 EX1 PX1 PX1H - 1 ET0 EADC PT0 PT0H PADCL PADCH 0 EX0 PX0 PX0H - A8h Interrupt Enable Control 0 E8h Interrupt Enable Control 1 B8h Interrupt Priority Control Low 0 B7h Interrupt Priority Control High 0 F8h F7h Interrupt Priority Control Low 1 Interrupt Priority Control High1 Table 9. ADC SFRs Mnemonic Add ADCON ADCF ADCLK ADDH ADDL F3h F6h F2h F5h F4h ADC Control ADC Configuration ADC Clock ADC Data High byte ADC Data Low byte Name 7 CH7 ADAT9 - 6 PSIDLE CH6 ADAT8 - 5 ADEN CH5 ADAT7 - 4 ADEOC CH4 PRS4 ADAT6 - 3 ADSST CH3 PRS3 ADAT5 - 2 SCH2 CH2 PRS2 ADAT4 - 1 SCH1 CH1 PRS1 ADAT3 ADAT1 0 SCH0 CH0 PRS0 ADAT2 ADAT0 Draft.A - March 30, 2001 11 Preview - Confidential T89C51AC2 Table 10. Other SFRs Mnemonic Add PCON AUXR AUXR1 CKCON FCON EECON Name 7 SMOD1 FPL3 EEPL3 6 SMOD0 M(1) WDX2 FPL2 EEPL2 5 M0 ENBOOT PCAX2 FPL1 EEPL1 4 POF SIX2 FPL0 EEPL0 3 GF1 XRS1 GF3 T2X2 FPS - 2 GF0 XRS2 T1X2 FMOD1 - 1 PD EXTRAM T0X2 FMOD0 EEE 0 IDL A0 DPS X2 FBUSY EEBUSY 87hh Power Control 8Eh Auxiliary Register 0 A2h Auxiliary Register 1 8Fh Clock Control D1h FLASH Control D2h EEPROM Contol 12 Draft.A - March 30, 2001 Preview - Confidential T89C51AC2 Table 11. SFR’s mapping 0/8(1) F8h F0h E8h E0h D8h D0h C8h C0h B8h B0h A8h A0h 98h 90h 88h 80h IPL1 xxxx x000 B 0000 0000 IEN1 xxxx x000 ACC 0000 0000 CCON 00xx xx00 PSW 0000 0000 T2CON 0000 0000 P4 xxxx xx11 IPL0 x000 0000 P3 1111 1111 IEN0 0000 0000 P2 1111 1111 SCON 0000 0000 P1 1111 1111 TCON 0000 0000 P0 1111 1111 0/8(1) TMOD 0000 0000 SP 0000 0111 1/9 TL0 0000 0000 DPL 0000 0000 2/A TL1 0000 0000 DPH 0000 0000 3/B 4/C 5/D 6/E TH0 0000 0000 TH1 0000 0000 AUXR 0000 1000 CKCON 0000 0000 PCON 0000 0000 7/F SBUF 0000 0000 SADDR 0000 0000 AUXR1 0000 0000 WDTRST 1111 1111 WDTPRG xxxx x000 SADEN 0000 0000 IPH0 x000 0000 CMOD 00xx x000 FCON 0000 0000 T2MOD xxxx xx00 CCAPM0 x000 0000 EECON xxxx xx00 RCAP2L 0000 0000 RCAP2H 0000 0000 TL2 0000 0000 TH2 0000 0000 CANEN1 xx00 0000 CANEN2 0000 0000 CCAPM1 x000 0000 CCAPM2 x000 0000 CCAPM3 x000 0000 CCAPM4 x000 0000 CL 0000 0000 1/9 CH 0000 0000 2/A CCAP0H 0000 0000 ADCLK xx00 0000 CCAP0L 0000 0000 3/B CCAP1H 0000 0000 ADCON x000 0000 CCAP1L 0000 0000 4/C CCAP2H 0000 0000 ADDL 0000 0000 CCAP2L 0000 0000 5/D CCAP3H 0000 0000 ADDH 0000 0000 CCAP3L 0000 0000 6/E CCAP4H 0000 0000 ADCF 0000 0000 CCAP4L 0000 0000 IPH1 xxxx x000 7/F FFh F7h EFh E7h DFh D7h CFh C7h BFh B7h AFh A7h 9Fh 97h 8Fh 87h Note: 2. These registers are bit-addressable. Sixteen addresses in the SFR space are both byte-addressable and bit-addressable. The bit-addressable SFR’s are those whose address ends in 0 and 8. The bit addresses, in this area, are 0x80 through to 0xFF. Draft.A - March 30, 2001 13 Preview - Confidential T89C51AC2 6. Clock 6.1. Introduction The T89C51AC2 core needs only 6 clock periods per machine cycle. This feature, called ”X2”, provides the following advantages: • • • • Divides frequency crystals by 2 (cheaper crystals) while keeping the same CPU power. Saves power consumption while keeping the same CPU power (oscillator power saving). Saves power consumption by dividing dynamic operating frequency by 2 in operating and idle modes. Increases CPU power by 2 while keeping the same crystal frequency. In order to keep the original C51 compatibility, a divider-by-2 is inserted between the XTAL1 signal and the main clock input of the core (phase generator). This divider may be disabled by the software. An extra feature is available for selected hardware in the X2 mode. This feature allows starting of the CPU in the X2 mode, without starting in the standard mode. The hardware CPU X2 mode can be read and write via IAP (SetX2mode, ClearX2mode, ReadX2mode), see InSystem Programming section. These IAPs are detailed in the "In-System Programming" section. 6.2. Description The clock for the whole circuit and peripheral is first divided by two before being used by the CPU core and peripherals. This allows any cyclic ratio to be accepted on the XTAL1 input. In X2 mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to 60%. Figure 5. shows the clock generation block diagram. The X2 bit is validated on the XTAL1÷2 rising edge to avoid glitches when switching from the X2 to the STD mode. Figure 6 shows the mode switching waveforms. 14 Draft.A - March 30, 2001 Preview - Confidential T89C51AC2 X2 CKCON.0 PCON.0 IDL X2B Hardware byte XTAL1 ÷2 0 1 CPU Core Clock XTAL2 CPU CLOCK PD PCON.1 CPU Core Clock Symbol ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 1 FT0 Clock 0 1 FT1 Clock 0 1 FT2 Clock 0 1 0 FUart Clock 1 FPca Clock 0 1 0 FWd Clock X2 CKCON.0 PERIPH CLOCK Peripheral Clock Symbol WDX2 CKCON.6 PCAX2 CKCON.5 SIX2 CKCON.4 T2X2 CKCON.3 T1X2 CKCON.2 T0X2 CKCON.1 Figure 5. Clock CPU Generation Diagram Draft.A - March 30, 2001 15 Preview - Confidential T89C51AC2 XTAL1 XTAL2 X2 bit CPU clock STD Mode X2 Mode STD Mode Figure 6. Mode Switching Waveforms The X2 bit in the CKCON register (See Table 7) allows switching from 12 clock cycles per instruction to 6 clock cycles and vice versa. At reset, the standard speed is activated (STD mode). Setting this bit activates the X2 feature (X2 mode). CAUTION In order to prevent any incorrect operation while operating in the X2 mode, users must be aware that all peripherals using the clock frequency as a time reference (UART, timers...) will have their time reference divided by two. For example a free running timer generating an interrupt every 20 ms will then generate an interrupt every 10 ms. A UART with a 4800 baud rate will have a 9600 baud rate. 16 Draft.A - March 30, 2001 Preview - Confidential T89C51AC2 6.3. Register CKCON (S:8Fh) Clock Control Register 7 6 WDX2 5 PCAX2 4 SIX2 3 T2X2 2 T1X2 1 T0X2 0 X2 Bit Number Bit Mnemonic 7 - Description Reserved The value read from this bit is indeterminate. Do not set this bit. Watchdog clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. Programmable Counter Array clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. Enhanced UART clock (MODE 0 and 2) (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. Timer2 clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. Timer1 clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. Timer0 clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. CPU clock Clear to select 12 clock periods per machine cycle (STD mode) for CPU and all the peripherals. Set to select 6 clock periods per machine cycle (X2 mode) and to enable the individual peripherals "X2"bits. 6 WDX2 5 PCAX2 4 SIX2 3 T2X2 2 T1X2 1 T0X2 0 X2 NOTE: 1. This control bit is validated when the CPU clock bit X2 is set; when X2 is low, this bit has no effect. Reset Value = 0000 0000b Figure 7. CKCON Register Draft.A - March 30, 2001 17 Preview - Confidential T89C51AC2 7. Program/Code Memory 7.1. Introduction The T89C51AC2 implement 32 Kbytes of on-chip program/code memory. Figure 8 shows the split of internal and external program/code memory spaces depending on the product. The FLASH memory increases EPROM and ROM functionality by in-circuit electrical erasure and programming. Thanks to the internal charge pump, the high voltage needed for programming or erasing FLASH cells is generated on-chip using the standard VDD voltage. Thus, the FLASH Memory can be programmed using only one voltage and allows in application software programming commonly known as IAP. Hardware programming mode is also available using specific programming tool. FFFFh 32 Kbytes External Code 8000h 7FFFh1 32 Kbytes FLASH 0000h T89C51AC2 Figure 8. Program/Code Memory Organization Caution: 1. If the program executes exclusively from on-chip code memory (not from external memory), beware of executing code from the upper byte of on-chip memory (7FFFh) and thereby disrupt I/O Ports 0 and 2 due to external prefetch. Fetching code constant from this location does not affect Ports 0 and 2. 7.2. External Code Memory Access 7.2.1. Memory Interface The external memory interface comprises the external bus (port 0 and port 2) as well as the bus control signals (PSEN#, and ALE). Figure 9 shows the structure of the external address bus. P0 carries address A7:0 while P2 carries address A15:8. Data D7:0 is multiplexed with A7:0 on P0. Table 12 describes the external memory interface signals. 18 Draft.A - March 30, 2001 Preview - Confidential T89C51AC2 T89C51AC2 A15:8 P2 ALE AD7:0 P0 Latch A7:0 A7:0 D7:0 PSEN# OE A15:8 FLASH EPROM Figure 9. External Code Memory Interface Structure Table 12. External Data Memory Interface Signals Signal Name A15:8 AD7:0 ALE PSEN# Type O I/O O O Description Address Lines Upper address lines for the external bus. Address/Data Lines Multiplexed lower address lines and data for the external memory. Address Latch Enable ALE signals indicates that valid address information are available on lines AD7:0. Program Store Enable Output This signal is active low during external code fetch or external code read (MOVC instruction). Alternate Function P2.7:0 P0.7:0 - 7.2.2. External Bus Cycles This section describes the bus cycles the T89C51AC2 executes to fetch code (see Figure 10) in the external program/ code memory. External memory cycle takes 6 CPU clock periods. This is equivalent to 12 oscillator clock period in standard mode or 6 oscillator clock periods in X2 mode. For further information on X2 mode.(see the clock Section) For simplicity, the accompanying figure depicts the bus cycle waveforms in idealized form and do not provide precise timing information. CPU Clock ALE PSEN# P0 D7:0 P2 PCH PCL D7:0 PCL D7:0 PCH PCH Figure 10. External Code Fetch Waveforms Draft.A - March 30, 2001 19 Preview - Confidential T89C51AC2 7.3. FLASH Memory Architecture T89C51AC2 features two on-chip flash memories: • Flash memory FM0: containing 32 Kbytes of program memory (user space) organized into 128 byte pages, • Flash memory FM1: 2 Kbytes for boot loader and Application Programming Interfaces (API). The FM0 supports both parallel programming and Serial In-System Programming (ISP) whereas FM1 supports only parallel programming by programmers. The ISP mode is detailed in the "In-System Programming" section. All Read/Write access operations on FLASH Memory by user application are managed by a set of API described in the "In-System Programming" section. Hardware Security (1 byte) Extra Row (128 bytes) Column Latches (128 bytes) 2 Kbytes Flash memory boot space FM1 FFFFh F800h 7FFFh 32 Kbytes Flash memory user space FM0 FM1 mapped between FFFFh and F800h when bit ENBOOT is set in AUXR1 register 0000h Figure 11. Flash memory architecture 7.3.1. FM0 Memory Architecture The flash memory is made up of 4 blocks (see Figure 11): 1. The memory array (user space) 32 Kbytes 2. The Extra Row 3. The Hardware security bits 4. The column latch registers 7.3.1.1. User Space This space is composed of a 32 Kbytes FLASH memory organized in 256 pages of 128 bytes. It contains the user’s application code. 7.3.1.2. Extra Row (XRow) This row is a part of FM0 and has a size of 128 bytes. The extra row may contain information for boot loader usage. 20 Draft.A - March 30, 2001 Preview - Confidential T89C51AC2 7.3.1.3. Hardware security space The Hardware security space is a part of FM0 and has a size of 1 byte. The 4 MSB can be read/written by software, the 4 LSB can only be read by software and written by hardware in parallel mode. 7.3.1.4. Column latches The column latches, also part of FM0, have a size of full page (128 bytes). The column latches are the entrance buffers of the three previous memory locations (user array, XROW and Hardware security byte). Draft.A - March 30, 2001 21 Preview - Confidential T89C51AC2 7.4. Overview of FM0 operations The CPU interfaces to the flash memory through the FCON register and AUXR1 register. These registers are used to: • • • • Map the memory spaces in the adressable space Launch the programming of the memory spaces Get the status of the flash memory (busy/not busy) Select the flash memory FM0/FM1. 7.4.1. Mapping of the memory space By default, the user space is accessed by MOVC instruction for read only. The column latches space is made accessible by setting the FPS bit in FCON register. Writing is possible from 0000h to 7FFFh, address bits 6 to 0 are used to select an address within a page while bits 14 to 7 are used to select the programming address of the page. Setting this bit takes precedence on the EXTRAM bit in AUXR register. The other memory spaces (user, extra row, hardware security) are made accessible in the code segment by programming bits FMOD0 and FMOD1 in FCON register in accordance with Table 13. A MOVC instruction is then used for reading these spaces. Table 13. .FM0 blocks select bits FMOD1 0 0 1 1 FMOD0 0 1 0 1 FM0 Adressable space User (0000h-FFFFh) Extra Row(FF80h-FFFFh) Hardware Security (0000h) reserved 7.4.2. Launching programming FPL3:0 bits in FCON register are used to secure the launch of programming. A specific sequence must be written in these bits to unlock the write protection and to launch the programming. This sequence is 5 followed by A. Table 14 summarizes the memory spaces to program according to FMOD1:0 bits. Table 14. Programming spaces Write to FCON Operation FPL3:0 User 5 A 5 A 5 A 5 A FPS X X X X X X X X FMOD1 0 0 0 0 1 1 1 1 FMOD0 0 0 1 1 0 0 1 1 No action Write the column latches in user space No action Write the column latches in extra row space No action Write the fuse bits space No action No action Extra Row Security Space Reserved The FLASH memory enters a busy state as soon as programming is launched. In this state, the memory is no more available for fetching code. Caution: Interrupts that may occur during programming time must be disable to avoid any spurious exit of the idle mode. 22 Draft.A - March 30, 2001 Preview - Confidential T89C51AC2 7.4.3. Status of the flash memory The bit FBUSY in FCON register is used to indicate the status of programming. FBUSY is set when programming is in progress. 7.4.4. Selecting FM0/FM1 The bit ENBOOT in AUXR1 register is used to choose between FM0 and FM1 mapped up to F800h. Draft.A - March 30, 2001 23 Preview - Confidential T89C51AC2 7.4.5. Loading the Column Latches Any number of data from 1 byte to 128 bytes can be loaded in the column latches. This provides the capability to program the whole memory by byte, by page or by any number of bytes in a page. When programming is launched, an automatic erase of the locations loaded in the column latches is first performed, then programming is effectively done. Thus no page or block erase is needed and only the loaded data are programmed in the corresponding page. The following procedure is used to load the column latches and is summarized in Figure 12: • • • • • Map the column latch space by setting FPS bit. Load the DPTR with the address to load. Load Accumulator register with the data to load. Execute the MOVX @DPTR, A instruction. If needed loop the three last instructions until the page is completely loaded. Column Latches Loading Column Latches Mapping FPS= 1 Data Load DPTR= Address ACC= Data Exec: MOVX @DPTR, A Last Byte to load? Data memory Mapping FPS= 0 Figure 12. Column Latches Loading Procedure 24 Draft.A - March 30, 2001 Preview - Confidential T89C51AC2 7.4.6. Programming the FLASH Spaces User The following procedure is used to program the User space and is summarized in Figure 13: • Load data in the column latches from address 0000h to 7FFFh1. • Disable the interrupts. • Launch the programming by writing the data sequence 50h followed by A0h in FCON register. The end of the programming indicated by the FBUSY flag cleared. • Enable the interrupts. Note: 1. The last page address used when loading the column latch is the one used to select the page programming address. Extra Row The following procedure is used to program the Extra Row space and is summarized in Figure 13: • Load data in the column latches from address FF80h to FFFFh. • Disable the interrupts. • Launch the programming by writing the data sequence 52h followed by A2h in FCON register. The end of the programming indicated by the FBUSY flag cleared. • Enable the interrupts. Draft.A - March 30, 2001 25 Preview - Confidential T89C51AC2 FLASH Spaces Programming Column Latches Loading see Figure 12 Disable IT EA= 0 Launch Programming FCON= 5xh FCON= Axh FBusy Cleared? Erase Mode FCON = 00h End Programming Enable IT EA= 1 Figure 13. Flash and Extra row Programming Procedure 26 Draft.A - March 30, 2001 Preview - Confidential T89C51AC2 Hardware Security The following procedure is used to program the Hardware Security space and is summarized in Figure 14: • • • • • • Set FPS and map Harware byte (FCON = 0x0C) Disable the interrupts. Load DPTR at address 0000h. Load Accumulator register with the data to load. Execute the MOVX @DPTR, A instruction. Launch the programming by writing the data sequence 54h followed by A4h in FCON register. The end of the programming indicated by the FBusy flag cleared. • Enable the interrupts. FLASH Spaces Programming FCON = 0Ch Data Load DPTR= 00h ACC= Data Exec: MOVX @DPTR, A Disable IT EA= 0 Launch Programming FCON= 54h FCON= A4h FBusy Cleared? Erase Mode FCON = 00h End Programming Enable IT EA= 1 Figure 14. Hardware Programming Procedure Draft.A - March 30, 2001 27 Preview - Confidential T89C51AC2 7.4.7. Reading the FLASH Spaces User The following procedure is used to read the User space and is summarized in Figure 15: • Map the User space by writing 00h in FCON register. • Read one byte in Accumulator by executing MOVC A,@A+DPTR with A= 0 & DPTR= 0000h to FFFFh. Extra Row The following procedure is used to read the Extra Row space and is summarized in Figure 15: • Map the Extra Row space by writing 02h in FCON register. • Read one byte in Accumulator by executing MOVC A,@A+DPTR with A= 0 & DPTR= FF80h to FFFFh. Hardware Security The following procedure is used to read the Hardware Security space and is summarized in Figure 15: • Map the Hardware Security space by writing 04h in FCON register. • Read the byte in Accumulator by executing MOVC A,@A+DPTR with A= 0 & DPTR= 0000h. FLASH Spaces Reading FLASH Spaces Mapping FCON= 00000xx0b Data Read DPTR= Address ACC= 0 Exec: MOVC A, @A+DPTR Erase Mode FCON = 00h Figure 15. Reading Procedure 28 Draft.A - March 30, 2001 Preview - Confidential T89C51AC2 7.5. Registers FCON (S:D1h) FLASH Control Register 7 FPL3 6 FPL2 5 FPL1 4 FPL0 3 FPS 2 FMOD1 1 FMOD0 0 FBUSY Bit Number Bit Mnemonic 7-4 FPL3:0 Description Programming Launch Command Bits Write 5Xh followed by AXh to launch the programming according to FMOD1:0. (see Table 14.) FLASH Map Program Space Set to map the column latch space in the data memory space. Clear to re-map the data memory space. FLASH Mode See Table 13 or Table 14. FLASH Busy Set by hardware when programming is in progress. Clear by hardware when programming is done. Can not be cleared by software. 3 FPS 2-1 FMOD1:0 0 FBUSY Reset Value= 0000 0000b Figure 16. FCON Register Draft.A - March 30, 2001 29 Preview - Confidential T89C51AC2 8. Data Memory 8.1. Introduction The T89C51AC2 provides data memory access in two different spaces: 1. The internal space mapped in three separate segments: • the lower 128 bytes RAM segment. • the upper 128 bytes RAM segment. • the expanded 1024 bytes RAM segment (ERAM). 2. The external space. A fourth internal segment is available but dedicated to Special Function Registers, SFRs, (addresses 80h to FFh) accessible by direct addressing mode. Figure 17 shows the internal and external data memory spaces organization. FFFFh 64 Kbytes External XRAM FFh or 3FFh FFh Upper 128 bytes Internal RAM indirect addressing 80h 7Fh 80h Lower 128 bytes Internal RAM direct or indirect addressing FFh Special Function Registers direct addressing 256 up to 1024 bytes Internal ERAM EXTRAM= 0 00h 00h 0100h up to 0400h 0000h EXTRAM= 1 Figure 17. Internal and External Data Memory Organization 30 Draft.A - March 30, 2001 Preview - Confidential T89C51AC2 8.2. Internal Space 8.2.1. Lower 128 Bytes RAM The lower 128 bytes of RAM (see Figure 17) are accessible from address 00h to 7Fh using direct or indirect addressing modes. The lowest 32 bytes are grouped into 4 banks of 8 registers (R0 to R7). Two bits RS0 and RS1 in PSW register (see Figure 23) select which bank is in use according to Table 15. This allows more efficient use of code space, since register instructions are shorter than instructions that use direct addressing, and can be used for context switching in interrupt service routines. Table 15. Register Bank Selection RS1 0 0 1 1 RS0 0 1 0 1 Description Register bank 0 from 00h to 07h Register bank 0 from 08h to 0Fh Register bank 0 from 10h to 17h Register bank 0 from 18h to 1Fh The next 16 bytes above the register banks form a block of bit-addressable memory space. The C51 instruction set includes a wide selection of single-bit instructions, and the 128 bits in this area can be directly addressed by these instructions. The bit addresses in this area are 00h to 7Fh. 7Fh 30h 2Fh 20h 18h 10h 08h 00h 1Fh 17h 0Fh 07h 4 Banks of 8 Registers R0-R7 Bit-Addressable Space (Bit Addresses 0-7Fh) Figure 18. Lower 128 bytes Internal RAM Organization 8.2.2. Upper 128 Bytes RAM The upper 128 bytes of RAM are accessible from address 80h to FFh using only indirect addressing mode. 8.2.3. Expanded RAM The on-chip 1024 bytes of expanded RAM (ERAM) are accessible from address 0000h to 03FFh using indirect addressing mode through MOVX instructions. In this address range, the bit EXTRAM in AUXR register is used to select the ERAM (default) or the XRAM. As shown in Figure 17 when EXTRAM= 0, the ERAM is selected and when EXTRAM= 1, the XRAM is selected. Caution: Lower 128 bytes RAM, Upper 128 bytes RAM, and expanded RAM are made of volatile memory cells. This means that the RAM content is indeterminate after power-up and must then be initialized properly. Draft.A - March 30, 2001 31 Preview - Confidential T89C51AC2 8.3. External Space 8.3.1. Memory Interface The external memory interface comprises the external bus (port 0 and port 2) as well as the bus control signals (RD#, WR#, and ALE). Figure 19 shows the structure of the external address bus. P0 carries address A7:0 while P2 carries address A15:8. Data D7:0 is multiplexed with A7:0 on P0. Table 16 describes the external memory interface signals. = CCAPnL “1” 7 ECOMn0 00 0 0PWMn0 CCAPMn Register Figure 69. PCA PWM Mode 80 Draft.A - March 30, 2001 Preview - Confidential T89C51AC2 15.7. PCA Watchdog Timer An on-board watchdog timer is available with the PCA to improve system reliability without increasing chip count. Watchdog timers are useful for systems that are sensitive to noise, power glitches, or electrostatic discharge. Module 4 is the only PCA module that can be programmed as a watchdog. However, this module can still be used for other modes if the watchdog is not needed. The user pre-loads a 16-bit value in the compare registers. Just like the other compare modes, this 16-bit value is compared to the PCA timer value. If a match is allowed to occur, an internal reset will be generated. This will not cause the RST pin to be driven high. To hold off the reset, the user has three options: • 1. periodically change the compare value so it will never match the PCA timer, • 2. periodically change the PCA timer value so it will never match the compare values, or • 3. disable the watchdog by clearing the WDTE bit before a match occurs and then re-enable it. The first two options are more reliable because the watchdog timer is never disabled as in option #3. If the program counter ever goes astray, a match will eventually occur and cause an internal reset. If other PCA modules are being used the second option not recommended either. Remember, the PCA timer is the time base for all modules; changing the time base for other modules would not be a good idea. Thus, in most applications the first solution is the best option. Draft.A - March 30, 2001 81 Preview - Confidential T89C51AC2 15.8. PCA Registers CMOD (S:D8h) PCA Counter Mode Register 7 CIDL 6 WDTE 5 4 3 2 CPS1 Description PCA Counter Idle Control bit Clear to let the PCA run during Idle mode. Set to stop the PCA when Idle mode is invoked. Watchdog Timer Enable Clear to disable Watchdog Timer function on PCA Module 4, Set to enable it. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. EWC Count Pulse CPS1 CPS0 0 0 0 1 1 0 1 1 Select bits Clock source Internal Clock, FPca/6 Internal Clock, FPca/2 Timer 0 overflow External clock at ECI/P1.2 pin (Max. Rate = FPca/4) 1 CPS0 0 ECF Bit Number Bit Mnemonic 7 CIDL 6 WDTE 5 4 3 - 2 CPS1 1 0 CPS0 ECF Enable PCA Counter Overflow Interrupt bit Clear to disable CF bit in CCON register to generate an interrupt. Set to enable CF bit in CCON register to generate an interrupt. Reset Value = 00XX X000b Figure 70. CMOD Register 82 Draft.A - March 30, 2001 Preview - Confidential T89C51AC2 CCON (S:D8h) PCA Counter Control Register 7 CF 6 CR 5 4 CCF4 3 CCF3 2 CCF2 1 CCF1 0 CCF0 Bit Number Bit Mnemonic Description PCA Timer/Counter Overflow flag Set by hardware when the PCA Timer/Counter rolls over. This generates a PCA interrupt request if the ECF bit in CMOD register is set. Must be cleared by software. PCA Timer/Counter Run Control bit Clear to turn the PCA Timer/Counter off. Set to turn the PCA Timer/Counter on. Reserved The value read from this bit is indeterminate. Do not set this bit. PCA Module 4 Compare/Capture flag Set by hardware when a match or capture occurs. This generates a PCA interrupt request if the ECCF 4 bit in CCAPM 4 register is set. Must be cleared by software. PCA Module 3 Compare/Capture flag Set by hardware when a match or capture occurs. This generates a PCA interrupt request if the ECCF 3 bit in CCAPM 3 register is set. Must be cleared by software. PCA Module 2 Compare/Capture flag Set by hardware when a match or capture occurs. This generates a PCA interrupt request if the ECCF 2 bit in CCAPM 2 register is set. Must be cleared by software. PCA Module 1 Compare/Capture flag Set by hardware when a match or capture occurs. This generates a PCA interrupt request if the ECCF 1 bit in CCAPM 1 register is set. Must be cleared by software. PCA Module 0 Compare/Capture flag Set by hardware when a match or capture occurs. This generates a PCA interrupt request if the ECCF 0 bit in CCAPM 0 register is set. Must be cleared by software. 7 CF 6 CR 5 - 4 CCF4 3 CCF3 2 CCF2 1 CCF1 0 CCF0 Reset Value = 00X0 0000b Figure 71. CCON Register Draft.A - March 30, 2001 83 Preview - Confidential T89C51AC2 CCAP0H (S:FAh) CCAP1H (S:FBh ) CCAP2H (S:FCh) CCAP3H (S:FDh) CCAP4H (S:FEh) PCA High Byte Compare/Capture Module n Register (n=0..4) 7 CCAPnH 7 6 CCAPnH 6 5 CCAPnH 5 4 CCAPnH 4 3 CCAPnH 3 2 CCAPnH 2 1 CCAPnH 1 0 CCAPnH 0 Bit Number Bit Mnemonic 7:0 CCAPnH 7:0 Description High byte of EWC-PCA comparison or capture values Reset Value = 0000 0000b Figure 72. CCAPnH Registers CCAP0L (S: EAh) CCAP1L (S:EBh ) CCAP2L (S:ECh) CCAP3L (S:EDh) CCAP4L (S:EEh) PCA Low Byte Compare/Capture Module n Register (n=0..4) 7 CCAPnL 7 6 CCAPnL 6 5 CCAPnL 5 4 CCAPnL 4 3 CCAPnL 3 2 CCAPnL 2 1 CCAPnL 1 0 CCAPnL 0 Bit Number Bit Mnemonic 7:0 CCAPnL 7:0 Description Low byte of EWC-PCA comparison or capture values Reset Value = 0000 0000b Figure 73. CCAPnL Registers 84 Draft.A - March 30, 2001 Preview - Confidential T89C51AC2 CCAPM0 (S:DAh) CCAPM1 (S:DBh) CCAPM2 (S:DCh) CCAPM3 (S:DDh) CCAPM4 (S:DEh) PCA Compare/Capture Module n Mode registers (n=0..4) 7 6 ECOMn 5 CAPPn 4 CAPNn 3 MATn 2 TOGn 1 PWMn 0 ECCFn Bit Number Bit Mnemonic 7 - Description Reserved The Value read from this bit is indeterminate. Do not set this bit. Enable Compare Mode Module x bit Clear to disable the Compare function. Set to enable the Compare function. The Compare function is used to implement the software Timer, the high-speed output, the Pulse Width Modulator (PWM) and the Watchdog Timer (WDT). Capture Mode (Positive) Module x bit Clear to disable the Capture function triggered by a positive edge on CEXx pin. Set to enable the Capture function triggered by a positive edge on CEXx pin Capture Mode (Negative) Module x bit Clear to disable the Capture function triggered by a negative edge on CEXx pin. Set to enable the Capture function triggered by a negative edge on CEXx pin. Match Module x bit Set when a match of the PCA Counter with the Compare/Capture register sets CCFx bit in CCON register, flagging an interrupt. Must be cleared by software. Toggle Module x bit The toggle mode is configured by setting ECOMx, MATx and TOGx bits. Set when a match of the PCA Counter with the Compare/Capture register toggles the CEXx pin. Must be cleared by software. Pulse Width Modulation Module x Mode bit Set to configure the module x as an 8-bit Pulse Width Modulator with output waveform on CEXx pin. Must be cleared by software. Enable CCFx Interrupt bit Clear to disable CCFx bit in CCON register to generate an interrupt request. Set to enable CCFx bit in CCON register to generate an interrupt request. 6 ECOMn 5 CAPPn 4 CAPNn 3 MATn 2 TOGn 1 PWMn 0 ECCFn Reset Value = X000 0000b Figure 74. CCAPMn Registers Draft.A - March 30, 2001 85 Preview - Confidential T89C51AC2 CH (S:F9h) PCA Counter Register High value 7 CH 7 6 CH 6 5 CH 5 4 CH 4 3 CH 3 2 CH 2 1 CH 1 0 CH 0 Bit Number Bit Mnemonic 7:0 CH 7:0 High byte of Timer/Counter Description Reset Value = 0000 00000b Figure 75. CH Register CL (S:E9h) PCA counter Register Low value 7 CL 7 6 CL 6 5 CL 5 4 CL 4 3 CL 3 2 CL 2 1 CL 1 0 CL 0 Bit Number Bit Mnemonic 7:0 CL0 7:0 Low byte of Timer/Counter Description Reset Value = 0000 00000b Figure 76. CL Register 86 Draft.A - March 30, 2001 Preview - Confidential T89C51AC2 16. Analog-to-Digital Converter (ADC) 16.1. Introduction This section describes the on-chip 10 bit analog-to-digital converter of the T89C51AC2. Eight ADC channels are available for sampling of the external sources AN0 to AN7. An analog multiplexer allows the single ADC converter to select one from the 8 ADC channels as ADC input voltage (ADCIN). ADCIN is converted by the 10 bitcascaded potentiometric ADC. Two kind of conversion are available: - Standard conversion (8 bits). - Precision conversion (10 bits). For the precision conversion, set bit PSIDLE in ADCON register and start conversion. The chip is in a pseudoidle mode, the CPU doesn’t run but the peripherals are always running. This mode allows digital noise to be as low as possible, to ensure high precision conversion. For this mode it is necessary to work with end of conversion interrupt, which is the only way to wake up the chip. If another interrupt occurs during the precision conversion, it will be treated only after this conversion is ended. 16.2. Features • 8 channels with multiplexed inputs • 10-bit cascaded potentiometric ADC • Conversion time 20 micro-seconds • Zero Error (offset) +/- 2 LSB max • Positive Reference Voltage Range 2.4 to 3.0Volt • ADCIN Range 0 to 3Volt • Integral non-linearity typical 1 LSB, max. 2 LSB • Differential non-linearity typical 0.5 LSB, max. 1 LSB • Conversion Complete Flag or Conversion Complete Interrupt • Selected ADC Clock 16.3. ADC Port1 I/O Functions Port 1 pins are general I/O that are shared with the ADC channels. The channel select bit in ADCF register define which ADC channel/port1 pin will be used as ADCIN. The remaining ADC channels/port1 pins can be used as general purpose I/O or as the alternate function that is available. Writes to the port register which aren’t selected by the ADCF will not have any effect. Draft.A - March 30, 2001 87 Preview - Confidential T89C51AC2 ADCON.5 ADCON.3 ADEN ADSST ADCON.4 ADC CLOCK ADEOC CONTROL ADC Interrupt Request EADC IEN1.1 AN0/P1.0 AN1/P1.1 AN2/P1.2 AN3/P1.3 AN4/P1.4 AN5/P1.5 AN6/P1.6 AN7/P1.7 000 001 010 011 100 101 110 111 AVSS ADCIN 8 + SAR 2 ADDH ADDL Sample and Hold R/2R DAC 10 SCH2 ADCON.2 SCH1 ADCON.1 SCH0 ADCON.0 VAREF VAGND Figure 77. ADC Description Figure 78 shows the timing diagram of a complete conversion. For simplicity, the figure depicts the waveforms in idealized form and do not provide precise timing information. For ADC characteristics and timing parameters refer to the Section “AC Characteristics” of the T89C51AC2 datasheet. CLK ADEN TSETUP ADSST TCONV ADEOC Figure 78. Timing Diagram NOTE: Tsetup = 4 us Tconv=11 clock ADC 88 Draft.A - March 30, 2001 Preview - Confidential T89C51AC2 16.4. ADC Converter Operation A start of single A/D conversion is triggered by setting bit ADSST (ADCON.3). The busy flag ADSST(ADCON.3) is automatically set when an A/D conversion is running. After completion of the A/D conversion, it is cleared by hardware. This flag can be read only, a write has no effect. The end-of-conversion flag ADEOC (ADCON.4) is set when the value of conversion is available in ADDH and ADDL, it is cleared by software. If the bit EADC (IEN1.1) is set, an interrupt occur when flag ADEOC is set (see Figure 80). Clear this flag for re-arming the interrupt. The bits SCH0 to SCH2 in ADCON register are used for the analog input channel selection. Before Starting Power reduction modes the ADC conversion has to be completed. Table 21. Selected Analog input SCH2 0 0 0 0 1 1 1 1 SCH1 0 0 1 1 0 0 1 1 SCH0 0 1 0 1 0 1 0 1 Selected Analog input AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 16.5. Voltage Conversion When the ADCIN is equals to VAREF the ADC converts the signal to 3FFh (full scale). If the input voltage equals VAGND, the ADC converts it to 000h. Input voltage between VAREF and VAGND are a straight-line linear conversion. All other voltages will result in 3FFh if greater than VAREF and 000h if less than VAGND. Note that ADCIN should not exceed VAREF absolute maximum range! Draft.A - March 30, 2001 89 Preview - Confidential T89C51AC2 16.6. Clock Selection The maximum clock frequency for ADC is 700KHz. A prescaler is featured (ADCCLK) to generate the ADC clock from the oscillator frequency. conversion clock fADC CPU CLOCK ÷2 Prescaler ADCLK A/D Converter CPU Core Clock Symbol Figure 79. A/D Converter clock 16.7. ADC Standby Mode When the ADC is not used, it is possible to set it in standby mode by clearing bit ADEN in ADCON register. In this mode the power dissipation is about 1uW. 90 Draft.A - March 30, 2001 Preview - Confidential T89C51AC2 16.8. IT ADC management An interrupt end-of-conversion will occurs when the bit ADEOC is actived and the bit EADC is set. For re-arming the interrupt the bit ADEOC must be cleared by software. ADEOC ADCON.2 ADCI EADC IEN1.1 Figure 80. ADC interrupt structure Draft.A - March 30, 2001 91 Preview - Confidential T89C51AC2 16.9. Registers ADCF (S:F6h) ADC Configuration 7 CH 7 Bit Number 6 CH 6 Bit Mnemonic CH 0:7 Channel Configuration Set to use P1.x as ADC input. Clear tu use P1.x as standart I/O port. 5 CH 5 4 CH 4 3 CH 3 2 CH 2 1 CH 1 0 CH 0 Description 7-0 Reset Value=0000 0000b Figure 81. ADCF Register ADCON (S:F3h) ADC Control Register 7 6 PSIDLE 5 ADEN 4 ADEOC 3 ADSST 2 SCH2 1 SCH1 0 SCH0 Bit Number Bit Mnemonic 7 6 PSIDLE Description Pseudo Idle mode (best precision) Set to put in idle mode during conversion Clear to converte without idle mode. Enable/Standby Mode Set to enable ADC Clear for Standby mode (power dissipation 1 uW). End Of Conversion Set by hardware when ADC result is ready to be read. This flag can generate an interrupt. Must be cleared by software. Start and Status Set to start an A/D conversion. Cleared by hardware after completion of the conversion Selection of channel to convert see Table 21 5 ADEN 4 ADEOC 3 ADSST 2-0 SCH2:0 Reset Value=X000 0000b Figure 82. ADCON Register 92 Draft.A - March 30, 2001 Preview - Confidential T89C51AC2 ADCLK (S:F2h) ADC Clock Prescaler 7 6 5 4 PRS 4 3 PRS 3 2 PRS 2 1 PRS 1 0 PRS 0 Bit Number Bit Mnemonic 7-5 4-0 PRS4:0 Description Reserved The value read from these bits are indeterminate. Do not set these bits. Clock Prescaler fADC = fosc / (4 (or 2 in X2 mode)* PRS) Reset Value: XXX0 0000b Figure 83. ADCLK Register ADDH (S:F5h Read Only) ADC Data High byte register 7 ADAT 9 6 ADAT 8 5 ADAT 7 4 ADAT 6 3 ADAT 5 2 ADAT 4 1 ADAT 3 0 ADAT 2 Bit Number Bit Mnemonic 7-0 ADAT9:2 ADC result bits 9-2 Description Reset Value: 00h Figure 84. ADDH Register ADDL (S:F4h Read Only) ADC Data Low byte register 7 6 5 4 3 Description Reserved The value read from these bits are indeterminate. Do not set these bits. ADC result bits 1-0 2 - 1 ADAT 1 0 ADAT 0 Bit Number Bit Mnemonic 7-2 1-0 ADAT1:0 Reset Value: 00h Figure 85. ADDL Register Draft.A - March 30, 2001 93 Preview - Confidential T89C51AC2 17. Interrupt System 17.1. Introduction The CAN Controller has a total of 8 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (timers 0, 1 and 2), a serial port interrupt, a PCA and an ADC. These interrupts are shown below. Highest Priority Interrupts INT0# External Interrupt 0 EX0 IEN0.0 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 Timer 0 ET0 IEN0.1 INT1# External Interrupt 1 EX1 IEN0.2 Timer 1 ET1 CEX0:5 IEN0.3 PCA EC TxD RxD IEN0.6 UART ES IEN0.4 Timer 2 ET2 IEN0.5 00 01 10 11 AIN1:0 A to D Converter EADC IEN1.1 00 01 10 11 EA IEN0.7 IPH/L Priority Enable Lowest Priority Interrupts Interrupt Enable Figure 86. Interrupt Control System 94 Draft.A - March 30, 2001 Preview - Confidential T89C51AC2 Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the Interrupt Enable register. This register also contains a global disable bit which must be cleared to disable all the interrupts at the same time. Each interrupt source can also be individually programmed to one of four priority levels by setting or clearing a bit in the Interrupt Priority registers. The Table below shows the bit values and priority levels associated with each combination. Table 22. Priority Level Bit Values IPH.x 0 0 1 1 IPL.x 0 1 0 1 Interrupt Level Priority 0 (Lowest) 1 2 3 (Highest) A low-priority interrupt can be interrupted by a high priority interrupt but not by another low-priority interrupt. A high-priority interrupt cannot be interrupted by any other interrupt source. If two interrupt requests of different priority levels are received simultaneously, the request of the higher priority level is serviced. If interrupt requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. Thus within each priority level there is a second priority structure determined by the polling sequence, see Table 23. Table 23. Interrupt priority Within level Interrupt Name external interrupt (INT0) Timer0 (TF0) external interrupt (INT1) Timer1 (TF1) PCA (CF or CCFn) UART (RI or TI) Timer2 (TF2) ADC (ADCI) Interrupt Address Vector 0003h 000Bh 0013h 001Bh 0033h 0023h 002Bh 0043h Priority Number 1 2 3 4 5 6 7 8 Draft.A - March 30, 2001 95 Preview - Confidential T89C51AC2 17.2. Registers IEN0 (S:A8h) Interrupt Enable Register 7 EA 6 EC 5 ET2 4 ES 3 ET1 2 EX1 1 ET0 0 EX0 Bit Number Bit Mnemonic Description Enable All interrupt bit Clear to disable all interrupts. Set to enable all interrupts. If EA=1, each interrupt source is individually enabled or disabled by setting or clearing its interrupt enable bit. PCA Interrupt Enable Clear to disable the PCA interrupt. Set to enable the PCA interrupt. Timer 2 overflow interrupt Enable bit Clear to disable timer 2 overflow interrupt. Set to enable timer 2 overflow interrupt. Serial port Enable bit Clear to disable serial port interrupt. Set to enable serial port interrupt. Timer 1 overflow interrupt Enable bit Clear to disable timer 1 overflow interrupt. Set to enable timer 1 overflow interrupt. External interrupt 1 Enable bit Clear to disable external interrupt 1. Set to enable external interrupt 1. Timer 0 overflow interrupt Enable bit Clear to disable timer 0 overflow interrupt. Set to enable timer 0 overflow interrupt. External interrupt 0 Enable bit Clear to disable external interrupt 0. Set to enable external interrupt 0. 7 EA 6 EC 5 ET2 4 ES 3 ET1 2 EX1 1 ET0 0 EX0 Reset Value: 0000 0000b bit addressable Figure 87. IEN0 Register 96 Draft.A - March 30, 2001 Preview - Confidential T89C51AC2 IEN1 (S:E8h) Interrupt Enable Register 7 6 5 4 Description Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. ADC Interrupt Enable bit Clear to disable the ADC interrupt. Set to enable the ADC interrupt. Reserved The value read from this bit is indeterminate. Do not set this bit. 3 2 - 1 EADC 0 - Bit Number Bit Mnemonic 7 6 5 4 3 2 - 1 EADC 0 - Reset Value: xxxx xx0xb bit addressable Figure 88. IEN1 Register Draft.A - March 30, 2001 97 Preview - Confidential T89C51AC2 IPL0 (S:B8h) Interrupt Enable Register 7 6 PPC 5 PT2 4 PS 3 PT1 2 PX1 1 PT0 0 PX0 Bit Number Bit Mnemonic 7 6 5 4 3 2 1 0 PPC PT2 PS PT1 PX1 PT0 PX0 Description Reserved The value read from this bit is indeterminate. Do not set this bit. EWC Counter Interrupt Priority bit Refer to PPCH for priority level Timer 2 overflow interrupt Priority bit Refer to PT2H for priority level. Serial port Priority bit Refer to PSH for priority level. Timer 1 overflow interrupt Priority bit Refer to PT1H for priority level. External interrupt 1 Priority bit Refer to PX1H for priority level. Timer 0 overflow interrupt Priority bit Refer to PT0H for priority level. External interrupt 0 Priority bit Refer to PX0H for priority level. Reset Value: x000 0000b bit addressable Figure 89. IPL0 Register 98 Draft.A - March 30, 2001 Preview - Confidential T89C51AC2 IPL1 (S:F8h) Interrupt Priority Low Register 1 7 6 5 4 3 Description Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. ADC Interrupt Priority level less significant bit. Refer to PSPIH for priority level. Reserved The value read from this bit is indeterminate. Do not set this bit. 2 - 1 PADCL 0 - Bit Number Bit Mnemonic 7 6 5 4 3 2 1 0 PADCL - Reset Value: xxxx xx0xb bit addressable Figure 90. IPL1 Register Draft.A - March 30, 2001 99 Preview - Confidential T89C51AC2 IPH0 (B7h) Interrupt High Priority Register 7 6 PPCH 5 PT2H 4 PSH 3 PT1H 2 PX1H 1 PT0H 0 PX0H Bit Number Bit Mnemonic 7 - Description Reserved The value read from this bit is indeterminate. Do not set this bit. EWC-PCA Counter Interrupt Priority level most significant bit PPCH PPC Priority level 0 0 Lowest 0 1 1 0 1 1 Highest priority Timer 2 overflow interrupt High Priority bit PT2H PT2 Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest Serial port High Priority bit PSH PS Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest Timer 1 overflow interrupt High Priority bit PT1H PT1 Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest External interrupt 1 PX1H 0 0 1 1 High Priority bit PX1 Priority Level 0 Lowest 1 0 1 Highest 6 PPCH 5 PT2H 4 PSH 3 PT1H 2 PX1H 1 PT0H Timer 0 overflow interrupt High Priority bit PT0H PT0 Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest External interrupt 0 PX0H 0 0 1 1 high priority bit PX0 Priority Level 0 Lowest 1 0 1 Highest 0 PX0H Reset Value: X000 0000b Figure 91. IPL0 Register 100 Draft.A - March 30, 2001 Preview - Confidential T89C51AC2 IPH1 (S:FFh) Interrupt high priority Register 1 7 6 5 4 3 Description Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. ADC Interrupt Priority level most significant bit PADCH PADCL Priority level 0 0 Lowest 0 1 1 0 1 1 Highest Reserved The value read from this bit is indeterminate. Do not set this bit. 2 - 1 PADCH 0 - Bit Number Bit Mnemonic 7 6 5 4 3 2 - 1 PADCH 0 - Reset Value = xxxx xx0xb Figure 92. IPH1 Register Draft.A - March 30, 2001 101 Preview - Confidential T89C51AC2 18. Electrical Characteristics 18.1. Absolute Maximum Ratings (1) Ambiant Temperature Under Bias: I = industrial -40°C to 85°C Storage Temperature -65°C to + 150°C Voltage on VCC to VSS-0.5 V to + 6V Voltage on Any Pin to VSS-0.5 V to VCC + 0.2 V Power Dissipation 1 W(2) NOTES 1. Stresses at or above those listed under “ Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. 2. This value is based on the maximum allowable die temperature and the thermal resistance of the package. 102 Draft.A - March 30, 2001 Preview - Confidential T89C51AC2 18.2. DC Parameters for Standard Voltage TA = -40°C to +85°C; VSS = 0 V; VCC = 5 V ± 10%; F = 0 to 40 MHz. Symbol VIL VIH VIH1 VOL Parameter Input Low Voltage Input High Voltage except XTAL1, RST Input High Voltage, XTAL1, RST Output Low Voltage, ports 1, 2, 3 and 4(6) Min -0.5 0.2 VCC + 0.9 0.7 VCC Typ Max 0.7(7) VCC + 0.5 VCC + 0.5 0.3 0.45 1.0 Unit V V V V V V Test Conditions IOL = 100 µA(4) IOL = 1.6 mA(4) IOL = 3.5 mA(4) IOL = 200 µA(4) IOL = 3.2 mA(4) IOL = 7.0 mA(4) IOH = -10 µA IOH = -30 µA IOH = -60 µA VCC = 5 V ± 10% VOL1 Output Low Voltage, port 0, ALE, PSEN (6) 0.3 0.45 1.0 V V V VOH Output High Voltage, ports 1, 2, 3, 4 and 5 VCC - 0.3 VCC - 0.7 VCC - 1.5 V V V VOH1 Output High Voltage, port 0, ALE, PSEN VCC - 0.3 VCC - 0.7 VCC - 1.5 V V V IOH = -200 µA IOH = -3.2 mA IOH = -7.0 mA VCC = 5 V ± 10% RRST IIL ILI ITL CIO IPD ICC RST Pulldown Resistor Logical 0 Input Current ports 1, 2, 3 and 4 Input Leakage Current Logical 1 to 0 Transition Current, ports 1, 2, 3 and 4 Capacitance of I/O Buffer 20 40 (5) 200 -50 ±10 -650 kΩ µA µA µA pF µA Vin = 0.45 V 0.45 V < Vin < VCC Vin = 2.0 V 10 Fc = 1 MHz TA = 25°C 4.5 V < VCC < 5.5 V(3) Power Down Current Power Supply Current (Typical) ICCOP = 0.5 Freq (MHz) + 3 mA ICCIDLE = 0.3 Freq (MHz) + 2 mA 120 350 Table 24. DC Parameters in Standard Voltage NOTES 1. Operating ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns (see Figure 96.), VIL = VSS + 0.5 V, VIH = VCC - 0.5V; XTAL2 N.C.; EA = RST = Port 0 = VCC. ICC would be slightly higher if a crystal oscillator used (see Figure 93.). 2. Idle ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VCC - 0.5 V; XTAL2 N.C; Port 0 = VCC; EA = RST = VSS (see Figure 94.). 3. Power Down ICC is measured with all output pins disconnected; EA = VSS, PORT 0 = VCC; XTAL2 NC.; RST = VSS (see Figure 95.). In addition, the WDT must be inactive and the POF flag must be set. Draft.A - March 30, 2001 103 Preview - Confidential T89C51AC2 4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLs of ALE and Ports 1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0 transitions during bus operation. In the worst cases (capacitive loading 100pF), the noise pulse on the ALE line may exceed 0.45V with maxi VOL peak 0.6V. A Schmitt Trigger use is not necessary. 5. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature.. 6. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 10 mA Maximum IOL per 8-bit port: Port 0: 26 mA Ports 1, 2 and 3: 15 mA Maximum total IOL for all output pins: 71 mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 7. Lower than standart C51 product independant from Vcc supply. VCC ICC VCC VCC RST (NC) CLOCK SIGNAL XTAL2 XTAL1 VSS All other pins are disconnected. P0 EA VCC Figure 93. ICC Test Condition, Active Mode VCC ICC VCC P0 RST (NC) CLOCK SIGNAL XTAL2 XTAL1 VSS All other pins are disconnected. EA VCC Figure 94. ICC Test Condition, Idle Mode 104 Draft.A - March 30, 2001 Preview - Confidential T89C51AC2 VCC ICC VCC P0 RST (NC) XTAL2 XTAL1 VSS All other pins are disconnected. EA VCC Figure 95. ICC Test Condition, Power-Down Mode VCC-0.5V 0.45V TCLCH TCHCL TCLCH = TCHCL = 5ns. 0.7VCC 0.2VCC-0.1 Figure 96. Clock Signal Waveform for ICC Tests in Active and Idle Modes 18.3. DC Parameters for A/D Converter Table 25. DC Parameters for AD Converter Symbol AVin Rref Vref Cai INL DNL OE Parameter Analog input voltage Resistance between Vref and Vss Reference voltage Analog input Capacitance Integral non linearity Differential non linearity Offset error Min Vss- 0.2 12 2.40 Typ 18 60 1 0.5 Max Vref + 0.2 24 3.00 2 1 2 Unit V Test Conditions -2 KOhm V pF During sampling lsb lsb lsb Draft.A - March 30, 2001 105 Preview - Confidential T89C51AC2 18.4. AC Parameters 18.4.1. Explanation of the AC Symbols Each timing symbol has 5 characters. The first character is always a “T” (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for. Example:TAVLL = Time for Address Valid to ALE Low. TLLPL = Time for ALE Low to PSEN Low. TA = -40°C to +85°C; VSS = 0 V; VCC = 5 V ±10% ; F = 0 to 40 MHz. TA = -40°C to +85°C; VSS = 0 V; VCC = 5 V ± 10%. (Load Capacitance for port 0, ALE and PSEN = 60 pF; Load Capacitance for all other outputs = 60 pF.) Table 26, Table 29 and Table 32 give the description of each AC symbols. Table 27, Table 30 and Table 33 give for each range the AC parameter. Table 28, Table 31 and Table 34 give the frequency derating formula of the AC parameter for each speed range description. To calculate each AC symbols. take the x value and use this value in the formula. Example: TLLIV and 20 MHz, Standard clock. x = 30 ns T = 50 ns TCCIV = 4T - x = 170 ns 106 Draft.A - March 30, 2001 Preview - Confidential T89C51AC2 18.4.2. External Program Memory Characteristics Table 26. Symbol Description Symbol T TLHLL TAVLL TLLAX TLLIV TLLPL TPLPH TPLIV TPXIX TPXIZ TAVIV TPLAZ Oscillator clock period ALE pulse width Address Valid to ALE Address Hold After ALE ALE to Valid Instruction In ALE to PSEN PSEN Pulse Width PSEN to Valid Instruction In Input Instruction Hold After PSEN Input Instruction FloatAfter PSEN Address to Valid Instruction In PSEN Low to Address Float Parameter Table 27. AC Parameters for a Fix Clock (F= 40 MHz) Symbol Min T TLHLL TAVLL TLLAX TLLIV TLLPL TPLPH TPLIV TPXIX TPXIZ TAVIV TPLAZ 0 18 85 10 15 55 35 25 40 10 10 70 Units Max ns ns ns ns ns ns ns ns ns ns ns ns Draft.A - March 30, 2001 107 Preview - Confidential T89C51AC2 Table 28. AC Parameters for a Variable Clock Symbol TLHLL TAVLL TLLAX TLLIV TLLPL TPLPH TPLIV TPXIX TPXIZ TAVIV TPLAZ Type Min Min Min Max Min Min Max Min Max Max Max Standard Clock 2T-x T-x T-x 4T-x T-x 3T-x 3T-x x T-x 5T-x x X2 Clock T-x 0.5 T - x 0.5 T - x 2T-x 0.5 T - x 1.5 T - x 1.5 T - x x 0.5 T - x 2.5 T - x x X parameter 10 15 15 30 10 20 40 0 7 40 10 Units ns ns ns ns ns ns ns ns ns ns ns 18.4.3. External Program Memory Read Cycle 12 TCLCL TLHLL ALE TLLIV TLLPL TPLPH PSEN TLLAX TAVLL PORT 0 INSTR IN A0-A7 TAVIV PORT 2 ADDRESS OR SFR-P2 ADDRESS A8-A15 ADDRESS A8-A15 TPLIV TPLAZ TPXIX INSTR IN A0-A7 INSTR IN TPXAV TPXIZ 108 Draft.A - March 30, 2001 Preview - Confidential T89C51AC2 18.4.4. External Data Memory Characteristics Table 29. Symbol Description Symbol TRLRH TWLWH TRLDV TRHDX TRHDZ TLLDV TAVDV TLLWL TAVWL TQVWX TQVWH TWHQX TRLAZ TWHLH RD Pulse Width WR Pulse Width RD to Valid Data In Data Hold After RD Data Float After RD ALE to Valid Data In Address to Valid Data In ALE to WR or RD Address to WR or RD Data Valid to WR Transition Data set-up to WR High Data Hold After WR RD Low to Address Float RD or WR High to ALE high Parameter Draft.A - March 30, 2001 109 Preview - Confidential T89C51AC2 Table 30. AC Parameters for a Fix Clock (F= 40 MHz) Symbol Min TRLRH TWLWH TRLDV TRHDX TRHDZ TLLDV TAVDV TLLWL TAVWL TQVWX TQVWH TWHQX TRLAZ TWHLH 10 50 75 10 160 15 0 40 0 30 160 165 100 130 130 100 Units Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns 110 Draft.A - March 30, 2001 Preview - Confidential T89C51AC2 Table 31. AC Parameters for a Variable Clock Symbol TRLRH TWLWH TRLDV TRHDX TRHDZ TLLDV TAVDV TLLWL TLLWL TAVWL TQVWX TQVWH TWHQX TRLAZ TWHLH TWHLH Type Min Min Max Min Max Max Max Min Max Min Min Min Min Max Min Max Standard Clock 6T-x 6T-x 5T-x x 2T-x 8T-x 9T-x 3T-x 3T+x 4T-x T-x 7T-x T-x x T-x T+x X2 Clock 3T-x 3T-x 2.5 T - x x T-x 4T -x 4.5 T - x 1.5 T - x 1.5 T + x 2T-x 0.5 T - x 3.5 T - x 0.5 T - x x 0.5 T - x 0.5 T + x X parameter 20 20 25 0 20 40 60 25 25 25 15 15 10 0 15 15 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 18.4.5. External Data Memory Write Cycle ALE TWHLH PSEN TLLWL TWLWH WR TLLAX PORT 0 A0-A7 TAVWL PORT 2 ADDRESS OR SFR-P2 ADDRESS A8-A15 OR SFR P2 TQVWX TQVWH DATA OUT TWHQX Draft.A - March 30, 2001 111 Preview - Confidential T89C51AC2 18.4.6. External Data Memory Read Cycle TWHLH ALE TLLDV PSEN TLLWL TRLRH TRHDZ TRHDX DATA IN TRLAZ ADDRESS A8-A15 OR SFR P2 RD TAVDV TLLAX PORT 0 A0-A7 TAVWL PORT 2 ADDRESS OR SFR-P2 18.4.7. Serial Port Timing - Shift Register Mode Table 32. Symbol Description (F= 40 MHz) Symbol TXLXL TQVHX TXHQX Serial port clock cycle time Output data set-up to clock rising edge Parameter Output data hold after clock rising edge Input data hold after clock rising edge Clock rising edge to input data valid TXHDX TXHDV Table 33. AC Parameters for a Fix Clock (F= 40 MHz) Symbol Min TXLXL TQVHX TXHQX TXHDX TXHDV 300 200 30 0 117 Units Max ns ns ns ns ns 112 Draft.A - March 30, 2001 Preview - Confidential T89C51AC2 Table 34. AC Parameters for a Variable Clock Symbol TXLXL TQVHX TXHQX TXHDX TXHDV Type Min Min Min Min Max Standard Clock 12 T 10 T - x 2T-x x 10 T - x X2 Clock 6T 5T-x T-x x 5 T- x X parameter for -M range Units ns 50 20 0 133 ns ns ns ns 18.4.8. Shift Register Timing Waveforms INSTRUCTION ALE 0 1 2 3 4 5 6 7 8 TXLXL CLOCK TQVXH OUTPUT DATA WRITE to SBUF INPUT DATA CLEAR RI 0 TXHDV VALID VALID TXHQX 1 2 TXHDX VALID VALID VALID VALID VALID 3 4 5 6 7 SET TI VALID SET RI 18.4.9. External Clock Drive Characteristics (XTAL1) Symbol TCLCL TCHCX TCLCX TCLCH TCHCL TCHCX/TCLCX Oscillator Period High Time Low Time Rise Time Fall Time Parameter Min 25 5 5 Max Units ns ns ns 5 5 40 60 ns ns % Cyclic ratio in X2 mode Table 35. AC Parameters Draft.A - March 30, 2001 113 Preview - Confidential T89C51AC2 18.4.10. External Clock Drive Waveforms VCC-0.5V 0.45V 0.7VCC 0.2VCC-0.1 TCHCL TCLCX TCLCL TCHCX TCLCH 18.4.11. AC Testing Input/Output Waveforms VCC -0.5 V INPUT/OUTPUT 0.45 V 0.2 VCC + 0.9 0.2 VCC - 0.1 AC inputs during testing are driven at VCC - 0.5 for a logic “1” and 0.45V for a logic “0”. Timing measurement are made at VIH min for a logic “1” and VIL max for a logic “0”. 18.4.12. Float Waveforms FLOAT VOH - 0.1 V VOL + 0.1 V VLOAD VLOAD + 0.1 V VLOAD - 0.1 V For timing purposes as port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded VOH/VOL level occurs. IOL/IOH ≥ ± 20mA. 18.4.13. Clock Waveforms Valid in normal clock mode. In X2 mode XTAL2 must be changed to XTAL2/2. 114 Draft.A - March 30, 2001 Preview - Confidential T89C51AC2 INTERNAL CLOCK XTAL2 ALE EXTERNAL PROGRAM MEMORY FETCH PSEN P0 DATA SAMPLED FLOAT PCL OUT DATA SAMPLED FLOAT PCL OUT DATA SAMPLED FLOAT PCL OUT THESE SIGNALS ARE NOT ACTIVATED DURING THE EXECUTION OF A MOVX INSTRUCTION STATE4 P1 P2 STATE5 P1 P2 STATE6 P1 P2 STATE1 P1 P2 STATE2 P1 P2 STATE3 P1 P2 STATE4 P1 P2 STATE5 P1 P2 P2 (EXT) READ CYCLE RD INDICATES ADDRESS TRANSITIONS PCL OUT (IF PROGRAM MEMORY IS EXTERNAL) P0 DPL OR Rt OUT DATA SAMPLED FLOAT P2 WRITE CYCLE INDICATES DPH OR P2 SFR TO PCH TRANSITION WR P0 DPL OR Rt OUT DATA OUT P2 PORT OPERATION MOV PORT SRC MOV DEST P0 MOV DEST PORT (P1. P2. P3) (INCLUDES INTO. INT1. TO T1) SERIAL PORT SHIFT CLOCK TXD (MODE 0) P1, P2, P3 PINS SAMPLED OLD DATA NEW DATA P0 PINS SAMPLED INDICATES DPH OR P2 SFR TO PCH TRANSITION PCL OUT (EVEN IF PROGRAM MEMORY IS INTERNAL) PCL OUT (IF PROGRAM MEMORY IS EXTERNAL) P0 PINS SAMPLED P1, P2, P3 PINS SAMPLED RXD SAMPLED RXD SAMPLED This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins, however, ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin loading. Propagation also varies from output to output and component. Typically though (TA=25°C fully loaded) RD and WR propagation delays are approximately 50ns. The other signals are typically 85 ns. Propagation delays are incorporated in the AC specifications. Draft.A - March 30, 2001 115 Preview - Confidential T89C51AC2 19. Ordering Information T 89C51AC2 -RL S C M Packages: RL: TQFP44 SL: PLCC44 Temperature Range C:Commercial 0 to 70oC I:Industrial -40 to 85oC E:Enginering Sample 89C51AC2 ( 32 Kbytes Flash ) -M: VCC: 5V 40 MHz, X1 mode 20 MHz, X2 mode Conditioning S: Stick T: Tray 116 Draft.A - March 30, 2001 Preview - Confidential T89C51AC2 Table 36. Possible order entries Extension -SLSCM -SLSIM -RLTCM -RLTIM -SLSEM -RLTEM Stick, PLCC44, Com Stick, PLCC44, Ind Tray, TQFP44, Com Tray, TQFP44, Ind Stick, PLCC44, Sample Tray, TQFP44, Sample Type Draft.A - March 30, 2001 117 Preview - Confidential