U2739M-BFC

U2739M-B DAB One-Chip Channel- and Source Decoder Description The U2739M-B is an integrated circuit in advanced CMOS technology for demodulation and decoding of a DAB signal according to ETS 300 401. The channel decoder part includes the main features OFDM demodulation & decoding and time & frequency synchronization algorithms, using the embedded OAK DSP core. The source decoder consists of an audio and a data decoder part. The audio source decoder supports ISO MPEG 1,2 layer 2 and the data decoder offers 2 independent packet mode decoders. Several standard interfaces, like I2C/L3, I2S, SPDIF or RDI are implemented to offer a flexible utilization. Moreover the U2739M-B includes a mechanism to replace respectively extend certain software modules by using a special boot mode (so-called USE). For example, the time & frequency synchronization modules can be replaced by down-loading the corresponding user software algorithms to the OAK DSP core. Electrostatic sensitive device. Observe precautions for handling. Block Diagram RAM SLI, WAGC Channel decoder U2739M–A I2S DAC Tuner ADC Audio decoder SPDIF ROM Data decoder V24/RS232 HSSO MC interface RDI interface MCU SFCO RDI Figure 1. Block diagram Ordering Information Extended Type Number U2739M-BFT U2739M-BFC CQFP144 Package T–PQFP–G100 Tray Tray Remarks Rev. A1, 22-May-01 1 (69) U2739M-B Table of Contents 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Channel Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Audio Source Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Data Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Strap Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 ADC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.1 ADC Interface Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.2 ADC Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.3 ADC Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.4 ADC Interface Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 Tuner Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.1 Tuner Interface Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.2 Tuner Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4 MC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.1 MC Interface Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.2 MC Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.3 L3 Bus Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.4 L3 Bus Timing Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.5 I2C Bus Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.6 I2C Bus Timing Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 C-Bus / BOOT Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5.1 C-Bus Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5.2 C-Bus / BOOT Bus Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5.3 BOOT Bus Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5.4 BOOT Bus Timing Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6 SRAM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6.1 SRAM Interface Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6.2 SRAM Interface Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6.3 SRAM Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6.4 SRAM Interface Timing Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.7 VCXO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.7.1 VCXO Interface Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.7.2 VCXO Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 5 5 5 6 6 7 10 11 14 14 14 14 15 15 15 16 16 16 16 16 16 17 18 18 18 19 19 20 20 20 21 21 21 22 23 23 23 23 2 3 4 5 6 2 (69) Rev. A1, 22-May-01 U2739M-B Table of Contents (continued) 6.8 Audio Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8.1 I2S Interface Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8.2 I2S Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8.3 I2S Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8.4 I2S Interface Timing Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8.5 SP-DIF Interface Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8.6 SP-DIF Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8.7 SP-DIF Interface Timing Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8.8 SP-DIF Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.9 RDI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.9.1 RDI Interface Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.9.2 RDI Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.9.3 RDI Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.9.4 RDI Interface Timing Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.10 SFCO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.10.1 SFCO Interface Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.10.2 SFCO Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.10.3 SFCO Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.10.4 Detailed SFCO Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.10.5 SFCO Interface Timing Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.11 RS232 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.11.1 RS232 Interface Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.11.2 RS232 Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.11.3 RS232 Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.11.4 RS232 Interface Timing Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.12 HSSO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.12.1 HSSO Interface Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.12.2 HSSO Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.12.3 HSSO Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.12.4 HSSO Interface Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1 ’Set System’ Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.1 Set DAB System Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.2 Set ASD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.3 Set DD1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.4 Set DD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.5 Set CIF Counter and Occurrence Change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.6 Set Current SBCHID Long Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.7 Set Next SBCHID Long Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.8 Set Current SBCHID Short Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 24 24 24 24 24 25 25 25 25 25 25 25 26 26 26 26 27 28 29 29 29 29 29 29 30 30 30 30 30 31 31 31 31 32 32 32 33 35 36 37 38 40 42 3 (69) 7 8 Rev. A1, 22-May-01 U2739M-B Table of Contents (continued) ’Set Configuration’ Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.1 Set Global Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.2 Set TS Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.3 Set FS Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.4 Set XO Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.5 Set HSSO / RS232 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.6 Set WAGC Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.7 Set RCC Slot Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.8 Set RFU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3 ’Read Status’ Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.1 Read Global Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.2 Read Synchronization Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.3 Read CIR Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4 ’Read Data’ Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.1 Read ASD Header Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.2 Read X–PAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.3 Read F–PAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.4 Read AIC Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.5 Read TII Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.6 Read EFC Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.7 Read FIC Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.8 Read RCC Slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.9 Read Slot Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.10 Read RFU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2 43 43 44 46 47 48 50 51 52 53 53 55 56 57 57 58 59 60 61 62 63 64 65 66 67 9 4 (69) Rev. A1, 22-May-01 U2739M-B 1 1.1 Features General D Digital AGC with a wide gain control range D Off-chip de-interleaver memory for full 1.8 Mbit/s decoding data rate D Time & frequency synchronization on DSP OAK core D Support of TII decoding and corresponding RDI insertion (set 2) D Support of mode I, II, III and IV acc. to ETS 300 401 D Time & frequency synchronization with a wide-range parameter set D Optional implementation of user-defined synchronization strategy by using USE boot mode D Flexible software configuration: set 1 – (temic kernel), set 2 – (user extension) concept D Automatic mode detection (AMD) D FIC on-chip memory, access via MC interface D Generation of receiver status information D Generation of tuner control signals D Generation of pulse width modulated VCXO control signal D Power supply 3.3 V, master clock 24.576 MHz D Plastic TQFP100 package or D Ceramic QFP144 package for software development 1.3 Audio Source Decoder D Supports MPEG1 layer II streams according to ISO/ IEC 11172/3 D Supports MPEG2 layer II (half sampling rate) streams according to ISO/IEC 13818–3 D Supports all bit rates defined in the ETS 300 401 standard D I2S and SPDIF output interfaces D Programmable fader D Programmable DRC D PAD extraction 1.2 Channel Decoder 1.4 Data Decoder D 2 independent packet mode decoder D Flexible configuration via MC commands D Data group length limited to ~1 kbyte each D Output via HSSO or V24 D DD1 option: FIDC decoder D Support of AIC decoding (set 2) D Demodulation and decoding of up to 64 UEP/EEP sub-channels D Support of dynamic multiplex reconfiguration (DMR) without mute state D Digital Null-Symbol detection (FSYNCH generation) D Channel filtering (48 dB) D Optional SAW filter equalization D Digital AFC (freq. tolerance < 0.5 Hz for mode I) Rev. A1, 22-May-01 5 (69) U2739M-B 1.5 Interfaces D 10-bit ADC interface: – ADC sampling clock generation – ADC binary or 2’s complement format selection – support of several intermediate frequencies D DSP OAK core bootstrap ROM interface D Voltage controlled reference oscillator (VCXO) interface D Time de-interleaver SRAM (4 Mbit) interface D High speed serial output HSSO (PAD, DD1, DD2, CIR) interface, 3-line serial burst mode interface D Source decoder output interface: I2S and SPDIF D Data decoder output interface: V24 or HSSO D Channel decoder output interface: RDI and SFCO D Microcontroller interface: D RDI: – Extended high capacity mode – IEC 958 format – RDI control channel (RCC) D SFCO simple full capacity output: – window-, serial sub-channel identifier (SbChId)-, data-, error- and clock line – 3.072 MHz burst mode interface I2C/L3 2 Functional Block Diagram SRAM I2S ADC IQ splitting filtering AFC AGC SLI W_AGC FSYNC generation PWM AMD FSYNC Time synchro– nization Frequency synchro– nization TII decoding (USE) Demodulation FS_IN PAD extraction Source decoder Status generation Channel decoder Deinterleaving Decodeing Audio source decoding DAC SPDIF TUNER dF Data decoder 1 (FIDC) Data decoder 2 (AIC (USE)) V24/RS232 VCXO tank XO UNIT Data decoder ROM BOOT UNIT MC interface MC memory MC interface RDI controller RDI interface RDI_TX RDI_RX U2739M-B HSSO MC SFCO Figure 2. Functional block diagram 6 (69) Rev. A1, 22-May-01 U2739M-B 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 32 23 24 25 26 27 28 29 30 31 22 21 19 20 17 18 10 11 12 13 14 15 16 6 7 8 9 2 3 4 5 Pin Description QFP100 1 Pin Name ADC_CLK TIN0 TIN1 ADC_DATA9 ADC_DATA8 ADC_DATA7 ADC_DATA6 TIN2 DVSSE ADC_DATA5 ADC_DATA4 ADC_DATA3 ADC_DATA2 TIN3 TIN4 ADC_DATA1 ADC_DATA0 DVSS1 AVSS1 XIN XOUT AVDD1 /C_DR /RS PWM /C_DW W_AGC SLI /C_PR HSSO_WIN /C_PW HSSO _CLK /ABORT HSSO _DAT C_ADD0 C_ADD1 /BOOT_RE C_ADD2 C_ADD3 C_ADD4 C_ADD5 C_ADD6 TOUT0 C_ADD7 Signal Description ADC sampling clock output 8.192 MHz Test input 0 (pull down) Test input 1 (pull down) ADC data input, bit 9 (MSB) ADC data input, bit 8 ADC data input, bit 7 ADC data input, bit 6 Test input 2 (pull down) Ground ADC data input, bit 5 ADC data input, bit 4 ADC data input, bit 3 ADC data input, bit 2 Test input 3 (pull down) Test input 4 (pull down) ADC data input, bit 1 ADC data input, bit 0 (LSB) Digital ground Analog ground Oscillator input Oscillator output Analog power supply C-bus data read enable Low active reset Pulse width modulated control output C-bus data write enable Window AGC Synchronization lock indicator C-bus program read enable HSSO window signal C-bus program write enable HSSO clock signal Low active ABORT signal (pull up) HSSO data signal C-bus address bit 0 (LSB) C-bus address bit 1 BOOT read enable C-bus address bit 2 C-bus address bit 3 C-bus address bit 4 C-bus address bit 5 C-bus address bit 6 Test output bit 0 C-bus address bit 7 Pad Type PDO04T PDDZ PDDZ PDIZ PDIZ PDIZ PDIZ PDDZ PVSS1Z, PVSS2Z PDIZ PDIZ PDIZ PDIZ PDDZ PDDZ PDIZ PDIZ PVSS1Z, PVSS2Z PVSS3Z PDX02 (PDX02) PVDD3Z PRO04T PDIZ PRO04T PRO04T PRO04T PRO04T PRO04T PRO04T PRO04T PRO04T PDUZ PRO04T PRO04T PRO04T PRO04T PRO04T PRO04T PRO04T PRO04T PRO04T PRO02T PRO04T Dir. out in in in in in in in gnd in in in in in in in in gnd gnd osc osc pwr out in out out out out out out out out in out out out out out out out out out out out x x x x x x x x x x x x x x x x x x x x 5 V Tol. QFP144 Rev. A1, 22-May-01 7 (69) U2739M-B QFP144 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 59 60 61 62 58 54 55 56 57 49 50 51 52 53 47 48 45 46 42 43 44 40 41 QFP100 33 34 35 36 37 38 39 Pin Name C_ADD8 C_ADD9 C_ADD10 C_ADD11 C_ADD12 DVDD1 C_ADD13 C_ADD14 C_ADD15 C_DATA0/DBG C_DATA1/BOOT C_DATA8 C_DATA9 DVSS2 C_DATA2/URST C_DATA3/XUSE C_DATA10 C_DATA11 C_DATA4/PSPC C_DATA5/RDI_VBIT C_DATA12 C_DATA13 C_DATA6/XO12 C_DATA7/ADE C_DATA14 C_DATA15 TEST_MODE/BYPP MCM_TRIGGER MC_MODE MC_CLK MC_DAT DVDDE SPDIF RS232 I2S_CLK I2S_DAT TOUT1 I2S_WIN TOUT2 TOUT3 RDI_RX RDI_TX DVSS3 TOUT4 Signal Description C-bus address bit 8 C-bus address bit 9 C-bus address bit 10 C-bus address bit 11 C-bus address bit 12 Digital power supply C-bus address bit 13 C-bus address bit 14 C-bus address bit 15 C-bus data bit 0 (pull down) C-bus data bit 1 (pull down) C-bus data bit 8 (pull down) C-bus data bit 9 (pull down) Digital ground C-bus data bit 2 (pull down) C-bus data bit 3 (pull down) C-bus data bit 10 (pull down) C-bus data bit 11 (pull down) C-bus data bit 4 (pull down) C-bus data bit 5 (pull down) C-bus data bit 12 (pull down) C-bus data bit 13 (pull down) C-bus data bit 6 (pull down) C-bus data bit 7 (pull down) C-bus data bit 14 (pull down) C-bus data bit 15 (pull down) Test mode selection (pull down) MCM trigger signal Microcontroller mode signal Microcontroller clock signal Microcontroller data signal Digital power supply SPDIF output RS232 output I2S clock output I2S data output Test output bit 1 I2S win output Test output bit 2 Test output bit 3 RDI receive data RDI transmit data Digital ground Test output bit 4 Pad Type PRO04T PRO04T PRO04T PRO04T PRO04T PVDD1Z, PVDD2Z PRO04T PRO04T PRO04T PRD04TZ PRD04TZ PRD04TZ PRD04TZ PVSS1Z, PVSS2Z PRD04TZ PRD04TZ PRD04TZ PRD04TZ PRD04TZ PRD04TZ PRD04TZ PRD04TZ PRD04TZ PRD04TZ PRD04TZ PRD04TZ PDDZ PRO04T PDIZ PDIZ PRB04TZ PVDD1Z, PVDD2Z PRO04T PRO04T PRO04T PRO04T PRO02T PRO04T PRO02T PRO02T PDIZ PRO04T PVSS1Z, PVSS2Z PRO02T Dir. out out out out out pwr out out out inout inout inout inout gnd inout inout inout inout inout inout inout inout inout inout inout inout in out in in inout pwr out out out out out out out out in out gnd out x x x x x x x x x x x x x x x x x x x x x x x x x 5 V Tol. 8 (69) Rev. A1, 22-May-01 U2739M-B QFP144 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 90 91 88 89 86 87 83 84 85 81 82 78 79 80 76 77 74 75 72 73 70 71 68 69 66 67 63 64 65 QFP100 TOUT5 SFCO_SID SFCO_ERR SFCO_DAT TOUT6 SFCO_CLK SFCO_WIN TOUT7 DVDD2 TOUT8 TOUT9 SRAM_D7 SRAM_D6 TOUT10 SRAM_D5 SRAM_D4 TOUT11 SRAM_D3 SRAM_D2 TOUT12 SRAM_D1 SRAM_D0 TIN5 SRAM_WR SRAM_OE SRAM_A18 TIN6 SRAM_A17 SRAM_A16 TOUT13 SRAM_A15 SRAM_A14 DVSS4 TIN7 SRAM_A13 SRAM_A12 TOUT14 SRAM_A11 SRAM_A10 TOUT15 SRAM_A9 SRAM_A8 Pin Name Signal Description Test output bit 5 SFCO sub-channel ID SFCO errorflag SFCO data Test output bit 6 SFCO clock SFCO window Test output bit 7 Digital power supply Test output bit 8 Test output bit 9 SRAM data bit 7 SRAM data bit 6 Test output bit 10 SRAM data bit 5 SRAM data bit 4 Test output bit 11 SRAM data bit 3 SRAM data bit 2 Test output bit 12 SRAM data bit 1 SRAM data bit 0 Test input 5 (pull down) SRAM write signal SRAM output enable SRAM address bit 18 Test input 6 (pull down) SRAM address bit 17 SRAM address bit 16 Test output bit 13 SRAM address bit 15 SRAM address bit 14 Digital ground Test input 7 (pull down) SRAM address bit 13 SRAM address bit 12 Test output bit 14 SRAM address bit 11 SRAM address bit 10 Test output bit 15 SRAM address bit 9 SRAM address bit 8 Pad Type PRO02T PRO04T PRO04T PRO04T PRO02T PRO04T PRO04T PRO02T PVDD1Z, PVDD2Z PRO02T PRO02T PRB04TZ PRB04TZ PRO02T PRB04TZ PRB04TZ PRO02T PRB04TZ PRB04TZ PRO02T PRB04TZ PRB04TZ PDDZ PRO04T PRO04T PRO04T PDDZ PRO04T PRO04T PRO02T PRO04T PRO04T PVSS1Z, PVSS2Z PDDZ PRO04T PRO04T PRO02T PRO04T PRO04T PRO02T PRO04T PRO04T Dir. out out out out out out out out pwr out out inout inout out inout inout out inout inout out inout inout in out out out in out out out out out gnd in out out out out out out out out x x x x x x x x x x x x x 5 V Tol. Rev. A1, 22-May-01 9 (69) U2739M-B QFP144 131 132 133 134 135 136 137 138 139 140 141 142 143 144 99 100 97 98 95 96 92 93 94 QFP100 TOUT16 SRAM_A7 SRAM_A6 DVDD3 TOUT17 SRAM_A5 SRAM_A4 TMUX0 SRAM_A3 SRAM_A2 TMUX1 SRAM_A1 SRAM_A0 TMUX2 Pin Name Signal Description Test output bit 16 SRAM address bit 7 SRAM address bit 6 Digital power supply Test output bit 17 SRAM address bit 5 SRAM address bit 4 Test mux in bit 0 (LSB) (pull down) SRAM address bit 3 SRAM address bit 2 Test mix in bit 1 (pull down) SRAM address bit 1 SRAM address bit 0 Test mux in bit 2 (pull down) Pad Type PRO02T PRO04T PRO04T PVDD1Z, PVDD2Z PRO02T PRO04T PRO04T PDDZ PRO04T PRO04T PDDZ PRO04T PRO04T PDDZ Dir. out out out pwr out out out in out out in out out in x x x 5 V Tol. 4 16 17 54 55 59 60 63 64 Strap Pins QFP100 10 11 40 41 43 44 45 46 Pin Name ADC_DATA1 ADC_DATA0 C_DATA0/DBG C_DATA1/BOOT C_DATA2/URST C_DATA3/XUSE C_DATA4/PSPC C_DATA5/ RDI_VBIT C_DATA6/XO12 Signal Description ADC data input, bit 1 ADC data input, bit 0 C-bus data bit 0 C-bus data bit 1 C-bus data bit 2 C-bus data bit 3 C-bus data bit 4 C-bus data bit 5 Pad Type PDIZ PDIZ PRD04TZ PRD04TZ PRD04TZ PRD04TZ PRD04TZ PRD04TZ Dir in in inout inout inout inout inout inout Comment Strap pin OCSEL 1 Strap pin OCSEL 0 Strap pin C_DATA0/DBG Strap pin C_DATA1/BOOT Strap pin C_DATA2/URST Strap pin C_DATA3/XUSE Strap pin C_DATA4/PSPC Strap pin C_DATA5/RDI_VBIT 0 RDI spec.: validity bit 1 1 IEC958 spec.: validity bit 0 Strap pin C_DATA6/XO12 0 external oscillator 24.576 MHz 1 external oscillator 12.288 MHz Strap pin C_DATA7/ADE 0 ADC_DATA strap pin function disabled 1 ADC_DATA strap pin function enabled Strap pin TEST_MODE/BYPP 0 PLL activated 1 PLL bypassed Strap pin I2C/L3 0 I2C 1 L3 QFP144 67 47 C-bus data bit 6 PRD04TZ inout 68 48 C_DATA7/ADE C-bus data bit 7 ADC_DATA strap pin function enable PRD04TZ inout 71 49 TEST_MODE/BYPP Test mode selection PDDZ in 73 51 MC_MODE Microcontroller mode signal PDIZ in 10 (69) Rev. A1, 22-May-01 U2739M-B 5 Pin Configuration SRAM_A0 SRAM_A1 SRAM_A2 SRAM_A3 SRAM_A4 SRAM_A5 DVDD3 SRAM_A6 SRAM_A7 SRAM_A8 SRAM_A9 SRAM_A10 SRAM_A11 SRAM_A12 SRAM_A13 DVSS4 SRAM_A14 SRAM_A15 SRAM_A16 SRAM_A17 SRAM_A18 SRAM_OE SRAM_WR SRAM_D0 SRAM_D1 ADC_CLK ADC_D9 ADC_D8 ADC_D7 ADC_D6 ADC_D5 ADC_D4 ADC_D3 ADC_D2 ADC_D1 ADC_D0 DVSS1 AVSS1 XOUT XIN AVDD1 /RS PWM W_AGC SLI HSSO_WIN HSSO_CLK HSSO_DAT C_ADD0 C_ADD1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 QFP100 SRAM_D2 SRAM_D3 SRAM_D4 SRAM_D5 SRAM_D6 SRAM_D7 TOUT8 DVDD2 SFCO_WIN SFCO_CLK SFCO_DAT SFCO_ERR SFCO_SID DVSS3 RDI_TX RDI_RX TOUT3 I2S_WIN I2S_DAT I2S_CLK RS232 SPDIF MC_DAT MC_CLK MC_MODE Rev. A1, 22-May-01 /BOOT_RE C_ADD2 C_ADD3 C_ADD4 C_ADD5 C_ADD6 C_ADD7 C_ADD8 C_ADD9 C_ADD10 C_ADD11 C_ADD12 DVDD1 C_ADD13 C_DATA0 C_DATA1 DVSS2 C_DATA2 C_DATA3 C_DATA4 C_DATA5 C_DATA6 C_DATA7 TEST_MODE MCM_TRIGGER 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Figure 3. Production version QFP100 11 (69) U2739M-B 12 (69) /BOOT_RE C_ADD2 C_ADD3 C_ADD4 C_ADD5 C_ADD6 TOUT0 C_ADD7 C_ADD8 C_ADD9 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 36 C_ADD1 35 C_ADD0 34 HSSO_DAT 33 /ABORT 32 HSSO_CLK 31 /C_PW 30 HSSO_WIN 29 /C_PR 28 SLI 27 W_AGC 26 /C_DW 25 PWM 24 /RS 23 /C_DR 22 AVDD1 21 XIN 20 XOUT 19 AVSS1 18 DVSS1 17 ADC_D0 16 ADC_D1 15 TIN4 14 TIN3 13 ADC_D2 12 ADC_D3 11 ADC_D4 10 ADC_D5 9 DVSSE 8 TIN2 7 ADC_D6 6 ADC_D7 5 ADC_D8 4 ADC_D9 3 TIN1 2 TIN0 1 ADC_CLK 144 143 142 141 140 139 138 137 136 135 134 133 132 TMUX2 SRAM_A0 SRAM_A1 TMUX1 SRAM_A2 SRAM_A3 TMUX0 SRAM_A4 SRAM_A5 TOUT17 DVDD3 SRAM_A6 SRAM_A7 Figure 4. Software development version QFP144 C_ADD10 C_ADD11 C_ADD12 DVDD1 C_ADD13 C_ADD14 C_ADD15 C_DATA0 C_DATA1 C_DATA8 C_DATA9 DVSS2 C_DATA2 C_DATA3 C_DATA10 C_DATA11 C_DATA4 C_DATA5 C_DATA12 C_DATA13 C_DATA6 C_DATA7 C_DATA14 C_DATA15 TEST_MODE MCM_TRIGGER 131 TOUT16 130 129 128 SRAM_A8 SRAM_A9 TOUT15 CQFP 144 127 SRAM_A10 126 125 124 123 122 SRAM_A11 TOUT14 SRAM_A12 SRAM_A13 TIN7 121 DVSS4 120 119 118 117 116 115 114 113 112 111 SFCO_ERR SFCO_DAT MC_MODE SFCO_CLK SFCO_WIN SRAM_A14 SRAM_A15 TOUT13 SRAM_A16 SRAM_A17 TIN6 SRAM_A18 SRAM_OE SRAM_WR TIN5 SRAM_D0 SRAM_D1 Rev. A1, 22-May-01 71 72 110 TOUT12 SFCO_SID SRAM_D5 SRAM_D4 SRAM_D3 SRAM_D2 SRAM_D7 SRAM_D6 MC_DAT I2S_DAT I2S_WIN MC_CLK 74 I2S_CLK TOUT10 RDI_RX RDI_TX TOUT6 DVDDE DVSS3 TOUT4 TOUT5 TOUT11 DVDD2 TOUT1 TOUT2 TOUT3 TOUT7 TOUT8 TOUT9 RS232 SPDIF 109 100 101 102 103 104 105 106 107 108 73 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 U2739M-B SRAM_A14 SRAM_A15 SRAM_A11 SRAM_A10 SRAM_A16 SRAM_A12 SRAM_A13 SRAM_A17 SRAM_A18 SRAM_A7 SRAM_A9 SRAM_WR SRAM_A0 SRAM_A4 SRAM_A5 SRAM_OE SRAM_A1 SRAM_A3 SRAM_A2 SRAM_A6 SRAM_A8 SRAM_D0 109 108 SRAM_D2 SRAM_D3 ADC_D9 105 SRAM_D4 104 103 102 SRAM_D6 101 100 99 TOUT8 98 97 96 SFCO_WIN 95 94 93 SFCO_DAT 92 91 SFCO_SID 90 89 88 DVSS3 RDI_TX /RS PWM RDI_RX TOUT3 87 86 85 84 83 W_AGC SLI I2S_DAT HSSO_WIN I2S_CLK RS232 HSSO_CLK SPDIF I2S_WIN 82 81 80 79 78 77 76 HSSO_DAT C_ADD0 C_ADD1 MC_DAT MC_CLK MC_MODE 75 74 73 SFCO_CLK ADC_D1 ADC_D0 DVSS1 AVSS1 XOUT XIN AVDD1 DVDD2 SRAM_D7 ADC_D5 ADC_D4 ADC_D3 ADC_D2 SRAM_D5 ADC_D8 ADC_D7 ADC_D6 106 107 SFCO_ERR 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 ADC_CLK CQFP 144 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 TEST_MODE DVDD1 C_DATA6 C_ADD13 C_DATA4 C_DATA0 C_DATA1 C_DATA2 C_DATA3 C_DATA5 C_DATA7 DVSS2 110 MCM_TRIGGER 72 C_ADD2 C_ADD3 C_ADD4 C_ADD5 C_ADD6 C_ADD7 C_ADD8 /BOOT_RE C_ADD9 C_ADD11 C_ADD10 Figure 5. Version QFP144 used as production version Rev. A1, 22-May-01 C_ADD12 111 SRAM_D1 DVDD3 DVSS4 13 (69) U2739M-B 6 6.1 Interface Description Overview The interface description explains the purpose, the utilization and the meaning of every interface and every signal. It is divided into twelve sections, which are related to the different interfaces. An overview of all interfaces is shown in the functional block diagram below. Several standard output interfaces like I2S or SPDIF are used to offer a flexible usage of the U2739M-B. SRAM I2S ADC IQ splitting filtering AFC AGC SLI W_AGC FSYNC generation PWM AMD FSYNC Time synchro– nization Frequency synchro– nization TII decoding (USE) Demodulation FS_IN PAD extraction Source decoder Status generation Channel decoder Deinterleaving Decodeing Audio source decoding DAC SPDIF TUNER dF Data decoder 1 (FIDC) Data decoder 2 (AIC (USE)) V24/RS232 VCXO tank XO UNIT Data decoder ROM BOOT UNIT MC interface MC memory MC interface RDI controller RDI interface RDI_TX RDI_RX U2739M-B HSSO MC SFCO Figure 6. Functional block diagram 6.2 6.2.1 ADC Interface ADC Interface Signal Description QFP100 1 2 3 4 5 6 7 8 9 10 11 Pin Name ADC_CLK ADC_DATA9 ADC_DATA8 ADC_DATA7 ADC_DATA6 ADC_DATA5 ADC_DATA4 ADC_DATA3 ADC_DATA2 ADC_DATA1 ADC_DATA0 Signal Description ADC sampling clock output 8.192 MHz ADC data input, bit 9 (MSB) ADC data input, bit 8 ADC data input, bit 7 ADC data input, bit 6 ADC data input, bit 5 ADC data input, bit 4 ADC data input, bit 3 ADC data input, bit 2 ADC data input, bit 1 ADC data input, bit 0 (LSB) Pad Type PDO04T PDIZ PDIZ PDIZ PDIZ PDIZ PDIZ PDIZ PDIZ PDIZ PDIZ Dir. out in in in in in in in in in in x x x x x x x x x x 5 V Tol. QFP144 1 4 5 6 7 10 11 12 13 16 17 14 (69) Rev. A1, 22-May-01 U2739M-B 6.2.2 ADC Interface Description typical output delay (td3 in figure 7) of the AD converter related to the falling edge of the sampling clock CLK8192 should be 20 ns. The generated 8.192 MHz output clock take over the ADC_DATA with his rising edge of ADC_CLK. The format ‘binary offset’ or ‘2’s complement’ of the A/D converter can be selected by the parameter ADCF. This parameter is also defined by the ‘set global configuration’ MC command [Atmel Wireless & Microcontrollers U2739M documentation set – “U2739M_MC_Command_set_vxxx.pdf”]. Furthermore, the sampling clock generation is performed by the U2739M-B. The input data appearing at the ADC_DATA port are assumed to be generated by an A/D converter. The effective resolution of this converter should be greater than 9 bit in order to use the full dynamic range implemented in the U2739M-B. The sampling clock required for the external A/D converter is derived inside U2739M-B. It has to be 8.192 MHz. The ADC interface as shown in figure 6 consists of the ADC data input signal ADC_DATA(9:0) and the ADC sampling clock output signal ADC_CLK. The U2739M-B can be connected to every standard AD with either binary or 2’s complement output format. The sampling frequency is 8.192 MHz and a bandwidth of 2 MHz is necessary. The possible IF’s, which are supported in conjunction with the IF input signal mode (parameter IFM) are given by the formula. fif = 2.048 MHz + n 4.096 MHz, with n = 0, 1, 2, 3 .... Thus possible IFs are 2.048 MHz, 6.144 MHz, ... 38.912 MHz. The parameter IFM is defined by the MC command ‘set global configuration’ [Atmel Wireless & Microcontrollers U2739M documentation set – “U2739M_MC_Command_set_vxxx.pdf”]. The analog input bandwidth of the A/D converter must be chosen accordingly. The ADC_DATA input is 10 bit wide. The 6.2.3 ADC Interface Timing Diagram tclk tH tL XIN td1 td1 tc8 H tc8 tc8 L ADC_CLK ADC_D[9:0] ts1 Figure 7. ADC interface timing diagram 6.2.4 ADC Interface Timing Parameters Parameter Symbol tclk tH tL tc8 tc8H tc8L ts1 td1 5.0 12.0 20.0 28.0 15.0 15.0 Min. Typ. 40.7 20.35 20.35 3 × 40.7 1 × 40.7 2 × 40.7 25.0 25.0 Max. Unit ns ns ns ns ns ns ns ns XIN clock period XIN clock high XIN clock low ADC_CLK clock period ADC_CLK clock high ADC_CLK clock low Setup time ADC_D(9:0) Output delay of ADC_CLK Rev. A1, 22-May-01 15 (69) U2739M-B 6.3 6.3.1 QFP144 27 Tuner Interface Tuner Interface Signal Description QFP100 19 Pin Name W_AGC Signal Description Window AGC 0 during COFDM symbols 1 during the NULL symbol Synchronization lock indicator 0 receiver synchronization not locked 1 receiver synchronization locked Pad Type PRO04T Dir. out 5 V Tol. 28 20 SLI PRO04T out 6.3.2 Tuner Interface Description the set WAGC configuration MC command. The WAGC signal does not follow the moving FFT window. The rising and falling edge can be adjusted by the MC. The MC can use the differential dT, which correspond to the FFT window shift, from the read synchronization status command to adjust the WAGC rising and falling edge. In order to implement a flexible AGC concept of a DAB receiver the signals W_AGC and SLI can be used to control the tuner IC U2731B. The influence of W_AGC and SLI to the RF AGC voltage generation block is described in the U2731B preliminary datasheet. The WAGC signal must be controlled by the MC by using 6.4 6.4.1 MC Interface MC Interface Signal Description QFP100 50 51 Pin Name MCM_TRIGGER MC_MODE Signal Description MCM trigger signal Microcontroller mode signal 0 I2C bus protocol 1 L3 bus protocol Microcontroller clock signal Microcontroller data signal Pad Type PRO04T PDIZ Dir. out in x 5 V Tol. QFP144 72 73 74 75 52 53 MC_CLK MC_DAT PDIZ PRB04TZ in inout x x 6.4.2 MC Interface Description The external MCU is able to communicate with the U2739M-B during LOW phases of MCM_TRIGGER only ! Further the MCM trigger signal indicates the synchronization status. If the MCM trigger has period of 8 ms, then the U2739M-B is not locked. In the synchronized (‘locked’) state the MCM trigger period correspond to the CIF frame, which is provided every 24 ms. The complete FIC is processed at the beginning of the transmission frame. The MC interface is used for data transmission between the U2739M-B (slave) and an external microcontroller (master). It can be configured for L3- or I2C protocol depending on the status of the MC_MODE line during reset (/RS = LOW): MC_MODE = HIGH MC_MODE = LOW V V L3 bus selected I2C bus selected The MCM_TRIGGER line indicates the status of the internal interface controller. 16 (69) Rev. A1, 22-May-01 U2739M-B 6.4.3 L3 Bus Interface Timing Diagram 1 ts2 Address mode th2 MC_MODE tLC tHC MC_CLK MC_DAT ts1 0 th1 1 6 7 2 ts2 Data mode th2 MC_MODE tLC tHC MC_CLK MC_DAT (MCU U2739M) ts 0 th1 1 6 7 MC_DAT (U2739M MCU) 0 td1 1 6 7 3 Halt mode tL MC_MODE th2 ts2 MC_CLK td3 td2 MC_DAT (U2739M MCU) high Z Figure 8. MC L3 bus interface timing diagram Rev. A1, 22-May-01 17 (69) U2739M-B 6.4.4 L3 Bus Timing Parameter Parameter MC_CLK low phase MC_CLK high phase MC_DAT input setup time MC_DAT input hold time MC_MODE hold time MC_MODE setup time MC_CLK(h/l) / MC_DAT delay MC_MODE(l/h) / MC_DAT (output driven) MC_CLK(l/h) / MC_DAT(high Z) Symbol tLC tHC ts1 th1 th2 ts2 td1 td2 td3 Min. 61 61 61 61 61 61 20 110 120 100 130 160 Typ. Max. Unit ns ns ns ns ns ns ns ns ns 6.4.5 I2C Bus Interface Timing Diagram tBF thS tsS thS tsS MC_DATA tsD 7 thD 0 7 0 tLC tHC MC_CLK S p S t r S t S p Figure 9. MC I2C bus timing diagram 6.4.6 I2C Bus Timing Parameter Parameter Symbol tBF thS tsD thD tLC tHC tsS Min. 400 200 120 320 300 200 240 Typ. Max. Unit ns ns ns ns ns ns ns Bus free time between STOP and START condition Hold time (repeated) START condition Setup time data Hold time data Low period clock High period clock Setup time: repeated START condition, STOP condition 18 (69) Rev. A1, 22-May-01 U2739M-B 6.5 6.5.1 QFP144 23 26 29 31 35 36 37 38 39 40 41 42 44 45 46 47 48 49 51 52 53 54 55 56 57 59 60 61 62 63 64 65 66 67 68 69 70 47 48 45 46 43 44 40 41 24 25 26 27 28 29 30 31 32 33 34 35 36 37 39 C-Bus / BOOT Bus Interface C-Bus Signal Description QFP100 Pin Name /C_DR /C_DW /C_PR /C_PW C_ADD0 C_ADD1 /BOOT_RE C_ADD2 C_ADD3 C_ADD4 C_ADD5 C_ADD6 C_ADD7 C_ADD8 C_ADD9 C_ADD10 C_ADD11 C_ADD12 C_ADD13 C_ADD14 C_ADD15 C_DATA0/DBG C_DATA1/BOOT C_DATA8 C_DATA9 C_DATA2/URST C_DATA3/XUSE C_DATA10 C_DATA11 C_DATA4/PSPC C_DATA5/RDI_VBIT C_DATA12 C_DATA13 C_DATA6/XO12 C_DATA7/BYPP C_DATA14 C_DATA15 Signal Description C-bus data read enable C-bus data write enable C-bus program read enable C-bus program write enable C-bus address bit 0 (LSB) C-bus address bit 1 BOOT read enable C-bus address bit 2 C-bus address bit 3 C-bus address bit 4 C-bus address bit 5 C-bus address bit 6 C-bus address bit 7 C-bus address bit 8 C-bus address bit 9 C-bus address bit 10 C-bus address bit 11 C-bus address bit 12 C-bus address bit 13 C-bus address bit 14 C-bus address bit 15 C-bus data bit 0 (pull down) C-bus data bit 1 (pull down) C-bus data bit 8 (pull down) C-bus data bit 9 (pull down) C-bus data bit 2 (pull down) C-bus data bit 3 (pull down) C-bus data bit 10 (pull down) C-bus data bit 11 (pull down) C-bus data bit 4 (pull down) C-bus data bit 5 (pull down) C-bus data bit 12 (pull down) C-bus data bit 13 (pull down) C-bus data bit 6 (pull down) C-bus data bit 7 (pull down) C-bus data bit 14 (pull down) C–-bus data bit 15 (pull down) Pad Type PRO04T PRO04T PRO04T PRO04T PRO04T PRO04T PRO04T PRO04T PRO04T PRO04T PRO04T PRO04T PRO04T PRO04T PRO04T PRO04T PRO04T PRO04T PRO04T PRO04T PRO04T PRD04TZ PRD04TZ PRD04TZ PRD04TZ PRD04TZ PRD04TZ PRD04TZ PRD04TZ PRD04TZ PRD04TZ PRD04TZ PRD04TZ PRD04TZ PRD04TZ PRD04TZ PRD04TZ Dir. out out out out out out out out out out out out out out out out out out out out out inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout x x x x x x x x x x x x x x x x 5 V Tol. Rev. A1, 22-May-01 19 (69) U2739M-B 6.5.2 C-Bus / BOOT Bus Interface Description Atmel Wireless & Microcontrollers firmware. The BOOT bus is a standard ROM interface (address/ data buses, read enable line) and the read access is always with 16 wait states (referring the OAK internal 49.152 MHz clock) to support slow devices. The BOOT bus is available in both package versions. The timing diagram refers to the BOOT bus signals only. The C-Bus is a multiplexed program as well as data bus system to communicate with external components. The complete bus system is available only in the QFP144 package version and needed for debugging the internal OAK DSP core. The BOOT bus covers a subset of the C-Bus signals. The user is able to download his own so-called ’User Software Extensions’ using this bus system to replace or extend the 6.5.3 /BOOT_RE BOOT Bus Timing Diagram C_ADD (13..0) valid address valid address C_DATA (7..0) tacc valid data valid data Figure 10. C-bus interface timing diagram 6.5.4 BOOT Bus Timing Parameter Parameter Symbol tacc Min. Typ. Max. 120 Unit ns BOOT ROM access time 20 (69) Rev. A1, 22-May-01 U2739M-B 6.6 6.6.1 QFP144 100 101 103 104 106 107 109 110 112 113 114 116 117 119 120 123 124 126 127 129 130 132 133 136 137 139 140 142 143 SRAM Interface SRAM Interface Signal Description QFP100 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 86 87 88 89 90 91 92 93 95 96 97 98 99 100 Pin Name SRAM_D7 SRAM_D6 SRAM_D5 SRAM_D4 SRAM_D3 SRAM_D2 SRAM_D1 SRAM_D0 SRAM_WR SRAM_OE SRAM_A18 SRAM_A17 SRAM_A16 SRAM_A15 SRAM_A14 SRAM_A13 SRAM_A12 SRAM_A11 SRAM_A10 SRAM_A9 SRAM_A8 SRAM_A7 SRAM_A6 SRAM_A5 SRAM_A4 SRAM_A3 SRAM_A2 SRAM_A1 SRAM_A0 Signal Description SRAM data bit 7 SRAM data bit 6 SRAM data bit 5 SRAM data bit 4 SRAM data bit 3 SRAM data bit 2 SRAM data bit 1 SRAM data bit 0 SRAM write signal SRAM output enable SRAM address bit 18 SRAM address bit 17 SRAM address bit 16 SRAM address bit 15 SRAM address bit 14 SRAM address bit 13 SRAM address bit 12 SRAM address bit 11 SRAM address bit 10 SRAM address bit 9 SRAM address bit 8 SRAM address bit 7 SRAM address bit 6 SRAM address bit 5 SRAM address bit 4 SRAM address bit 3 SRAM address bit 2 SRAM address bit 1 SRAM address bit 0 Pad Type PRB04TZ PRB04TZ PRB04TZ PRB04TZ PRB04TZ PRB04TZ PRB04TZ PRB04TZ PRO04T PRO04T PRO04T PRO04T PRO04T PRO04T PRO04T PRO04T PRO04T PRO04T PRO04T PRO04T PRO04T PRO04T PRO04T PRO04T PRO04T PRO04T PRO04T PRO04T PRO04T Dir. inout inout inout inout inout inout inout inout out out out out out out out out out out out out out out out out out out out out out 5 V Tol. x x x x x x x x 6.6.2 SRAM Interface Descriptions Due to the high data rates a fast SRAM with a access time of 18 ns or below is necessary. For time de-interleaving and further task an external static random access memory of 4 MB is necessary. The organization of the SRAM is 512 k × 8 bit. Rev. A1, 22-May-01 21 (69) U2739M-B 6.6.3 SRAM Interface Timing Diagram READ CYCLE XIN td1 tavav SRAM_A(18:0) td2 valid address SRAM_WR SRAM_OE td3 HIGH–Z SRAM_D(7:0) tsdata data valid WRITE CYCLE XIN td1 tavav SRAM_A(18:0) td2 valid address SRAM_WR twleh td3 SRAM_OE SRAM_D(7:0) tddata data valid tdvwh Figure 11. SRAM interface timing diagram 22 (69) Rev. A1, 22-May-01 U2739M-B 6.6.4 SRAM Interface Timing Parameter Parameter Read/ write cycle time Output delay SRAM_A(18:0) Output delay SRAM_WR Output delay SRAM_OE Setup time SRAM_D(7:0) Write pulse with Output delay SRAM_D(7:0) Data valid to end of write Symbol tavav td1 td2 td3 tsdata twleh tddata tdvwh 15.0 12.0 16.0 2.0 33.0 15.0 33.0 40.7 23.0 40.7 48.0 31.0 48.0 Min. Typ. 40.7 25.0 20.0 24.0 35.0 28.0 32.0 Max. Unit ns ns ns ns ns ns ns ns 6.7 6.7.1 VCXO Interface VCXO Interface Signal Description QFP100 13 14 15 16 18 Pin Name AVSS1 XIN XOUT AVDD1 PWM Signal Description Analog ground Oscillator input Oscillator output Analog power supply Pulse width modulated control output Pad Type PVSS3Z PDX02 (PDX02) PVDD3Z PRO04T Dir. gnd osc osc pwr out 5 V Tol. x QFP144 19 20 21 22 25 6.7.2 VCXO Interface Description U2739M-B PLL 49.192 MHz PWM PAD XIN PAD XOUT PAD VCXO 24.576 MHz fPWM = fclk2457 / 2n n = 11 –> fPWM = 12 kHz Figure 12. VCXO application circuit The U2739M-B master clock should be derived from a voltage-controlled reference oscillator. The pulse width modulated output signal PWM of the U2739M-B can be used to control the VCXO frequency of 24.576 MHz. Rev. A1, 22-May-01 23 (69) U2739M-B 6.8 6.8.1 QFP144 79 80 82 Audio Interfaces I2S Interface Signal Description QFP100 56 57 58 Pin Name I2S_CLK I2S_DAT I2S_WIN Signal Description I2S clock line I2S data line I2S window line Pad Type PRO04T PRO04T PRO04T Dir. out out out 5 V Tol. 6.8.2 I2S Interface Description As in the DAB system the I2S_WIN clock is fixed as 48 kHz (MPEG1) or 24 kHz (MPEG2) the bit clock depends on the data word length. The standard word length is 16 bit, hence the bit clock is fixed at 1.536 MHz resp. 768 kHz. The I2S interface is a standard continuous audio interface consisting of bit clock (_CLK), word select (_WIN) and data (_DAT) lines. The word select line indicates the transmitted channel: LOW for left, HIGH for right. Please be aware of the 1 cycle delay of the data word MSB corresponding to the I2S_WIN edge ! 6.8.3 I2S Interface Timing Diagram tclk tH tL I2S_CLK I2S_WIN td1 I2S_DAT 0 15 td2 14 13 12 3 2 1 0 15 14 13 12 3 2 1 0 15 14 13 12 left sample right sample Figure 13. I2S interface timing diagram 6.8.4 I2S Interface Timing Parameter Parameter Symbol tclk tH tL td1 td2 –5.0 –5.0 Min. Typ. 16.28 14.28 14.28 0.0 0.0 5.0 5.0 Max. Unit us us us ns ns I2S clock period I2S clock high I2S clock low I2S_WIN output delay I2S_DAT output delay 6.8.5 QFP144 77 SP-DIF Interface Signal Description QFP100 54 Pin Name SPDIF Signal Description SPDIF output Pad Type PRO04T Dir. out 5 V Tol. 24 (69) Rev. A1, 22-May-01 U2739M-B 6.8.6 SP-DIF Interface Description The SP-DIF format is frame based, which means one frame represents one audio sampling period. Every frame comprises 2 subframes a 32 bit referring to the left and right sample. The data is transmitted in bi-phase coded format. The frame synchronization pattern are based on biphase violations and indicate whether a left or right subframe follows. The last 4 bi-phase coded bits of each subframe represent the V (validity flag), U (user channel data), C (channel status data) and P (parity) information as described in the SP-DIF specification. Complete frames (left and right sample according to 64 2 bit due to bi-phase coding) are transmitted at the audio sampling rate (48 resp. 24 kHz). 6.8.7 SP-DIF Interface Timing Parameter The SP-DIF interface was designed according the digital audio interface IEC958 specification [CEI/ISO 958 Digital Audio Interface Standard]. 6.8.8 SPDIF SP-DIF Interface Timing Diagram S3 S2 S1 A0 Frame sync. pattern 8 Zero’s (bi–phase coded) A1 A2 A14 A15 V U C P Audio data bits (bi–phase coded) Flag bits (bi–phase coded) SP–DIF subframe (left or right audio sample) Figure 14. SP-DIF interface timing diagram 6.9 6.9.1 RDI Interface RDI Interface Signal Description QFP100 46 60 61 Pin Name C_DATA5/RDI_VBIT RDI_RX RDI_TX Signal Description C–bus data bit 5 (pull down) RDI receive data RDI transmit data Pad Type PRD04TZ PDIZ PRO04T Dir. inout in out 5 V Tol. x x QFP144 64 85 86 6.9.2 RDI Interface Description data is provided in the extended format of the high capacity mode. Further the RDI Control Channel (RCC) can be implemented according to the preliminary specification [Digital Audio Broadcasting System: Preliminary Specification of the RDI Control Channel], [Proposal of DAB Command Set for Receiver (DCSR)]. The RDI interface is designed according to the ‘Digital Audio Broadcasting System: Specification of the Receiver Data Interface (RDI)’ [Digital Audio Broadcasting System: Specification of the Receiver Data Interface (RDI), Issue 1.4]. The RDI frames are embedded into the IEC 958 interface. The RDI output 6.9.3 RDI Interface Timing Diagram tH tL 2 * tH 2 * tL 3 * tH 3 * tL RDI_TX/RX Figure 15. RDI interface timing diagram Rev. A1, 22-May-01 25 (69) U2739M-B 6.9.4 RDI Interface Timing Parameter The RDI interface is realized according to the digital audio interface IEC958 specification [CEI/ISO 958 Digital Audio Interface Standard]. Parameter Data high period Data low period Symbol TH TL Min. Typ. 160 160 Max. Unit ns ns 6.10 SFCO Interface 6.10.1 QFP144 90 91 92 94 95 SFCO Interface Signal Description QFP100 63 64 65 66 67 Pin Name SFCO_SID SFCO_ERR SFCO_DAT SFCO_CLK SFCO_WIN Signal Description SFCO sub-channel ID SFCO error flag SFCO data SFCO clock SFCO window Pad Type PRO04T PRO04T PRO04T PRO04T PRO04T Dir. out out out out out 5 V Tol. 6.10.2 SFCO Interface Description decoder. The window line can be used to distinguish between FIC and MSC data. Via the MC interface the provided sub-channel can be selected. Only these selected sub-channels are processed by the channel decoder. The simple full capacity output interface (SFCO) is a 3.072 MHz burst mode interface. It consists of a window, data, errorflag and clock line. Furthermore, a serial subchannel identifier information is provided. The interface carries fast information channel (FIC) and main service information (MSC) at the output of the COFDM channel 26 (69) Rev. A1, 22-May-01 U2739M-B 6.10.3 SFCO Interface Timing Diagram FIC 32*clk 2 * 32 * clk 48*clk SFCO_win 3 * 32 * clk 16*clk 80*clk 20*clk 32 * clk 12*clk 16 *clk SFCO_clk SFCO_data FIB1 1 FIB1 12 FIB1 CRC FIB2 1 FIBn 12 FIBn CRC SFCO_SubChId 0 SFCO_ErrFl MSC 32*clk 1*clk SFCO_win 32*clk 22*clk 10 *clk SFCO_clk SFCO_data 6*clk MSC 1 MSC n–1 MSC n SFCO_SubChId ID SFCO_ErrFl Figure 16. SFCO interface timing diagram Rev. A1, 22-May-01 27 (69) U2739M-B 6.10.4 Detailed SFCO Interface Timing Diagram FIC td1 td2 SFCO_win tHC tLC SFCO_clk SFCO_data ts 0 th 1 n SFCO_SubChId 0 SFCO_ErrFl MSC tHW th SFCO_win tHC tLC SFCO_clk SFCO_data ts 0 th 1 6 n SFCO_SubChId 6 5 0 SFCO_ErrFl Figure 17. Detailed SFCO interface timing diagram 28 (69) Rev. A1, 22-May-01 U2739M-B 6.10.5 SFCO Interface Timing Parameter Parameter Clock high period Clock low period Data setup time Data hold time Window MSC high period Delay data valid Delay window FIC low Symbol tHC tLC ts th tHW td1 td2 Min. Typ. 160 160 160 160 10.56 10.24 10.24 Max. Unit ns ns ns ns us us us 6.11 RS232 Interface 6.11.1 QFP144 78 RS232 Interface Signal Description QFP100 55 Pin Name RS232 Signal Description RS232 output Pad Type PRO04T Dir. out 5 V Tol. 6.11.2 RS232 Interface Description D Data decoder 2 D Programme Associated Data (PAD) Each RS232 burst consists of a header word followed by n data words (as indicated in the header): Length (Number of Transmitted Data Words n Without Header Word) 11 10 9 8 7 6 5 4 3 2 1 0 Number of DD1 words Number of DD2 words Number of PAD words out and the baud rate. Please notice the byte order: first the high byte is transmitted followed by the low byte (LSB first both). The RS232 interface is an standard serial output used for transferring data directly to a PC COM port. One of 3 applications can be given out: D Data decoder 1 RS232-ID (Burst Identifier) bit DD1 DD2 PAD 15 0 0 0 14 0 0 0 13 0 1 1 12 1 0 1 The RS232 output can be configured using the ’set HSSO/ RS232 configuration’ MC command [Atmel Wireless & Microcontrollers U2739M documentation set – “U2739M_MC_Command_set_vxxx.pdf”]. Using this command the user can select the application to be given 6.11.3 RS232 RS232 Interface Timing Diagram 8 9 10 14 15 0 1 2 6 7 8 9 10 11 12 Figure 18. RS232 interface timing diagram 6.11.4 RS232 Interface Timing Parameter The RS232 timing is related to the defined baud rate of the interface. Rev. A1, 22-May-01 29 (69) U2739M-B 6.12 HSSO Interface 6.12.1 QFP144 30 32 34 HSSO Interface Signal Description QFP100 21 22 23 Pin Name HSSO_WIN HSSO _CLK HSSO _DAT Signal Description HSSO window signal HSSO clock signal HSSO data signal Pad Type PRO04T PRO04T PRO04T Dir. out out out 5 V Tol. 6.12.2 HSSO Interface Description D Data decoder 2 D Programme Associated Data (PAD) The HSSO can be configured using the ’set HSSO / RS232 configuration’ MC command (see section 8). Each HSSO burst consists of a header word followed by n data words (as indicated in the header). The High Speed Serial Output (HSSO) is a standard 3-line output interface implemented to give out data bursts in a multiplexed way. Up to 4 applications can be given out simultaneously: D Channel Impulse Response (CIR) D Data decoder 1 HSSO-ID (Burst Identifier) bit CIR DD1 DD2 PAD 15 0 0 0 0 14 0 0 0 0 13 0 0 1 1 12 0 1 0 1 Length (Number of Transmitted Data Words n Without Header Word) 11 10 9 8 7 6 5 4 3 2 1 0 Number of CIR words Number of DD1 words Number of DD2 words Number of PAD words 6.12.3 HSSO Interface Timing Diagram tclk tH tL HSSO_CLK HSSO_WIN td1 HSSO_DAT 15 td2 14 13 1 0 15 14 13 1 0 15 0 15 14 1 0 header Data 0 Data n–1 Figure 19. HSSO interface timing diagram 6.12.4 HSSO Interface Timing Parameters Parameter Symbol tclk tH tL td1 td2 –5.0 –5.0 Min. Typ. 4.07 2.035 2.035 0.0 0.0 5.0 5.0 Max. Unit us us us ns ns HSSO clock period HSSO clock high HSSO clock low HSSO_WIN output delay HSSO_DAT output delay 30 (69) Rev. A1, 22-May-01 U2739M-B 7 7.1 Electrical Characteristics Absolute Maximum Ratings Parameter Symbol VDD Vin/Vout Tstg Min. –0.5 –0.5 –65 Max. VDD + 0.5 VDD + 0.5 125 Unit V V °C Supply voltage Input / output voltage Storage temperature 7.2 Operating Range Parameter Symbol VDD Vin/Vout Tamb Pstat Pdyn Min. 3.0 0 –40 20 860 Typ. 3.3 Max. 3.6 VDD +85 Unit V V °C mW mW Supply voltage Input / output voltage Ambient temperature Power dissipation Power dissipation 7.3 DC Characteristics Parameter Test Conditions Pad Type VIH VIL VT IOH= –2 mA IOH= –4 mA IOL= 2 mA IOL= 4 mA VOH VOL Pxx02x Pxx04x Pxx02x Pxx04x 2.4 2.4 0.2 0.2 1.4 VDD VDD 0.4 0.4 Symbol Min. 2.0 0.8 Typ. Max. Unit V V V V V V V Input HIGH voltage Input LOW voltage Threshold Output HIGH voltage Output LOW voltage Rev. A1, 22-May-01 31 (69) U2739M-B 8 8.1 8.1.1 MC Command Set ’Set System’ Commands Set DAB System Mode Command Settings Overview: D Set system mode D Set FSLI control loops Command sequence: Address Mode 7 0 6 1 DAB 5 1 4 0 3 1 U2739M-B 2 1 1 1 0 0 $6E Write Command Data Mode 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 $00 Address Mode 7 0 6 1 DAB 5 1 4 0 3 1 U2739M-B 2 1 1 0 0 0 $6C Write Command Data Mode 7 SMODE 6 5 NSM 4 0 3 0 2 0 1 0 0 0 $XX Command Parameters: Parameter SMODE(1..0) Meaning New DAB system mode 00: 01: 10: 11: 0: 1: Description DAB system mode 4 DAB system mode 1 DAB system mode 2 DAB system mode 3 SMODE not valid SMODE indicates new system mode NSM New system mode valid 32 (69) Rev. A1, 22-May-01 U2739M-B 8.1.2 Set ASD D Set ASD dynamic range control fixed value D Set ASD ScF–CRC on/off D Set ASD dual channel configuration D Set ASD fader value Command sequence: Address Mode 7 0 6 1 DAB 5 1 4 0 3 1 U2739M-B 2 1 1 1 0 0 $6E Command Settings Overview: D Set ASD on/off D Set ASD mute state D Set ASD sub–channel ID D Set ASD dynamic range control on/off Write Command Data Mode 7 0 6 0 5 0 4 1 3 0 2 0 1 0 0 0 $10 Address Mode 7 0 6 1 DAB 5 1 4 0 3 1 U2739M-B 2 1 1 0 0 0 $6C Write Command Data Mode 7 ASDE FADD DCC 6 MUTE 5 IDV 4 DCCV 3 FADV SBCHID DRCFV 2 DRCON 1 0 $XX $XX $XX DRCFIX SCFON Rev. A1, 22-May-01 33 (69) U2739M-B Command Parameters: Parameter ASDE MUTE IDV DCCV FADV DRCON DRCFIX SCFON FAD Meaning ASD enable ASD mute state ASD SBCHID valid DCC setting valid Fader setting valid DRC on/off switch 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: ASD disabled ASD enabled ASD output active ASD output muted Last set ASD SBCHID remains valid Following ASD SBCHID valid Last set DCC remains valid Following DCC valid Last set FAD remains valid Following FAD valid DRC off DRC on DRC additional fixed gain + 6 dB (default) DRC additional fixed gain according to DRCFV ScF–CRC off ScF–CRC on Fade In / Fade out over 0 frames each Fade In / Fade out over 30 frames each Fade In / Fade out over 60 frames each Fade In / Fade out over 90 frames each ASD sub–channel ID Description DRC additional fixed gain 0: value valid 1: ScF–CRC on/off switch Fader value 0: 1: 00: 01: 10: 11: n: SBCHID(5..0) DCC(1..0) Sub–channel identifier Dual channel configuration 00/10: Left channel on both ASD output channels 01: Right channel on both ASD output channels 11: Both channels on ASD output DRCFV(5..0) DRC additional fixed gain 000000: Fixed gain 0 dB value 000001: Fixed gain + 0.25 dB ... (continuous steps of +0.25 dB) 111111: fixed gain + 15.75 dB 34 (69) Rev. A1, 22-May-01 U2739M-B 8.1.3 Set DD1 DD configuration for transmission in packet mode Command Settings Overview: D Set DD1 on/off D Set DD1 sub–channel ID D Set DD1 packet address Command sequence: Address Mode 7 0 6 1 DAB 5 1 4 0 3 1 U2739M-B 2 1 1 1 0 0 $6E Write Command Data Mode 7 0 6 0 5 0 4 1 3 0 2 0 1 0 0 1 $11 Address Mode 7 0 6 1 DAB 5 1 4 0 3 1 U2739M-B 2 1 1 0 0 0 $6C Write Command Data Mode 7 DD1E 0 6 FIDC 5 PA1V 4 ID1V PA(7..0) 3 0 SBCHID 2 1 PA(9/8) 0 $XX $XX $XX Command Parameters: Parameter DD1E FIDC PA1V ID1V PA(9..0) SBCHID(5..0) 1) Meaning DD1 enable FIDC decoding switch PA valid DD1 SBCHID valid Packet address Sub–channel identifier 0: 1: 0: 1: 0: 1: 0: 1: n: n: DD1 disabled DD1 enabled DD1 decodes MSC DD1 decodes FIDC 1) Last set DD1 PA remains valid Following DD1 PA valid Last set DD1 SBCHID remains valid Following DD1 SBCHID valid DD1 packet address DD1 sub–channel ID Description in this case PA and SBCHID parameters are ignored (regardless of whether PA1V/ID1V have been set or not) 35 (69) Rev. A1, 22-May-01 U2739M-B 8.1.4 Set DD2 DD configuration for transmission in packet mode Command Settings Overview: D Set DD2 on/off D Set DD2 AIC on/off D Set DD2 sub–channel ID D Set DD2 packet address Command sequence: Address Mode 7 0 6 1 DAB 5 1 4 0 3 1 U2739M-B 2 1 1 1 0 0 $6E Write Command Data Mode 7 0 6 0 5 0 4 1 3 0 2 0 1 1 0 0 $12 Address Mode 7 0 6 1 DAB 5 1 4 0 3 1 U2739M-B 2 1 1 0 0 0 $6C Write Command Data Mode 7 DD2E 0 6 AIC 5 PA2V 4 ID2V PA(7..0) 3 0 SBCHID 2 1 PA(9/8) 0 $0X $XX $XX Command Parameters: Parameter DD2E AIC PA2V ID2V PA(9..0) SBCHID(5..0) 1) Meaning DD2 enable AIC decoding switch DD2 PA valid DD2 SBCHID valid Packet address Sub–channel identifier 0: 1: 0: 1: 0: 1: 0: 1: n: n: DD2 disabled DD2 enabled DD2 decodes MSC DD2 decodes AIC 2) Last set DD2 PA remains valid Following DD2 PA valid Last set DD2 SBCHID remains valid Following DD2 SBCHID valid DD2 packet address DD2 sub–channel ID Description in this case PA and SBCHID parameters are ignored (regardless of whether PA2V/ID2V have been set or not) and the default values for AIC decoding (PA = 1023, SBCHID = 63) are used instead 36 (69) Rev. A1, 22-May-01 U2739M-B 8.1.5 Set CIF Counter and Occurrence Change Command Settings Overview: D Set channel decoder CIF counter D Set channel decoder occurrence change Command sequence: Address Mode 7 0 6 1 DAB 5 1 4 0 3 1 U2739M-B 2 1 1 1 0 0 $6E Write Command Data Mode 7 0 6 0 5 0 4 1 3 0 2 0 1 1 0 1 $13 Address Mode 7 0 6 1 DAB 5 1 4 0 3 1 U2739M-B 2 1 1 0 0 0 $6C Write Command Data Mode 7 CF 6 5 AF 4 3 2 CIFCH(4..0) 1 0 $XX $XX $XX CIFCL(7..0) OC(7..0) Command Parameters: Parameter CF(1..0) Meaning Change flags 00: 01: 10: 11: 0: 1: n: n: n: Description No change Sub–channel organization change Service organization change Sub–channel & service organization change Alarm messages not accessible Alarm messages accessible CIF counter higher part (modulo 20) CIF counter lower part (modulo 250) Value for CIFCL, from which the new configuration is valid AF CIFCH(4..0) CIFCL(7..0) OC(7..0) Alarm flag CIF counter (higher part) CIF counter (lower part) Occurrence change Rev. A1, 22-May-01 37 (69) U2739M-B 8.1.6 Set Current SBCHID Long Form Command Settings Overview: D Set current sub–channel parameters (long form) Command sequence: Address Mode 7 0 6 1 DAB 5 1 4 0 3 1 U2739M-B 2 1 1 1 0 0 $6E Write Command Data Mode 7 0 6 0 5 0 4 1 3 0 2 1 1 0 0 0 $14 Address Mode 7 0 6 1 DAB 5 1 4 0 3 1 U2739M-B 2 1 1 0 0 0 $6C Write Command Data Mode 7 ON 6 SCEFC 5 4 3 SBCHID 2 1 0 $XX $XX CU(9..8) $XX $XX SCU(9..2) SCU(1..0) EP EPPAR CU(7..0) 38 (69) Rev. A1, 22-May-01 U2739M-B Command Parameters: Parameter ON SCEFC SBCHID(5..0) SCU(9..0) EP EPPAR(2..0) Meaning Sub–channel on/off switch 0: 1: Single sub–channel for EFC sub–channel identifier Start CU for SBCHID Error Protection Error Protection parameters 0: 1: n: n: 0: 1: Description Switch sub–channel off Switch sub–channel on Single sub–channel for EFC remains unchanged Set SBCHID as single sub–channel for EFC Sub–channel ID Start CU address (0..863) UEP EEP If EP = 0 (UEP): 000: Protection level P 1 001: Protection level P 2 010: Protection level P 3 011: Protection level P 4 100: Protection level P 5 If EP = 1 (EEP): 0xx: EEP long form option 0 (protection level xx–A) 00: Protection level 1–A (code rate 2/8) 01: Protection level 2–A (code rate 3/8) 10: Protection level 3–A (code rate 4/8) 11: Protection level 4–A (code rate 6/8) 1xx: EEP long form option 1 (protection level xx–B) 00: Protection level 1–B (code rate 4/9) 01: Protection level 2–B (code rate 4/7) 10: Protection level 3–B (code rate 4/6) 11: Protection level 4–B (code rate 4/5) Sub–channel size in CU’s (4..864) CU(9..0) Sub–channel size (number of CU’s) n: Rev. A1, 22-May-01 39 (69) U2739M-B 8.1.7 Set Next SBCHID Long Form Command Settings Overview: D Set next sub–channel parameters Command sequence: Address Mode 7 0 6 1 DAB 5 1 4 0 3 1 U2739M-B 2 1 1 1 0 0 $6E Write Command Data Mode 7 0 6 0 5 0 4 1 3 0 2 1 1 0 0 1 $15 Address Mode 7 0 6 1 DAB 5 1 4 0 3 1 U2739M-B 2 1 1 0 0 0 $6C Write Command Data Mode 7 ON 6 SCEFC 5 4 3 SBCHID 2 1 0 $XX $XX CU(9..8) $XX $XX SCU(9..2) SCU(1..0) EP EPPAR CU(7..0) 40 (69) Rev. A1, 22-May-01 U2739M-B Command Parameters: Parameter ON SCEFC SBCHID(5..0) SCU(9..0) EP EPPAR(2..0) Meaning Sub–channel on/off switch 0: 1: Single sub–channel for EFC Sub–channel identifier Start CU for SBCHID Error Protection Error Protection parameters 0: 1: n: n: 0: 1: Description Switch sub–channel off Switch sub–channel on Single sub–channel for EFC remains unchanged Set SBCHID as single sub–channel for EFC Sub–channel ID Start CU address (0..863) UEP EEP If EP = 0 (UEP): 000: Protection level P 1 001: Protection level P 2 010: Protection level P 3 011: Protection level P 4 100: Protection level P 5 If EP = 1 (EEP): 0xx: EEP long form option 0 (protection level xx–A) 00: Protection level 1–A (code rate 2/8) 01: Protection level 2–A (code rate 3/8) 10: Protection level 3–A (code rate 4/8) 11: Protection level 4–A (code rate 6/8) 1xx: EEP long form option 1 (protection level xx–B) 00: Protection level 1–B (code rate 4/9) 01: Protection level 2–B (code rate 4/7) 10: Protection level 3–B (code rate 4/6) 11: Protection level 4–B (code rate 4/5) Sub–channel size in CU’s (4..864) CU(9..0) Sub–channel size (number of CU’s) n: Rev. A1, 22-May-01 41 (69) U2739M-B 8.1.8 Set Current SBCHID Short Form Command Settings Overview: D Set current sub–channel parameters (short form) Command sequence: Address Mode 7 0 6 1 DAB 5 1 4 0 3 1 U2739M-B 2 1 1 1 0 0 $6E Write Command Data Mode 7 0 6 0 5 0 4 1 3 0 2 1 1 1 0 0 $16 Address Mode 7 0 6 1 DAB 5 1 4 0 3 1 U2739M-B 2 1 1 0 0 0 $6C Write Command Data Mode 7 ON 6 SCEFC 5 4 3 SBCHID 2 1 0 $XX Command Parameters: Parameter ON SCEFC SBCHID(5..0) Meaning Sub–channel on/off switch 0: 1: Single sub–channel for EFC Sub–channel identifier 0: 1: n: Description Switch sub–channel off Switch sub–channel on Single sub–channel for EFC remains unchanged Set SBCHID as single sub–channel for EFC Sub–channel ID 42 (69) Rev. A1, 22-May-01 U2739M-B 8.2 8.2.1 ’Set Configuration’ Commands Set Global Configuration D Set channel decoder AGC values D Set channel decoder global parameters Command sequence: Address Mode 7 0 6 1 DAB 5 1 4 0 3 1 U2739M-B 2 1 1 1 0 0 $6G Command Settings Overview: Write Command Data Mode 7 0 6 0 5 1 4 0 3 0 2 0 1 0 0 0 $00 Address Mode 7 0 6 1 DAB 5 1 4 0 3 1 U2739M-B 2 1 1 0 0 0 $6C Write Command Data Mode 7 AGCV CDPV 6 0 IFM 5 dB3 FSYS 4 DSC 3 2 1 PSC(10..8) 0 $XX $XX $XX PSC(7..0) SAW ADCF 0 Command Parameters: Parameter AGCV DSC(1..0) PSC(10..0) CDPV IFM FSYS Meaning AGC values valid Input data scale Programmable (I)FFT scale Channel decoder parameters valid IF input signal mode Frame synchronization sensitivity level 0: 1: n: n: 0: 1: 0: 1: 00: 01: 10: 11: 0: 1: 0: 1: Description Following DSC/PSC values ignored Following DSC/PSC values valid Scale value Scale value Following global parameters ignored Following global parameters valid Common IF representation Reverse IF representation Very high High Low Very low Equalization off Equalization on Binary ADC input format 2’s complement ADC input format 1 01 Defaults SAW ADCF SAW filter equalization switch ADC format 1 0 Rev. A1, 22-May-01 43 (69) U2739M-B 8.2.2 Set TS Configuration Command Settings Overview: D Set TS post processing parameters Command sequence: Address Mode 7 0 6 1 DAB 5 1 4 0 3 1 U2739M-B 2 1 1 1 0 0 $6E Write Command Data Mode 7 0 6 0 5 1 4 0 3 0 2 0 1 0 0 1 $21 Address Mode 7 0 6 1 DAB 5 1 4 0 3 1 U2739M-B 2 1 1 0 0 0 $6C Write Command Data Mode 7 PARV 6 COV 5 PKS 4 TMIN CIRTH NSTH GFCH GFCL 3 2 ISPCnt 1 0 $XX $XX $XX $XX $XX $XX 44 (69) Rev. A1, 22-May-01 U2739M-B Command Parameters: Parameter PARV COV PKS ISPCnt TMIN(7..0) CIRTH(7..0) Meaning CIR post processing parameters valid (PKS / AVG / CIRTH / NSTH / TMIN) CIR post processing filter coefficients valid Number of peaks required for ’CIR correct’ indication CIR post processing average CIR minimum dT output CIR threshold 0: 1: 0: 1: 2n : n: n: n.n: Description Parameters not valid Following parameters valid Coefficients not valid following coefficients valid Required peaks CIR output average over n+1 values Minimum dT output after CIR post processing (* 488 ns) – Threshold value for CIR peak detection (format: 4.4 bit) – Will be multiplied by ? (standard deviation) – Noise threshold value (8 bit unsigned) – Will be multiplied by 32 0 0 0 3.0 Defaults NSTH(7..0) Noise threshold n: 0 B0(15..0) IIR filter coefficients Coefficients for 1st order IIR filter used for CIR post processing (Q15 format required) 0.5 0.5 0 Rev. A1, 22-May-01 45 (69) U2739M-B 8.2.3 Set FS Configuration Command Settings Overview: D Set FS post processing parameters Command sequence: Address Mode 7 0 6 1 DAB 5 1 4 0 3 1 U2739M-B 2 1 1 1 0 0 $6E Write Command Data Mode 7 0 6 0 5 1 4 0 3 0 2 0 1 1 0 0 $22 Address Mode 7 0 6 1 DAB 5 1 4 0 3 1 U2739M-B 2 1 1 0 0 0 $6C Write Command Data Mode 7 6 5 4 GA THA GB THB GC F2FT 3 2 1 0 $XX $XX $XX $XX $XX $XX Command Parameters: Parameter GA(7..0) THA(7..0) GB(7..0) THB(7..0) GC(7..0) F2FT(7..0) Meaning Area A gradient Area A threshold Area B gradient Area B threshold Area C gradient Max. frame–to–frame tolerance n: n: n: n: n: n: Description Fractional part Fractional part Fractional part Fractional part Fractional part Maximum frequency shift in carriers (format: 3.5 bit) Defaults 0.03125 0.03125 0.125 0.25 0.5 1.0 46 (69) Rev. A1, 22-May-01 U2739M-B 8.2.4 Set XO Configuration Command Settings Overview: D Set XO control parameters Command sequence: Address Mode 7 0 6 1 DAB 5 1 4 0 3 1 U2739M-B 2 1 1 1 0 0 $6E Write Command Data Mode 7 0 6 0 5 1 4 0 3 0 2 0 1 1 0 1 $23 Address Mode 7 0 6 1 DAB 5 1 4 0 3 1 U2739M-B 2 1 1 0 0 0 $6C Write Command Data Mode 7 6 5 4 3 2 1 0 $XX $XX XO_Rough line XO_Fine line XOAVG 0 $XX Command Parameters: Parameter XO_B0(15..0) XO_B1(15..0) XO_B2(15..0) XO_A1(15..0) XO_A2(15..0) XOAVG(4..0) Meaning IIR filter coefficients Coefficients for control Description 2nd order IIR filter used for XO Defaults 0.25 0.5 0.25 0 0 0 XO control average n: XO control average over n+1 values Rev. A1, 22-May-01 47 (69) U2739M-B 8.2.5 Set HSSO / RS232 Configuration Command Settings Overview: D Set HSSO parameters D Set RS232 parameters Command sequence: Address Mode 7 0 6 1 DAB 5 1 4 0 3 1 U2739M-B 2 1 1 1 0 0 $6E Write Command Data Mode 7 0 6 0 5 1 4 0 3 0 2 1 1 0 0 0 $00 Address Mode 7 0 6 1 DAB 5 1 4 0 3 1 U2739M-B 2 1 1 0 0 0 $6C Write Command Data Mode 7 HCLK 6 5 HCIRL 4 0 3 HPAD 2 HDD2 1 HDD1 RSSEL 0 HCIR $XX $XX RSBAUD Command Parameters: Parameter HCLK(1..0) HCIRL(1..0) Meaning HSSO bit clock HSSO CIR output length 00: 0.768 MHz 01: 1.536 MHz Description 10: 3.072 MHz 11: 6.144 MHz 00: N values (DAB system mode dependent) 01: N/2 1x: N/4 0: No PAD output via HSSO 1: PAD output 0: No DD2 output via HSSO 1: DD2 output 0: No DD1 output via HSSO 1: DD1 output 0: No CIR output via HSSO 1: CIR output 00: 19200 baud 01: 38400 baud 00: 01: 10: 11: no output DD1 DD2 PAD 10: 57600 baud 11: 115200 baud HPAD HDD2 HDD1 HCIR RSBAUD(1..0) RSSEL(1..0) HSSO PAD output switch HSSO DD2 output switch HSSO DD1 output switch HSSO CIR output switch RS232 baud rate RS232 output selection 48 (69) Rev. A1, 22-May-01 U2739M-B Command Parameters: Parameter UFS UFSP UTSP UXOC UDD1 UDD2 UPAD UTII UAMD ... UNMI Meaning USE FS module USE FS post processing module USE TS post processing module USE XO control module USE DD1 module USE DD2 module USE PAD extraction module USE TII module Reserved 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: Description Internal set2 XTFPR module used External USE module used Internal set2 module used External USE module used Internal set2 module used External USE module used Internal set2 module used External USE module used Internal set2 module used External USE module used Internal set2 module used External USE module used Internal set2 module used External USE module used Internal set2 module used External USE module used Rev. A1, 22-May-01 49 (69) U2739M-B 8.2.6 Set WAGC Configuration Command Settings Overview: D Set WAGC rising edge / falling edge parameters Command sequence: Address Mode 7 0 6 1 DAB 5 1 4 0 3 1 U2739M-B 2 1 1 1 0 0 $6E Write Command Data Mode 7 0 6 0 5 1 4 0 3 0 2 1 1 1 0 0 $26 Address Mode 7 0 6 1 DAB 5 1 4 0 3 1 U2739M-B 2 1 1 0 0 0 $6C Write Command Data Mode 7 6 5 4 3 WS 2 0 1 0 WV $XX $XX $XX $XX $XX WRISE(3..0) WFALL(1..0) WRISE(11..4) WRISE(17..12) WFALL(9..2) WFALL(17..10) Command Parameters: Parameter WV WRISE(17..0) WFALL(17..0) Meaning WAGC values valid WAGC rising edge time marker WAGC falling edge time marker 0: 1: n: n: Description use default WAGC values use following WAGC values value for WAGC rising edge value for WAGC falling edge 50 (69) Rev. A1, 22-May-01 U2739M-B 8.2.7 Set RCC Slot Configuration Command Settings Overview: D Set RCC slot data Command sequence: Address Mode 7 0 6 1 DAB 5 1 4 0 3 1 U2739M-B 2 1 1 1 0 0 $6E Write Command Data Mode 7 0 6 0 5 1 4 0 3 0 2 1 1 1 0 1 $27 Address Mode 7 0 6 1 DAB 5 1 4 0 3 1 U2739M-B 2 1 1 0 0 0 $6C Write Command Data Mode 7 6 5 4 3 2 1 0 $XX $XX $XX $XX $XX $XX $XX $XX RCC(7..0) RCC(15..8) RCC(23..16) RCC(31..24) RCC(39..32) RCC(47..40) RCC(55..48) RCC(63..56) Command Parameters: Parameter RCC(63..0) Meaning RCC slot data Description Rev. A1, 22-May-01 51 (69) U2739M-B 8.2.8 Set RFU Command Settings Overview: D Set RFU parameters Command sequence: Address Mode 7 0 6 1 DAB 5 1 4 0 3 1 U2739M-B 2 1 1 1 0 0 $6E Write Command Data Mode 7 0 6 0 5 1 4 1 3 0 2 0 1 0 0 0 $30 Address Mode 7 0 6 1 DAB 5 1 4 0 3 1 U2739M-B 2 1 1 0 0 0 $6C Write Command Data Mode 7 6 5 4 3 2 1 0 $XX $XX $XX $XX $XX $XX $XX $XX $XX $XX $XX $XX (reserved) (reserved) (reserved) (reserved) RFU4 RFU5 RFU6 ... ... RFU42 RFU43 RFU44 Command Parameters: Parameter (reserved) RFU4..44 Meaning Description Reserved for internal use (Atmel Wireless & Microcontrollers will deliver default values, if necessary) Reserved for future use 52 (69) Rev. A1, 22-May-01 U2739M-B 8.3 8.3.1 ’Read Status’ Commands Read Global Status D Get synchronization status D Get AGC information Command sequence: Address Mode 7 0 6 1 DAB 5 1 4 0 3 1 U2739M-B 2 1 1 1 0 1 $6F Command Overview: D Get DAB system mode D Get OAK core operating mode Write Command Data Mode 7 0 6 1 5 0 4 0 3 0 2 0 1 0 0 0 $40 Address Mode 7 0 6 1 DAB 5 1 4 0 3 1 U2739M-B 2 1 1 0 0 1 $6D Write Command Data Mode 7 6 0 5 4 CIRS PSLI P(7..0) 3 MV CCIR 2 FSLI IDSL 1 SLI CAFC 0 WDSP P(8) $XX $XX $XX $XX DABMODE 0 OAKMODE Rev. A1, 22-May-01 53 (69) U2739M-B Command Parameters: Parameter DABMODE(1..0) Meaning DAB system mode 00: 01: 10: 11: 00: 01: 10: 11: Description DAB system mode 4 DAB system mode 1 DAB system mode 2 DAB system mode 3 Normal stand–alone USE boot mode XUSE boot mode HOST boot mode OAKMODE(1..0) OAK operating mode MV FSLI SLI CIRS CCIR(1..0) MODE_VALID line status FSLI line status SLI line status CIR status Coded CIR status 0: 1: 00: 01: 10: 11: 00: 01: 10: 11: No CIR detected CIR correct |average| ? N/64 N/64 < |average| ? N/8 |average| > N/4 rfu. |dFFRAME | ? TA TA < |dFFRAME | ? TB TB < |dFFRAME |< 16 kHz |dFFRAME | ? 16 kHz CAFC(1..0) Coded AFC status PSLI(3..0) Precise signal level information Input data signal level 0000: Very weak signal ... 1111: Very strong signal 00: 01: 10: 11: Weak input signal Typical input signal Strong input signal rfu. IDSL(1..0) P(8..0) WDSP Calculated in–band power Watchdog DSP Toggels every 24 ms from 0 to 1 54 (69) Rev. A1, 22-May-01 U2739M-B 8.3.2 Read Synchronization Status Command Overview: D Get TS control value D Get FS control value Command sequence: Address Mode 7 0 6 1 DAB 5 1 4 0 3 1 U2739M-B 2 1 1 1 0 1 $6F Write Command Data Mode 7 0 6 1 5 0 4 0 3 0 2 0 1 0 0 1 $41 Address Mode 7 0 6 1 DAB 5 1 4 0 3 1 U2739M-B 2 1 1 0 0 1 $6D Write Command Data Mode 7 DT(1..0) 6 5 0 4 DT(9..2) 3 2 1 0 $XX $XX $XX $XX DF(19..16) DF(15..8) DF(7..0) Command Parameters: Parameter DT(9..0) DF(19..0) Meaning Detected time deviation Detected channel frequency deviation n: n: Description Cycle count (signed, @2.048 MHz) 1) Deviation in carriers (signed, Q11 format) 1) Signed values refers to virtual zero at Tguard/2 Rev. A1, 22-May-01 55 (69) U2739M-B 8.3.3 Read CIR Status Command Overview: D Get CIR post processing results 1) Command sequence: Address Mode 7 0 6 1 DAB 5 1 4 0 3 1 U2739M-B 2 1 1 1 0 1 $6F Write Command Data Mode 7 0 6 1 5 0 4 0 3 0 2 0 1 1 0 0 $42 Address Mode 7 0 6 1 DAB 5 1 4 0 3 1 U2739M-B 2 1 1 0 0 1 $6D Write Command Data Mode 7 6 5 4 3 2 1 0 $XX $XX $XX $XX $XX $XX P_FIRST(15..8) P_FIRST(7..0) P_AGV(15..8) P_AGV(7..0) P_LAST(15..8) P_LAST(7..0) Command Parameters: Parameter P_FIRST(15..0) P_AVG(15..0) P_LAST(15..0) 1) 2) Index of 1st Meaning CIR peak above CIR threshold n: n: n: Index of CIR average value Index of last CIR peak above CIR threshold Description Cycle count (signed, @2.048 MHz) Cycle count (signed, @2.048 MHz) Cycle count (signed, @2.048 MHz) 2) If time synchronization has lost all values are set to $8000 ! Signed values refers to zero at Tguard/2 56 (69) Rev. A1, 22-May-01 U2739M-B 8.4 8.4.1 ’Read Data’ Commands Read ASD Header Data Command Overview: D Get MPEG audio header Command sequence: Address Mode 7 0 6 1 DAB 5 1 4 0 3 1 U2739M-B 2 1 1 1 0 1 $6F Write Command Data Mode 7 0 6 1 5 0 4 1 3 0 2 0 1 0 0 0 $50 Address Mode 7 0 6 1 DAB 5 1 4 0 3 1 U2739M-B 2 1 1 0 0 1 $6D Write Command Data Mode 7 6 5 4 3 2 1 0 $XX $XX $XX $XX MPG_HW1(15..8) MPG_HW1(7..0) MPG_HW2(15..8) MPG_HW2(7..0) Command Parameters: Parameter MPG_HW1(15..0) MPG_HW2(15..0) 2nd Meaning 1st MPEG header word MPEG header word Description Sync. word ($FFFx) expected MPEG stream signature Rev. A1, 22-May-01 57 (69) U2739M-B 8.4.2 Read X–PAD Command Overview: D Get MPEG ancillary data (X–PAD) Command sequence: Address Mode 7 0 6 1 DAB 5 1 4 0 3 1 U2739M-B 2 1 1 1 0 1 $6F Write Command Data Mode 7 0 6 1 5 0 4 1 3 0 2 1 XPNUM 0 $5X Address Mode 7 0 6 1 DAB 5 1 4 0 3 1 U2739M-B 2 1 1 0 0 1 $6D Write Command Data Mode 7 6 5 4 X–PAD0 ... 3 2 1 0 $XX $XX X–PAD31 Command Parameters: Parameter XPNUM Meaning X–PAD block number n (n from 1..5) Description The maximum X–PAD capacity supported by the U2739M-B is 64kbit/s. The access is splitted into 6 blocks (numbered 1..5) of 32 bytes. The blocks are time aligned, that means block 1 is the first block in an MPEG frame after audio samples. Byte 0 is the first byte of block n, byte 31 the last one. It is followed by the first one of block n+1. Use MC command “RFU” to read block 6 X–PADm X–PAD byte m Read RFU 58 (69) Rev. A1, 22-May-01 U2739M-B 8.4.3 Read F–PAD Command Overview: D Get MPEG ancillary data (F–PAD) Command sequence: Address Mode 7 0 6 1 DAB 5 1 4 0 3 1 U2739M-B 2 1 1 1 0 1 $6F Write Command Data Mode 7 0 6 1 5 0 4 1 3 1 2 0 1 0 0 0 $58 Address Mode 7 0 6 1 DAB 5 1 4 0 3 1 U2739M-B 2 1 1 0 0 1 $6D Write Command Data Mode 7 6 5 4 F–PAD0 F–PAD1 3 2 1 0 $XX $XX Command Parameters: Parameter F–PAD0 F–PAD1 Meaning F–PAD byte 0 F–PAD byte 1 Description Rev. A1, 22-May-01 59 (69) U2739M-B 8.4.4 Read AIC Data Command Overview: D Get AIC data Command sequence: Address Mode 7 0 6 1 DAB 5 1 4 0 3 1 U2739M-B 2 1 1 1 0 1 $6F Write Command Data Mode 7 0 6 1 5 1 4 0 3 2 1 0 $6X AICNUM Address Mode 7 0 6 1 DAB 5 1 4 0 3 1 U2739M-B 2 1 1 0 0 1 $6D Write Command Data Mode 7 6 5 4 AIC0 ... AIC31 3 2 1 0 $XX $XX Command Parameters: Parameter AICNUM Meaning Description AIC block number n The maximum AIC capacity is 512 bytes. The access is splitted into 16 blocks (numbered 0..15) of 32 bytes. The blocks are time aligned, that means block 0 is the first filled block. AIC byte m Byte 0 is the first byte of block n, byte 31 the last one. It is followed by the first one of block n+1. AICm 60 (69) Rev. A1, 22-May-01 U2739M-B 8.4.5 Read TII Data Command Overview: D Get TII data Command sequence: Address Mode 7 0 6 1 DAB 5 1 4 0 3 1 U2739M-B 2 1 1 1 0 1 $6F Write Command Data Mode 7 0 6 1 5 1 4 1 3 0 2 0 1 TIINUM 0 $7X Address Mode 7 0 6 1 DAB 5 1 4 0 3 1 U2739M-B 2 1 1 0 0 1 $6D Write Command Data Mode 7 6 5 4 TII0 ... TII31 3 2 1 0 $XX $XX Command Parameters: Parameter TIINUM Meaning TII block number n Description The maximum TII capacity is 128 bytes. The access is splitted into 4 blocks (numbered 0..3) of 32 bytes. The blocks are time aligned, that means block 0 is the first filled block. Byte 0 is the first byte of block n, byte 31 the last one. It is followed by the first one of block n+1. TIIm TII byte m Rev. A1, 22-May-01 61 (69) U2739M-B 8.4.6 Read EFC Data Command Overview: D Get EFC data Command sequence: Address Mode 7 0 6 1 DAB 5 1 4 0 3 1 U2739M-B 2 1 1 1 0 1 $6F Write Command Data Mode 7 1 6 0 5 0 4 0 3 0 2 0 1 EFCSEL 0 $8X Address Mode 7 0 6 1 DAB 5 1 4 0 3 1 U2739M-B 2 1 1 0 0 1 $6D Write Command Data Mode 7 6 5 4 3 2 1 0 $XX $XX EFC(7..0) EFC(15..8) Command Parameters: Parameter EFCSEL EFC(15..0) Meaning EFC selection EFC value for chosen application 00: 01: n: Description EFC of FIC EFC of all MSC applications EFC value summarized over... ... 12 FIB’s (DAB mode 1) ... 3 FIB’s (DAB mode 2) ... 4 FIB’s (DAB mode 3) ... 6 FIB’s (DAB mode 4) 62 (69) Rev. A1, 22-May-01 U2739M-B 8.4.7 Read FIC Data D Get FIB bytes Command sequence: Address Mode 7 0 6 1 DAB 5 1 4 0 3 1 U2739M-B 2 1 1 1 0 1 $6F Command Overview: Write Command Data Mode 7 1 6 0 5 0 4 1 3 2 1 0 $9X FIBNUM Address Mode 7 0 6 1 DAB 5 1 4 0 3 1 U2739M-B 2 1 1 0 0 1 $6D Write Command Data Mode 7 6 5 4 FIB0 ... FIB31 3 2 1 0 $XX $XX Command Parameters: Parameter FIBNUM Meaning FIB number n Description Possible FIB numbers DAB mode dependent: 0..11 (DAB mode 1) 0..2 (DAB mode 2) 0..3 (DAB mode 3) 0..5 (DAB mode 4) Each FIB consists of 32 bytes. The order of the FIB bytes and bits corresponds to the serial FIC processing. That means: (1) Byte order: The first 8 output bits after FIC processing represent FIB byte 0 of FIB number 0, the next ones FIB byte 1 of FIB number 0 and so on. (2) Bit order: The FIB bytes are given out MSB first. The first outgoing bit represents bit 7 of the corresponding byte, the next one bit 6 and so on. The FIB bits are numbered from bit 0 (MSB of FIB0) up to bit 255 (LSB of FIB31). NOTE: The last 2 bytes of an FIB represent the result of the U2739M internal CRC check. That means, if these bytes are $00 both, the internal CRC check was successful and the FIB data bytes are correct. FIBm FIB byte m Rev. A1, 22-May-01 63 (69) U2739M-B 8.4.8 Read RCC Slot Command Overview: D Get RCC slot data Command sequence: Address Mode 7 0 6 1 DAB 5 1 4 0 3 1 U2739M-B 2 1 1 1 0 1 $6F Write Command Data Mode 7 1 6 0 5 1 4 0 3 0 2 0 1 0 0 0 $A0 Address Mode 7 0 6 1 DAB 5 1 4 0 3 1 U2739M-B 2 1 1 0 0 1 $6D Write Command Data Mode 7 6 5 4 3 2 1 0 $XX $XX $XX $XX $XX $XX $XX $XX RCC(7..0) RCC(15..8) RCC(23..16) RCC(31..24) RCC(39..32) RCC(47..40) RCC(55..48) RCC(3..56) Command Parameters: Parameter RCC(63..0) Meaning RCC slot data Description 64 (69) Rev. A1, 22-May-01 U2739M-B 8.4.9 Read Slot Pointer Command Overview: D Get RCC RX/TX slot pointer Command sequence: Address Mode 7 0 6 1 DAB 5 1 4 0 3 1 U2739M-B 2 1 1 1 0 1 $6F Write Command Data Mode 7 1 6 0 5 1 4 0 3 0 2 0 1 0 0 1 $A1 Address Mode 7 0 6 1 DAB 5 1 4 0 3 1 U2739M-B 2 1 1 0 0 1 $6D Write Command Data Mode 7 6 TXPTR 5 4 3 2 RXPTR 1 0 $XX Command Parameters: Parameter RXPTR(3..0) TXPTR(3..0) Meaning RCC RX slot pointer RCC TX slot pointer Description Rev. A1, 22-May-01 65 (69) U2739M-B 8.4.10 Read RFU Command Overview: D Get RFU data Command sequence: Address Mode 7 0 6 1 DAB 5 1 4 0 3 1 U2739M-B 2 1 1 1 0 1 $6F Write Command Data Mode 7 1 6 0 5 1 4 1 3 0 2 0 1 0 0 0 $9X Address Mode 7 0 6 1 DAB 5 1 4 0 3 1 U2739M-B 2 1 1 0 0 1 $6D Write Command Data Mode 7 6 5 4 RFU0 ... RFU43 3 2 1 0 $XX $XX Command Parameters: Parameter XPAD0..31 RFU0..11 Meaning XPAD block 6 Description See: read XPAD command Reserved for future use 66 (69) Rev. A1, 22-May-01 U2739M-B 9 Package Information Rev. A1, 22-May-01 67 (69) U2739M-B 68 (69) Rev. A1, 22-May-01 U2739M-B Ozone Depleting Substances Policy Statement It is the policy of Atmel Germany GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (ODSs). The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. Atmel Germany GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency (EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively. Atmel Germany GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances. We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use Atmel Wireless & Microcontrollers products for any unintended or unauthorized application, the buyer shall indemnify Atmel Wireless & Microcontrollers against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. Data sheets can also be retrieved from the Internet: http://www.atmel–wm.com Atmel Germany GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 (0)7131 67 2594, Fax number: 49 (0)7131 67 2423 Rev. A1, 22-May-01 69 (69)